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1. 发明授权

US5453636A MOS SRAM cell with open base bipolar loads 失效
标题翻译：具有开路基极双极性负载的MOS SRAM单元
公开(公告)号：US5453636A
公开(公告)日：1995-09-26
申请号：US291252
申请日：1994-08-16
申请人： Boaz Eitan , Alexander Shubat
发明人： Boaz Eitan , Alexander Shubat
IPC分类号： H01L27/11 , H01L27/02
CPC分类号： H01L27/11 , Y10S257/903
摘要： An SRAM cell includes an open-base, bipolar transistor serving as a load device and one pull-down transistor having an associated leakage current. The amplification .beta. of the bipolar transistor controls the amount of load current through the bipolar transistor. The bipolar transistor provides the necessary load current to ensure the SRAM cell maintains its logic state.
摘要翻译： SRAM单元包括用作负载器件的开放式双极晶体管和具有相关联的漏电流的一个下拉晶体管。双极晶体管的放大率β控制通过双极晶体管的负载电流量。双极晶体管提供必要的负载电流，以确保SRAM单元保持其逻辑状态。

2. 发明授权

US06646933B1 Method and apparatus to reduce the amount of redundant memory column and fuses associated with a memory device 有权
标题翻译：用于减少与存储器件相关联的冗余存储器列和熔丝的量的方法和装置
公开(公告)号：US06646933B1
公开(公告)日：2003-11-11
申请号：US10210525
申请日：2002-07-31
申请人： Alexander Shubat , Niranjan Behera , Izak Kense
发明人： Alexander Shubat , Niranjan Behera , Izak Kense
IPC分类号： G11C700
CPC分类号： G11C29/846 , G11C29/808
摘要： A method, system, and apparatus exist which couple a first group of non-redundant memory columns to a non-redundant input-output circuit and couple a second group of redundant memory columns to a redundant input-output circuit. A fewer amount of memory columns exist in the second group of redundant memory columns than in the first of non-redundant memory columns. A first fuse indicates whether one or more memory columns are defective in a group of non-redundant memory columns coupled to the non-redundant input output circuit. Also, a second fuse couples to a first circuit. The first circuit identifies which sub-input circuit is coupled to the one or more defective memory columns.
摘要翻译：存在一种将第一组非冗余存储器列耦合到非冗余输入 - 输出电路并将第二组冗余存储器列耦合到冗余输入 - 输出电路的方法，系统和装置。在第二组冗余存储器列中存储的内存列数量少于非冗余存储器列中的第一组。第一个熔丝指示耦合到非冗余输入输出电路的一组非冗余存储器列中的一个或多个存储器列是否有缺陷。另外，第二保险丝耦合到第一电路。第一电路识别哪个子输入电路耦合到一个或多个有缺陷的存储器列。

3. 发明授权

US07904766B1 Statistical yield of a system-on-a-chip 有权
标题翻译：片上系统的统计收益率
公开(公告)号：US07904766B1
公开(公告)日：2011-03-08
申请号：US11951338
申请日：2007-12-06
申请人： Niranjan Behera , Alexander Shubat
发明人： Niranjan Behera , Alexander Shubat
IPC分类号： G11C29/00 , G01R31/30 , G06F11/00
CPC分类号： G11C29/4401 , G11C29/028 , G11C29/50 , G11C29/76 , G11C2029/0401
摘要： Improving statistical yield of a system-on-a-chip. The system-on-a-chip includes several memory systems. Each memory system includes a large number of memories. The memories are tested to identify any faulty memories. One or more margins of the faulty memories are then varied and the memories are then tested again.
摘要翻译：提高片上系统的统计收益。片上系统包括多个存储系统。每个存储器系统包括大量的存储器。测试记忆以识别任何错误的记忆。然后改变故障存储器的一个或多个边缘，然后再次测试存储器。

4. 发明授权

US07692964B1 Source-biased SRAM cell with reduced memory cell leakage 有权
标题翻译：源偏置SRAM单元，具有减少的存储单元泄漏
公开(公告)号：US07692964B1
公开(公告)日：2010-04-06
申请号：US11451043
申请日：2006-06-12
申请人： Deepak Sabharwal , Alexander Shubat
发明人： Deepak Sabharwal , Alexander Shubat
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C11/417
摘要： A Static Random Access Memory (SRAM) cell having a source-biasing mechanism for leakage reduction. In standby mode, the cell's wordline is deselected and a source-biasing potential is provided to the cell. In read mode, the wordline is selected and responsive thereto, the source-biasing potential provided to the cell is deactivated. Upon completion of reading, the source-biasing potential is re-activated.
摘要翻译：一种具有用于泄漏减少的源偏置机构的静态随机存取存储器（SRAM）单元。在待机模式下，取消选择单元格的字线，并向单元提供源偏置电位。在读取模式中，字线被选择并响应于此，提供给单元的源偏置电位被去激活。读取完成后，源偏置电位被重新激活。

5. 发明授权

US06392957B1 Fast read/write cycle memory device having a self-timed read/write control circuit 有权
标题翻译：具有自定时读/写控制电路的快速读/写周期存储器件
公开(公告)号：US06392957B1
公开(公告)日：2002-05-21
申请号：US09728377
申请日：2000-11-28
申请人： Alexander Shubat , Adam Kablanian , Jaroslav Raszka , Richard S. Roy
发明人： Alexander Shubat , Adam Kablanian , Jaroslav Raszka , Richard S. Roy
IPC分类号： G11C722
CPC分类号： G11C7/227 , G11C7/22 , G11C2207/104
摘要： A self-timed write control memory device minimizes the memory cycle time for the cells of the array. The self-timed write control memory device preferably comprises an X-decoder, a word-line driver, a memory cell array, control logic, pre-charge circuits, sense amplifiers, a reference decoder, and a reference word-line driver. The memory device preferably further includes a first reference cell, a second reference cell or logic, a first reference column, a second reference column and a reference sense amplifier. The first reference cell is preferably used for detection of read cycle completion and the second reference cell or logic is used for detection of write cycle completion. The output of the first reference cell and second reference cell are preferably coupled to inputs of a unique reference sense amplifier. The sense amplifier includes special circuitry that uses either the output of the first reference cell or the second reference cell to generate the self-timed clock and there by minimizes the memory cycle time. The second reference cell may be any one of a conventional memory cell or write reference logic.
摘要翻译：自定时的写入控制存储器件最小化阵列的单元的存储器周期时间。自定时写控制存储器件优选地包括X解码器，字线驱动器，存储单元阵列，控制逻辑，预充电电路，读出放大器，参考解码器和参考字线驱动器。存储器件优选地还包括第一参考单元，第二参考单元或逻辑，第一参考列，第二参考列和参考读出放大器。第一参考单元优选地用于检测读周期完成，并且第二参考单元或逻辑用于检测写周期完成。第一参考单元和第二参考单元的输出优选地耦合到唯一参考读出放大器的输入。读出放大器包括专用电路，其使用第一参考单元或第二参考单元的输出来产生自定时钟，并且通过使存储器周期时间最小化。第二参考单元可以是常规存储单元或写入参考逻辑中的任何一个。

6. 发明授权

US6051031A Module-based logic architecture and design flow for VLSI implementation 失效
标题翻译：基于模块的逻辑架构和VLSI实现的设计流程
公开(公告)号：US6051031A
公开(公告)日：2000-04-18
申请号：US795580
申请日：1997-02-05
申请人： Alexander Shubat , Adam Kablanian , Vardan Duvalyan
发明人： Alexander Shubat , Adam Kablanian , Vardan Duvalyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A new design methodology which utilizes a module-based architecture is used to implement customized VLSI designs. In accordance with this invention, the module-based architecture comprises a number of Matrix Transistor Logic (MTL) modules. Each MTL module has a control input buffer section, an output stage section, and a matrix array section. The matrix array section implements logic functions using Pass Transistor Logic technology. Three variables, each of which place a different constraint on the MTL modules, are used in an automated design procedure to implement the MTL modules.
摘要翻译：使用基于模块的架构的新设计方法来实现定制的VLSI设计。根据本发明，基于模块的架构包括许多矩阵晶体管逻辑（MTL）模块。每个MTL模块都有一个控制输入缓冲区，一个输出级区和一个矩阵阵列区。矩阵阵列部分使用通过晶体管逻辑技术实现逻辑功能。在自动设计过程中使用了三个变量，每个变量对MTL模块施加不同的约束，以实现MTL模块。

7. 发明授权

US5402014A Peripheral port with volatile and non-volatile configuration 失效
标题翻译：具有易失性和非易失性配置的外围端口
公开(公告)号：US5402014A
公开(公告)日：1995-03-28
申请号：US91795
申请日：1993-07-14
申请人： Arye Ziklik , Alexander Shubat , Yoram Cedar , John H. Pasternak
发明人： Arye Ziklik , Alexander Shubat , Yoram Cedar , John H. Pasternak
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/17708
摘要： An embodiment of this invention provides an integrated circuit (IC) having a configurable peripheral port which includes an input/output pin, a multiplexer coupled to the input/output pin, volatile configuration bits to control the multiplexer, and non-volatile configuration bits to control the multiplexer and override the volatile configuration bits. One embodiment of an IC also includes a peripheral port as above and functional units, such as programmable array logic (PAL) and erasable programmable read only memory (EPROM), coupled to the multiplexer. In another embodiment, a non-volatile configuration bit from a functional unit configures an input/output pin when the configuration bit is not needed by the functional unit.
摘要翻译：本发明的实施例提供了一种具有可配置外围端口的集成电路（IC），其包括输入/输出引脚，耦合到输入/输出引脚的多路复用器，用于控制多路复用器的易失性配置位，以及非易失性配置位控制多路复用器并覆盖易失性配置位。 IC的一个实施例还包括如上的外围端口和耦合到多路复用器的功能单元，诸如可编程阵列逻辑（PAL）和可擦除可编程只读存储器（EPROM）。在另一个实施例中，当功能单元不需要配置位时，来自功能单元的非易失性配置位配置输入/输出引脚。

8. 发明授权

US4961172A Decoder for a memory address bus 失效
标题翻译：解码器用于存储地址总线
公开(公告)号：US4961172A
公开(公告)日：1990-10-02
申请号：US231122
申请日：1988-08-11
申请人： Alexander Shubat , Yoram Cedar
发明人： Alexander Shubat , Yoram Cedar
IPC分类号： G11C8/12 , G11C8/18
CPC分类号： G11C8/12 , G11C8/18
摘要： A circuit constructed in accordance with my invention includes a microprocessor for generating addresses on an address bus, a plurality of memory devices, and a decoder for decoding the address on the address bus and generating select signals in response thereto. Of importance, the memory devices are also coupled to the address bus. A memory enable circuit is provided for enabling the memory devices before the decoder generates the select signals. Thus, the time required by the decoder to decode address signals does not add to the delay between the time an address is asserted by the microprocessor and the time one of the memory devices responds by providing data. In one embodiment, the memory enable circuit is incorporated into the bit line decoder of the memory devices. Thus, if one of the bit lines of the plurality of memory devices is selected to provide data, the memory device is enabled. Since the word line decoder is generally slower than the bit line decoder, inclusion of the memory enable circuit into the bit line decoder will not slow the memory devices. Also in one embodiment, the bit line decoder is programmable so that the memory devices can be mapped into different blocks of addresses within the microprocessor address space.
摘要翻译：根据本发明构造的电路包括用于在地址总线上产生地址的微处理器，多个存储器件以及用于对地址总线上的地址进行解码并响应于此产生选择信号的解码器。重要的是，存储器件也耦合到地址总线。提供存储器使能电路，用于在解码器产生选择信号之前使存储器件能够使能。因此，解码器解码地址信号所需的时间不会增加微处理器断言的时间与存储器件的时间之一通过提供数据的响应之间的延迟。在一个实施例中，存储器使能电路被并入到存储器件的位线解码器中。因此，如果选择多个存储器件中的一个位线来提供数据，则存储器件被使能。由于字线解码器通常比位线解码器慢，因此将存储器使能电路包括到位线解码器中将不会使存储器件减慢。同样在一个实施例中，位线解码器是可编程的，使得存储器件可以被映射到微处理器地址空间内的不同地址块中。

9. 发明授权

US4939392A Output circuit for driving a memory device output lead including a three-state inverting buffer and a transfer gate coupled between the buffer input lead and the buffer output lead 失效
标题翻译：用于驱动存储器件输出引线的输出电路，其包括耦合在缓冲器输入引线和缓冲器输出引线之间的三态反相缓冲器和传输栅极
公开(公告)号：US4939392A
公开(公告)日：1990-07-03
申请号：US231123
申请日：1988-08-11
申请人： Alexander Shubat , Barmak Sani
发明人： Alexander Shubat , Barmak Sani
IPC分类号： H03K19/0185 , H03K19/094
CPC分类号： H03K19/018557 , H03K19/09429
摘要： A novel circuit is coupled to a memory device sense amplifier and a memory device output pin for driving the output pin with data. The circuit includes a first inverter (18) and a second inverter (100) coupled to the first inverter. Transfer gates (30, 104) are coupled across the input and output leads of the first and second inverters, respectively. During a first mode of operation, the first and second transfer gates are closed and the second inverter is three-stated so that the input and output leads of the first and second inverters are held at a voltage between VCC and ground. When it is desired to drive the memory device output pin with data, the first and second transfer gates open, and the second inverter leaves the three-state mode and goes into a low output impedance mode. Because the input and output leads of the first and second inverters are held at a voltage between VCC and ground when the transfer gates are closed, when the transfer gates open, the delay between the time the transfer gates open and the time valid output data appears on the output lead of the second inverter is minimized. The second inverter comprises large transistors and can therefore provide a large output current. However, because the second inverter is three-stated when the second transfer gate is closed, the circuit draws minimal power when the first and second transfer gates are closed.
摘要翻译：一个新颖的电路耦合到存储器件读出放大器和存储器件输出引脚，用于用数据驱动输出引脚。电路包括耦合到第一反相器的第一反相器（18）和第二反相器（100）。转移门（30,104）分别耦合在第一和第二逆变器的输入和输出引线上。在第一操作模式下，第一和第二传输门关闭，第二反相器是三态的，使得第一和第二反相器的输入和输出引线保持在VCC和地之间的电压。当需要用数据驱动存储器件输出引脚时，第一和第二传输门打开，第二个反相器退出三态模式并进入低输出阻抗模式。由于当传输门关闭时，第一和第二反相器的输入和输出引线保持在VCC和地之间的电压，当传输门打开时，传输门打开时间和时间有效输出数据之间的延迟出现在第二反相器的输出引线上最小化。第二反相器包括大晶体管，因此可以提供大的输出电流。然而，由于当第二传输门关闭时第二反相器是三态的，所以当第一和第二传输门关闭时，电路消耗最小的功率。

10. 发明授权

US07061794B1 Wordline-based source-biasing scheme for reducing memory cell leakage 有权
标题翻译：用于减少内存单元泄漏的基于字词的源偏置方案
公开(公告)号：US07061794B1
公开(公告)日：2006-06-13
申请号：US10813419
申请日：2004-03-30
申请人： Deepak Sabharwal , Alexander Shubat
发明人： Deepak Sabharwal , Alexander Shubat
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C8/08 , G11C11/417
摘要： A source-biasing mechanism for leakage reduction in SRAM. In standby mode, wordlines are deselected and a source-biasing potential is provided to SRAM cells. In read mode, a selected wordline deactivates the source-biasing potential provided to the selected row of SRAM cells, whereas the remaining SRAM cells on the selected bitline column continue to be source-biased.
摘要翻译：用于SRAM中泄漏减少的源偏置机制。在待机模式下，取消选择字线，并向SRAM单元提供源极偏置电位。在读取模式下，所选择的字线禁止提供给所选择的SRAM单元行的源极偏置电位，而所选位线列上的剩余SRAM单元继续源偏置。

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