专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20130242648A1 APPROACH FOR PHASE CHANGE MEMORY CELLS TARGETING DIFFERENT DEVICE SPECIFICATIONS 有权
标题翻译：相位改变记忆细胞的方法，针对不同的设备规格
公开(公告)号：US20130242648A1
公开(公告)日：2013-09-19
申请号：US13421718
申请日：2012-03-15
申请人： Matthew J. BrightSky , Roger W. Cheek , Ming-Hsiu Lee
发明人： Matthew J. BrightSky , Roger W. Cheek , Ming-Hsiu Lee
IPC分类号： G11C11/00 , H01L21/8239
CPC分类号： G11C13/0004 , G11C13/0033 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1641 , H01L45/1675
摘要： A memory chip and methods of fabricating a memory device with different programming performance and retention characteristics on a single wafer. One method includes depositing a first bounded area of phase change material on the wafer and depositing a second bounded area of phase change material on the wafer. The method includes modifying the chemical composition of a switching volume of the first bounded area of phase change material. The method includes forming a first memory cell in the first bounded area of phase change material with a modified switching volume of phase change material and a second memory cell in the second bounded area of phase change material with an unmodified switching volume of phase change material such that the first memory cell has a first retention property and the second memory cell has a second retention property. The first retention property is different from the second retention property.
摘要翻译：存储器芯片以及在单个晶片上制造具有不同编程性能和保持特性的存储器件的方法。一种方法包括在晶片上沉积相变材料的第一界限区域，并在晶片上沉积相变材料的第二有界区域。该方法包括改变相变材料的第一有界区域的开关体积的化学成分。该方法包括在相变材料的第一有界区域中形成具有相变材料的修改的开关体积的第一存储单元，以及相变材料的第二有界区域中的第二存储单元，具有未改变的相变材料的开关体积，例如第一存储单元具有第一保留特性，而第二存储单元具有第二保留特性。第一保留性与第二保留性不同。

92. 发明授权

US08374019B2 Phase change memory with fast write characteristics 有权
标题翻译：具有快速写入特性的相变存储器
公开(公告)号：US08374019B2
公开(公告)日：2013-02-12
申请号：US12985253
申请日：2011-01-05
申请人： Chao-I Wu , Yen-Hao Shih , Ming-Hsiu Lee
发明人： Chao-I Wu , Yen-Hao Shih , Ming-Hsiu Lee
IPC分类号： G11C11/00
CPC分类号： H01L45/06 , G11C11/005 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C14/00 , G11C2013/0083 , G11C2013/0092 , H01L27/2463 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1641
摘要： A memory device including programmable resistance memory cells, including electrically pre-stressed target memory cells. The pre-stressed target memory cells have one of a lower voltage transition threshold, a shorter duration set interval and a longer reset state retention characteristic. Biasing circuitry is included on the device configured to control the pre-stressing operations, and to apply read, set and reset operations that can be modified for the pre-stressed memory cells.
摘要翻译：一种包括可编程电阻存储单元的存储器件，包括电预应力目标存储单元。预应力目标存储单元具有较低电压转变阈值，较短持续时间设定间隔和较长复位状态保持特性之一。设备上包括偏置电路，用于控制预应力操作，以及应用对预应力存储单元进行修改的读取，置位和复位操作。

93. 发明授权

US08241928B2 Test structure and method for detecting charge effects during semiconductor processing 有权
标题翻译：用于在半导体处理期间检测电荷效应的测试结构和方法
公开(公告)号：US08241928B2
公开(公告)日：2012-08-14
申请号：US12777858
申请日：2010-05-11
申请人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L2224/73204 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.
摘要翻译：半导体工艺测试结构包括电极，电荷俘获层和扩散区域。测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。然后可以使用栅极漏极泄漏（GIDL）测量技术来表征测试结构的充电状态。

94. 发明申请

US20120187362A1 Phase Change Memory Cell Structure 有权
标题翻译：相变存储单元结构
公开(公告)号：US20120187362A1
公开(公告)日：2012-07-26
申请号：US13436203
申请日：2012-03-30
申请人： Ming-Hsiu Lee , Chieh-Fang Chen
发明人： Ming-Hsiu Lee , Chieh-Fang Chen
IPC分类号： H01L45/00
CPC分类号： H01L45/1273 , G11C13/0004 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/126 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/148
摘要： A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.
摘要翻译：本文所述的存储单元包括存储元件，其包括覆盖导电触点的可编程电阻存储器材料。绝缘体元件包括从导电触点延伸到存储元件中的管状部分，管形部分具有近端和远端以及限定内部的内表面，近端与导电触点相邻。底部电极接触导电接触并在内部从近端向远端向上延伸，底部电极具有在第一接触表面处与远端相邻的顶表面接触存储元件。顶部电极通过存储元件与管状部分的远端分离，并在第二接触表面处接触存储元件，第二接触表面的表面积大于第一接触表面的表面积。

95. 发明授权

US08198619B2 Phase change memory cell structure 有权
标题翻译：相变存储单元结构
公开(公告)号：US08198619B2
公开(公告)日：2012-06-12
申请号：US12534599
申请日：2009-08-03
申请人： Ming-Hsiu Lee , Chieh-Fang Chen
发明人： Ming-Hsiu Lee , Chieh-Fang Chen
IPC分类号： H01L47/00
CPC分类号： H01L45/1273 , G11C13/0004 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/126 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/148
摘要： A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.
摘要翻译：本文所述的存储单元包括存储元件，其包括覆盖导电触点的可编程电阻存储器材料。绝缘体元件包括从导电触点延伸到存储元件中的管状部分，管形部分具有近端和远端以及限定内部的内表面，近端与导电触点相邻。底部电极接触导电接触并在内部从近端向远端向上延伸，底部电极具有在第一接触表面处与远端相邻的顶表面接触存储元件。顶部电极通过存储元件与管状部分的远端分离，并在第二接触表面处接触存储元件，第二接触表面的表面积大于第一接触表面的表面积。

96. 发明授权

US08094488B2 Set algorithm for phase change memory cell 有权
标题翻译：相变存储单元的集合算法
公开(公告)号：US08094488B2
公开(公告)日：2012-01-10
申请号：US12965126
申请日：2010-12-10
申请人： Ming-Hsiu Lee
发明人： Ming-Hsiu Lee
IPC分类号： G11C11/00
CPC分类号： G11C13/0038 , G11C13/0004 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2013/0092 , G11C2213/79
摘要： Memory devices and methods for operating such devices are described herein. A method is described herein for operating a memory cell comprising phase change material and programmable to a plurality of resistance states including a high resistance state and a lower resistance state. The method comprises applying a first bias arrangement to the memory cell to establish the lower resistance state, the first bias arrangement comprising a first voltage pulse. The method further comprises determining whether the memory cell is in the lower resistance state, and if the memory cell is not in the lower resistance state then applying a second bias arrangement to the memory cell. The second bias arrangement comprises a second voltage pulse having a pulse height greater than that of the first voltage pulse.
摘要翻译：这里描述了用于操作这样的设备的存储器件和方法。本文描述了一种用于操作包括相变材料并且可编程为包括高电阻状态和较低电阻状态的多个电阻状态的存储单元的方法。该方法包括将第一偏置装置施加到存储器单元以建立较低电阻状态，第一偏置装置包括第一电压脉冲。该方法还包括确定存储器单元是处于较低电阻状态，以及如果存储单元不处于较低电阻状态，则向存储单元施加第二偏置布置。第二偏置装置包括具有大于第一电压脉冲的脉冲高度的第二电压脉冲。

97. 发明授权

US07911856B2 Three-dimensional memory devices and methods of manufacturing and operating the same 有权
标题翻译：三维存储器件及其制造和操作方法
公开(公告)号：US07911856B2
公开(公告)日：2011-03-22
申请号：US12471411
申请日：2009-05-25
申请人： Ming-Hsiu Lee , Yen-Hao Shih
发明人： Ming-Hsiu Lee , Yen-Hao Shih
IPC分类号： G11C7/00
CPC分类号： G11C13/0023 , G11C13/00 , G11C13/0004 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/1203 , H01L29/66833 , H01L29/792
摘要： A method of accessing memory cells is disclosed. A first signal is sent to at least one layer select transistor. The at least one layer select transistor is activated based on the first signal. Signals are communicated to or from one or more memory cells based on the activated at least layer select transistor.
摘要翻译：公开了访问存储器单元的方法。第一信号被发送到至少一个层选择晶体管。基于第一信号激活至少一个层选择晶体管。基于激活的至少层选择晶体管将信号传送到或来自一个或多个存储器单元。

98. 发明授权

US07777275B2 Silicon-on-insulator structures 有权
标题翻译：绝缘体上硅结构
公开(公告)号：US07777275B2
公开(公告)日：2010-08-17
申请号：US11383973
申请日：2006-05-18
申请人： Ming-Hsiu Lee
发明人： Ming-Hsiu Lee
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7851 , H01L29/7881 , H01L29/792
摘要： Methods which include providing a single crystal silicon substrate having a device pattern formed on a portion of the substrate where the device pattern has a protrusion, forming a protection layer on a portion of the protrusion, and forming an oxide insulation layer between the protrusion and the substrate using a thermal oxidation process; methods of forming a partial SOI structure which include providing a single crystal silicon substrate having a device pattern formed thereon where the device pattern comprises a non-SOI region and an SOI region having a protrusion, forming a protection layer on a portion of the protrusion, and forming an oxide insulation layer between the protrusion and the substrate using a thermal oxidation process; structures formed by such methods; and partial silicon-on-insulator structures comprising a single crystal silicon substrate having an device pattern disposed on a surface thereof where the device pattern includes a non-SOI region and an SOI region having a protrusion, and an oxide insulation layer disposed in the device pattern where a portion of the insulation layer is disposed under the protrusion such that the protrusion is isolated from the single crystal substrate, and where the non-SOI region is not isolated from the single crystal structure.
摘要翻译：包括提供具有形成在基板的一部分上的器件图案的单晶硅衬底的方法，其中器件图案具有突起，在突起的一部分上形成保护层，并且在突出部和突起之间形成氧化物绝缘层使用热氧化工艺的基板; 形成部分SOI结构的方法包括提供其上形成有器件图案的器件图案的单晶硅衬底，其中器件图案包括非SOI区域和具有突起的SOI区域，在突出部分的一部分上形成保护层，以及使用热氧化工艺在所述突起和所述基板之间形成氧化物绝缘层; 通过这种方法形成的结构; 以及部分绝缘体上硅结构，其包括单晶硅衬底，其具有设置在其表面上的器件图案，其中器件图案包括非SOI区域和具有突起的SOI区域，以及设置在器件中的氧化物绝缘层其中所述绝缘层的一部分设置在所述突起下方，使得所述突起与所述单晶基板隔离，并且其中所述非SOI区域不与所述单晶结构隔离。

99. 发明授权

US07773430B2 Method of identifying logical information in a programming and erasing cell by on-side reading scheme 有权
标题翻译：通过旁路读取方案识别编程和擦除单元中的逻辑信息的方法
公开(公告)号：US07773430B2
公开(公告)日：2010-08-10
申请号：US12314881
申请日：2008-12-18
申请人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
发明人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
IPC分类号： G11C11/34
CPC分类号： G11C16/0475
摘要： A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.
摘要翻译：公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。

100. 发明申请

US20100008153A1 METHOD FOR OPERATING NONVOLATITLE MEMORY ARRAY 有权
标题翻译：操作非易失性存储器阵列的方法
公开(公告)号：US20100008153A1
公开(公告)日：2010-01-14
申请号：US12561849
申请日：2009-09-17
申请人： Hao-Ming Lien , Ming-Hsiu Lee
发明人： Hao-Ming Lien , Ming-Hsiu Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A method for programming a mixed nonvolatile memory array having a plurality of mixed memory cells, wherein each mixed memory cell includes a depletion mode memory cell and an enhanced mode memory cell. The method comprises steps of programming the enhanced mode memory cell in a way of channel hot carrier and programming the depletion mode memory cell in a way of band-to-band tunneling hot carrier.
摘要翻译：一种用于编程具有多个混合存储器单元的混合非易失性存储器阵列的方法，其中每个混合存储单元包括耗尽型存储单元和增强型存储单元。该方法包括以通道热载波的方式对增强型存储器单元进行编程的步骤，并以带对带隧道热载波的方式对耗尽型存储单元进行编程。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式