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1. 发明申请

US20100221851A1 TEST STRUCTURE AND METHOD FOR DETECTING CHARGE EFFECTS DURING SEMICONDUCTOR PROCESSING 有权
标题翻译：用于检测半导体加工过程中充电效应的测试结构和方法
公开(公告)号：US20100221851A1
公开(公告)日：2010-09-02
申请号：US12777858
申请日：2010-05-11
申请人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L2224/73204 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.
摘要翻译：半导体工艺测试结构包括电极，电荷俘获层和扩散区域。测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。然后可以使用栅极漏极泄漏（GIDL）测量技术来表征测试结构的充电状态。

2. 发明授权

US07209385B1 Array structure for assisted-charge memory devices 有权
标题翻译：辅助电荷存储器件的阵列结构
公开(公告)号：US07209385B1
公开(公告)日：2007-04-24
申请号：US11327561
申请日：2006-01-06
申请人： Chao-I Wu , Ming Hsiu Lee , Ming-Chang Kuo
发明人： Chao-I Wu , Ming Hsiu Lee , Ming-Chang Kuo
IPC分类号： G11C16/04
CPC分类号： G11C16/0491 , G11C16/0466 , G11C16/14 , H01L21/28282 , H01L29/792
摘要： An Assisted Charge (AC) Memory cell comprises a transistor that includes, for example, a p-type substrate with an n+ source region and an n+ drain region implanted on the p-type substrate. A gate electrode can be formed over the substrate and portions of the source and drain regions. The gate electrode can comprise a trapping structure. The trapping structure can be treated as electrically split into two sides. One side can be referred to as the “AC-side” and can be fixed at a high voltage by trapping electrons within the structure. The electrons are referred to as assisted charges. The other side of can be used to store data and is referred to as the “data-side.” The abrupt electric field between AC-side and the data-side can enhance programming efficiency.
摘要翻译：辅助充电（AC）存储单元包括晶体管，其包括例如p型衬底，其具有n +源极区域和n +漏极区域注入在p型衬底上。栅电极可以形成在衬底上以及源区和漏区的部分之上。栅电极可以包括捕获结构。捕获结构可以被电分为两侧。一侧可以称为“AC侧”，并且可以通过在结构内捕获电子而将其固定在高电压。电子被称为辅助电荷。另一边可以用来存储数据，被称为“数据端”。 AC侧和数据侧之间的突发电场可以提高编程效率。

3. 发明授权

US08178407B2 Systems and methods for a high density, compact memory array 有权
标题翻译：用于高密度，紧凑型存储器阵列的系统和方法
公开(公告)号：US08178407B2
公开(公告)日：2012-05-15
申请号：US12561395
申请日：2009-09-17
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0475 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.
摘要翻译：包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。因此，可以实现非常紧凑，高密度的存储器阵列。存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。可以使用多电平充电技术来增加每个单元的位数，并实现对存储器阵列的进一步增加的密度。

4. 发明授权

US07817472B2 Operating method of memory device 有权
标题翻译：存储器件的操作方法
公开(公告)号：US07817472B2
公开(公告)日：2010-10-19
申请号：US12169155
申请日：2008-07-08
申请人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-I Wu
发明人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-I Wu
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/10 , G11C16/14
摘要： An operating method of a memory array is provided. The operating method includes performing a programming operation. The programming operation is performed by applying a first voltage to a bit line of the memory array and a second voltage to a plurality of word lines of the memory array to cause simultaneously programming a plurality of selected memory cells in the memory array.
摘要翻译：提供了一种存储器阵列的操作方法。操作方法包括执行编程操作。通过将第一电压施加到存储器阵列的位线并将第二电压施加到存储器阵列的多个字线来执行编程操作，以同时对存储器阵列中的多个选择的存储器单元进行编程。

5. 发明申请

US20090207658A1 OPERATING METHOD OF MEMORY DEVICE 有权
标题翻译：存储器件的操作方法
公开(公告)号：US20090207658A1
公开(公告)日：2009-08-20
申请号：US12169155
申请日：2008-07-08
申请人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-I Wu
发明人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-I Wu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0416 , G11C16/10 , G11C16/14
摘要： An operating method of a memory array is provided. The operating method includes performing a programming operation. The programming operation is performed by applying a first voltage to a bit line of the memory array and a second voltage to a plurality of word lines of the memory array to cause simultaneously programming a plurality of selected memory cells in the memory array
摘要翻译：提供了一种存储器阵列的操作方法。操作方法包括执行编程操作。通过将第一电压施加到存储器阵列的位线并将第二电压施加到存储器阵列的多个字线来执行编程操作，以同时编程存储器阵列中的多个选择的存储器单元

6. 发明申请

US20080023699A1 A TEST STRUCTURE AND METHOD FOR DETECTING CHARGE EFFECTS DURING SEMICONDUCTOR PROCESSING 审中-公开
标题翻译：用于检测半导体加工过程中的充电效应的测试结构和方法
公开(公告)号：US20080023699A1
公开(公告)日：2008-01-31
申请号：US11460209
申请日：2006-07-26
申请人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L23/58
CPC分类号： H01L22/34 , H01L2224/73204 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.
摘要翻译：半导体工艺测试结构包括电极，电荷俘获层和扩散区域。测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。然后可以使用栅极漏极泄漏（GIDL）测量技术来表征测试结构的充电状态。

7. 发明申请

US20070161193A1 Systems and methods for a high density, compact memory array 有权
标题翻译：用于高密度，紧凑型存储器阵列的系统和方法
公开(公告)号：US20070161193A1
公开(公告)日：2007-07-12
申请号：US11327792
申请日：2006-01-06
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0475 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.
摘要翻译：包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。因此，可以实现非常紧凑，高密度的存储器阵列。存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。可以使用多电平充电技术来增加每个单元的位数，并实现对存储器阵列的进一步增加的密度。

8. 发明授权

US07206227B1 Architecture for assisted-charge memory array 有权
标题翻译：辅助电荷存储器阵列的架构
公开(公告)号：US07206227B1
公开(公告)日：2007-04-17
申请号：US11326855
申请日：2006-01-06
申请人： Chao-I Wu , Ming Hsiu Lee , Ming-Chang Kuo
发明人： Chao-I Wu , Ming Hsiu Lee , Ming-Chang Kuo
IPC分类号： G11C11/34
CPC分类号： G11C16/0475 , G11C16/0466 , G11C16/0491
摘要： An Assisted Charge (AC) Memory cell includes a transistor that includes, for example, a p-type substrate with an n+ source region and an n+ drain region implanted on the p-type substrate. A gate electrode can be formed over the substrate and portions of the source and drain regions. The gate electrode can include a trapping layer. The trapping layer can be treated as electrically split into two sides. One side can be referred to as the “AC-side” and can be fixed at a high voltage by trapping electrons within the layer. The electrons are referred to as assisted charges. The other side of can be used to store data and is referred to as the “data-side.” The abrupt electric field between AC-side and the data-side can enhance programming efficiency.
摘要翻译：辅助充电（AC）存储单元包括晶体管，其包括例如p型衬底，其具有植入在p型衬底上的n +源极区和n +漏极区。栅电极可以形成在衬底上以及源区和漏区的部分之上。栅电极可以包括捕获层。捕获层可以被电分为两侧。一侧可以称为“AC侧”，并且可以通过在层内捕获电子而将其固定在高电压。电子被称为辅助电荷。另一边可以用来存储数据，被称为“数据端”。 AC侧和数据侧之间的突发电场可以提高编程效率。

9. 发明申请

US20100009504A1 SYSTEMS AND METHODS FOR A HIGH DENSITY, COMPACT MEMORY ARRAY 有权
标题翻译：高密度，紧密记忆阵列的系统和方法
公开(公告)号：US20100009504A1
公开(公告)日：2010-01-14
申请号：US12561395
申请日：2009-09-17
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0475 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.
摘要翻译：包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。因此，可以实现非常紧凑，高密度的存储器阵列。存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。可以使用多电平充电技术来增加每个单元的位数，并实现对存储器阵列的进一步增加的密度。

10. 发明授权

US07501837B2 Test structure and method for detecting charge effects during semiconductor processing using a delayed inversion point technique 有权
标题翻译：使用延迟反转点技术在半导体处理期间检测电荷效应的测试结构和方法
公开(公告)号：US07501837B2
公开(公告)日：2009-03-10
申请号：US11279224
申请日：2006-04-10
申请人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-I Wu
发明人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-I Wu
IPC分类号： G01R31/302
CPC分类号： H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor process test structure comprises a gate electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. A CV measurement can then be used to detect whether a Vfb shift has occurred. If the process step resulted in a charge effect, then the induced charge will not be uniform. If the charging of the test structure is not uniform, then there will not be a Vfb shift. A delayed inversion point technique can then be used to monitor the charging status.
摘要翻译：半导体工艺测试结构包括栅电极，电荷捕获层和扩散区。测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。然后可以使用CV测量来检测是否发生了Vfb偏移。如果处理步骤导致电荷效应，则感应电荷将不均匀。如果测试结构的充电不均匀，则不会有Vfb偏移。然后可以使用延迟反转点技术来监视充电状态。

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