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91. 发明授权

US07217623B2 Fin FET and method of fabricating same 有权
标题翻译：翅片FET及其制造方法
公开(公告)号：US07217623B2
公开(公告)日：2007-05-15
申请号：US11050915
申请日：2005-02-04
申请人： Keun-Nam Kim , Hung-Mo Yang , Choong-Ho Lee
发明人： Keun-Nam Kim , Hung-Mo Yang , Choong-Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7854 , H01L21/823412 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0653 , H01L29/0657 , H01L29/4236 , H01L29/66621 , H01L29/66795 , H01L29/7851 , H01L29/7856
摘要： A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.
摘要翻译：使用体硅衬底形成鳍状场效应晶体管（鳍FET），并通过在翅片有源区中形成具有预定深度的凹槽，然后通过在上部形成栅极来充分保证形成在栅极下方的顶部沟道长度部分休息。形成器件隔离膜以在衬底的预定区域中限定非有源区和鳍有源区。在器件隔离膜的一部分中，形成第一凹部，并且在翅片有源区域的一部分中形成有比第一凹部浅的深度的第二凹部。栅极绝缘层形成在第二凹部内，栅极形成在第二凹部的上部。源极/漏极区域形成在栅电极的两侧的鳍片有源区域中。

92. 发明申请

US20050260814A1 Nonvolatile memory cells having high control gate coupling ratios using grooved floating gates and methods of forming same 失效
标题翻译：具有使用沟槽浮动栅极的高控制栅极耦合比的非易失性存储单元及其形成方法
公开(公告)号：US20050260814A1
公开(公告)日：2005-11-24
申请号：US11121887
申请日：2005-05-04
申请人： Eun-Suk Cho , Choong-Ho Lee , Tae-Yong Kim
发明人： Eun-Suk Cho , Choong-Ho Lee , Tae-Yong Kim
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L29/423 , H01L29/786 , H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/28282 , H01L29/42324 , H01L29/66787 , H01L29/7851 , H01L29/7853 , H01L29/7881
摘要： A non-volatile memory cell includes a semiconductor substrate having a fin-shaped active region extending therefrom. A tunnel dielectric layer is provided, which extends on opposing sidewalls and an upper surface of the fin-shaped active region. A floating gate electrode is provided on the tunnel dielectric layer. This floating gate electrode has at least a partial groove therein. An inter-gate dielectric layer is also provided. This inter-gate dielectric layer extends on the floating gate electrode and into the at least a partial groove. A control gate electrode is provided, which extends on the inter-gate dielectric layer and into the at least a partial groove.
摘要翻译：非易失性存储单元包括具有从其延伸的鳍状有源区的半导体衬底。提供隧道电介质层，其在相对的侧壁上延伸并且在鳍状有源区域的上表面上延伸。在隧道电介质层上设置浮栅电极。该浮栅电极中至少有一部分凹槽。还提供了栅极间电介质层。该栅极间电介质层在浮栅电极上延伸并进入至少一部分槽。提供控制栅极电极，其在栅极间电介质层上延伸并且进入至少部分凹槽。

93. 发明申请

US20050186746A1 Method of manufacturing a fin field effect transistor 有权
标题翻译：制造鳍式场效应晶体管的方法
公开(公告)号：US20050186746A1
公开(公告)日：2005-08-25
申请号：US11066703
申请日：2005-02-23
申请人： Chul Lee , Jae-Man Yoon , Choong-Ho Lee
发明人： Chul Lee , Jae-Man Yoon , Choong-Ho Lee
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/786
CPC分类号： H01L29/7851 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66795
摘要： In an exemplary embodiment, a fin active region is protruded along one direction from a bulk silicon substrate on which a shallow trench insulator is entirely formed so as to cover the fin active region. The shallow trench insulator is removed to selectively expose an upper part and sidewall of the fin active region, along a line shape that at least one time crosses with the fin active region, thus forming a trench. The fin active region is exposed by the trench and thereon a gate insulation layer is formed. Thereby, productivity is increased and performance of the device is improved. A fin FET employs a bulk silicon substrate of which a manufacturing cost is lower than that of a conventional SOI type silicon substrate. Also, a floating body effect can be prevented, or is substantially reduced.
摘要翻译：在一个示例性实施例中，翅片有源区域沿着整体形成浅沟槽绝缘体的体硅基板沿着一个方向突出，以覆盖翅片有源区域。去除浅沟槽绝缘体，以沿着至少一次与翅片有源区交叉的线形状选择性地暴露翅片有源区的上部和侧壁，从而形成沟槽。翅片有源区域被沟槽暴露，并且形成有栅极绝缘层。从而，提高了生产效率并提高了设备的性能。翅片FET采用其制造成本低于常规SOI型硅衬底的制造成本的体硅衬底。此外，可以防止浮体效应或大大降低浮体效应。

94. 发明申请

US20050184348A1 Semiconductor device gate structure and method of forming the same 审中-公开
标题翻译：半导体器件栅极结构及其形成方法
公开(公告)号：US20050184348A1
公开(公告)日：2005-08-25
申请号：US11059145
申请日：2005-02-15
申请人： Jae-Man Youn , Dong-Gun Park , Choong-Ho Lee , Makoto Yoshida , Chul Lee
发明人： Jae-Man Youn , Dong-Gun Park , Choong-Ho Lee , Makoto Yoshida , Chul Lee
IPC分类号： H01L21/28 , H01L21/316 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66666 , H01L21/823487 , H01L29/42384 , H01L29/4908 , H01L29/66742 , H01L29/78618 , H01L29/78642
摘要： A MOS transistor includes a gate structure extending forrom a semiconductor substrate in a vertical direction is disclosed. The gate structure includes a gate electrode extending from the substrate in a vertical direction, and a gate insulation layer enclosing the gate electrode. A channel pattern encloses the gate insulation layer, and a first conductive pattern extends from a lower portion of the channel pattern in a first direction verticalperpendicular to the channel pattern and in parallel with the substrate. A second conductive pattern extends from an upper portion of the channel pattern in a second direction verticalperpendicular to the channel pattern and in parallel with the substrate. Accordingly, the channel length of the MOS transistor is determined by a distance between the first and second conductive patterns, and a channel width of the MOS transistor is determined by a diameter of the gate structure. Short channel and narrow width effects are sufficiently prevented in a MOS transistor.
摘要翻译：公开了一种MOS晶体管，其包括在垂直方向上延伸半导体衬底的栅极结构。栅极结构包括从垂直方向从衬底延伸的栅极电极和围绕栅电极的栅极绝缘层。沟道图案包围栅极绝缘层，并且第一导电图案沿着垂直于沟道图案的第一方向并且与衬底平行地从沟道图案的下部延伸。第二导电图案沿着垂直于沟道图案的第二方向并与衬底平行地从沟道图案的上部延伸。因此，MOS晶体管的沟道长度由第一和第二导电图案之间的距离决定，并且MOS晶体管的沟道宽度由栅极结构的直径决定。在MOS晶体管中充分防止了短沟道和窄宽度效应。

95. 发明申请

US20050176186A1 Field effect transistor and method for manufacturing the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20050176186A1
公开(公告)日：2005-08-11
申请号：US11048369
申请日：2005-01-31
申请人： Choong-Ho Lee , Jae-Man Yoon , Dong-Gun Park , Chul Lee
发明人： Choong-Ho Lee , Jae-Man Yoon , Dong-Gun Park , Chul Lee
IPC分类号： H01L21/28 , H01L21/00 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/76 , H01L29/78 , H01L29/786 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66772 , H01L29/42384 , H01L29/42392 , H01L29/785 , H01L29/7854 , H01L29/78603 , H01L29/78648
摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a lower layer and an upper layer overlying the lower layer. The upper layer is arranged and structured to form first and second active regions that are spaced apart from each other and protrude from an upper surface of the lower layer. A third active region of a bridge shape is distanced vertically from the upper surface of the lower layer and connects the first and second active regions. The device further includes a gate electrode, which is formed with a gate insulation layer surrounding the third active region, so that the third active region functions as a channel.
摘要翻译：在一个实施例中，半导体器件包括具有下层和覆盖在下层上的上层的半导体衬底。上层被布置和构造成形成彼此间隔开并从下层的上表面突出的第一和第二有源区。桥接形状的第三有源区域与下层的上表面垂直地间隔开并且连接第一和第二有源区域。该器件还包括栅电极，其形成有围绕第三有源区的栅绝缘层，使得第三有源区用作沟道。

96. 发明授权

US08916237B2 Thin film deposition apparatus and method of depositing thin film 有权
标题翻译：薄膜沉积装置和沉积薄膜的方法
公开(公告)号：US08916237B2
公开(公告)日：2014-12-23
申请号：US12784774
申请日：2010-05-21
申请人： Choong-Ho Lee , Jung-Min Lee
发明人： Choong-Ho Lee , Jung-Min Lee
IPC分类号： C23C16/00 , C23C16/52 , C23C14/24 , C23C16/04
CPC分类号： C23C14/24
摘要： A method of manufacturing a thin film on a substrate including: disposing the substrate to be separated from a thin film deposition apparatus by a preset distance; passing vaporized deposition material through first slits of a first nozzle, the first slits arranged in a first direction; passing the vaporized deposition material received from the first slits through second slits of a second nozzle of the thin film deposition apparatus; using an adjusting member including an actuator set to adjust an orientation of the second nozzle relative to a deposition target area on the substrate on which the deposition material from the second nozzle is to be deposited; and depositing the deposition material from the second nozzle onto the deposition target area while the thin film deposition apparatus or the substrate is moved relative to the other, the second nozzle defining a pattern of deposition material on the substrate, is disclosed.
摘要翻译：一种在基板上制造薄膜的方法，包括：将从薄膜沉积设备分离的基板设置预定距离; 使蒸发的沉积材料通过第一喷嘴的第一狭缝，所述第一狭缝沿第一方向布置; 使从第一狭缝接收的汽化沉积材料通过薄膜沉积设备的第二喷嘴的第二狭缝; 使用包括致动器组件的调节构件来调节所述第二喷嘴相对于将沉积来自所述第二喷嘴的所述沉积材料上的所述基板上的沉积目标区域的取向; 并且将沉积材料从第二喷嘴沉积到沉积靶区域上，同时薄膜沉积设备或衬底相对于另一个移动，第二喷嘴在衬底上限定沉积材料的图案。

97. 发明授权

US08882920B2 Thin film deposition apparatus 有权
标题翻译：薄膜沉积装置
公开(公告)号：US08882920B2
公开(公告)日：2014-11-11
申请号：US12794093
申请日：2010-06-04
申请人： Jung-Min Lee , Choong-Ho Lee
发明人： Jung-Min Lee , Choong-Ho Lee
IPC分类号： C23C16/00
CPC分类号： C23C14/042 , C23C14/12 , C23C14/243 , H01L51/0005
摘要： A thin film deposition apparatus to form a fine pattern on a large substrate. The thin film deposition apparatus includes a deposition source, a first nozzle that is disposed at a side of the deposition source and includes a plurality of first slits, a second nozzle that is disposed opposite to the deposition source and includes a plurality of second slits, and a second nozzle reinforcement unit that is disposed on the second nozzle and crosses the second nozzle.
摘要翻译：一种薄膜沉积设备，用于在大的衬底上形成精细图案。薄膜沉积设备包括沉积源，设置在沉积源侧并包括多个第一狭缝的第一喷嘴，与沉积源相对设置并包括多个第二狭缝的第二喷嘴，以及第二喷嘴加强单元，其设置在所述第二喷嘴上并且穿过所述第二喷嘴。

98. 发明授权

US08556671B2 Frit sealing system and method of manufacturing organic light-emitting display (OLED) apparatus using the same 有权
标题翻译：玻璃料密封系统和使用其的有机发光显示（OLED）装置的制造方法
公开(公告)号：US08556671B2
公开(公告)日：2013-10-15
申请号：US12964641
申请日：2010-12-09
申请人： Jung-Min Lee , Choong-Ho Lee
发明人： Jung-Min Lee , Choong-Ho Lee
IPC分类号： H01J9/50
CPC分类号： H01L51/56 , B23K1/0056 , H01L51/524 , H01L51/5246 , H01L2251/566
摘要： A frit sealing system and a method of manufacturing an organic light-emitting display (OLED) using the frit sealing system are disclosed. In one embodiment, the frit sealing system includes: a thermal expansion film formed on the second substrate to pressurize the second substrate when heat is applied to the frit and thermal expansion film, wherein the frit is interposed between the first and second substrates and a mask formed on the thermal expansion film.
摘要翻译：公开了玻璃料密封系统和使用玻璃料密封系统制造有机发光显示器（OLED）的方法。在一个实施例中，玻璃料密封系统包括：热量膨胀膜，其形成在第二基板上，以在对玻璃料和热膨胀膜施加热量时对第二基板加压，其中玻璃料置于第一和第二基板之间，形成在热膨胀膜上。

99. 发明授权

US08293604B2 Methods of manufacturing vertical channel semiconductor devices 有权
标题翻译：制造垂直沟道半导体器件的方法
公开(公告)号：US08293604B2
公开(公告)日：2012-10-23
申请号：US12838826
申请日：2010-07-19
申请人： Jae-man Yoon , Dong-gun Park , Choong-Ho Lee , Seong-Goo Kim , Won-sok Lee , Seung-bae Park
发明人： Jae-man Yoon , Dong-gun Park , Choong-Ho Lee , Seong-Goo Kim , Won-sok Lee , Seung-bae Park
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L27/10823 , H01L27/10876 , H01L27/115 , H01L27/11568 , H01L28/91 , H01L29/66833 , H01L29/7926
摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.
摘要翻译：垂直沟道半导体器件包括具有上表面的柱的半导体衬底。绝缘栅电极围绕柱的周边。绝缘栅电极具有比柱的上表面低的垂直级的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。第一源极/漏极区域在与衬底相邻的衬底中。第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

100. 发明申请

US20120146061A1 ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：有机发光二极管显示及其制造方法
公开(公告)号：US20120146061A1
公开(公告)日：2012-06-14
申请号：US13276218
申请日：2011-10-18
申请人： Kie Hyun Nam , Sang-Soo Kim , Choong-Ho Lee , Jung-Min Lee
发明人： Kie Hyun Nam , Sang-Soo Kim , Choong-Ho Lee , Jung-Min Lee
IPC分类号： H01L51/52 , H01L51/56
CPC分类号： H01L27/3276 , H01L51/524 , H01L51/5246 , H01L51/5259 , H01L2251/55 , H01L2251/558
摘要： A large size organic light emitting diode (OLED) display and manufacturing method thereof are disclosed. In one embodiment, the method includes i) forming a display unit including a plurality of pixels on a substrate, ii) forming a getter layer, a bonding layer and a conductive contact layer around the display unit and iii) manufacturing a sealing member including a flexible polymer film and a metal layer formed on at least one side of the polymer film. The method may further include laminating the sealing member on the substrate using a roll lamination process such that the metal layer contacts the conductive contact layer and curing the contact layer and the conductive contact layer.
摘要翻译：公开了一种大尺寸有机发光二极管（OLED）显示器及其制造方法。在一个实施例中，该方法包括：i）在衬底上形成包括多个像素的显示单元，ii）在显示单元周围形成吸气剂层，接合层和导电接触层，以及iii）制造密封构件，柔性聚合物膜和在聚合物膜的至少一侧上形成的金属层。该方法可以进一步包括使用卷层压工艺将密封构件层压在基板上，使得金属层接触导电接触层并固化接触层和导电接触层。

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