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91. 发明授权

US5926693A Two level transistor formation for optimum silicon utilization 失效
标题翻译：用于最佳硅利用的两级晶体管形成
公开(公告)号：US5926693A
公开(公告)日：1999-07-20
申请号：US788376
申请日：1997-01-27
申请人： Mark I. Gardner , Fred N. Hause , Jon D. Cheek
发明人： Mark I. Gardner , Fred N. Hause , Jon D. Cheek
IPC分类号： H01L27/07 , H01L27/088 , H01L21/00
CPC分类号： H01L27/0705 , H01L27/088
摘要： A semiconductor process in which a trench transistor is formed between a pair of planar transistors such that the source/drain regions of the trench transistor are shared with the source/drain regions of the planar transistors. A substrate is provided and first and second planar transistors are formed upon the upper surface of the substrate. The gate dielectric of the trench transistor is vertically displaced below the upper surface of the substrate. The trench transistor shares a first shared source/drain structure with the first planar transistor and a second shared source/drain structure with the second planar transistor. The formation of the trench transistor preferably includes the steps of etching a trench into the substrate, thermally oxidizing a floor of the trench to form a trench gate dielectric, and filling the trench with a conductive material to form a trench gate structure. The trench floor is vertically displaced below the upper surface of the substrate by a trench depth. The trench depth is preferably greater than a junction depth of the source/drain structures. In one embodiment, the formation of the trench transistor further includes, prior to the thermal oxidation of the trench floor, forming first and second ldd structures within the first and second trench ldd regions of the substrate. The first and second trench ldd structures provide conductive paths that extend from a trench channel region located beneath the trench floor to the first and the second shared source/drain structures respectively.
摘要翻译：一种半导体工艺，其中沟槽晶体管形成在一对平面晶体管之间，使得沟槽晶体管的源极/漏极区域与平面晶体管的源极/漏极区域共享。提供衬底，并且在衬底的上表面上形成第一和第二平面晶体管。沟槽晶体管的栅极电介质在衬底的上表面下方垂直位移。沟槽晶体管与第一平面晶体管共享第一共享源极/漏极结构，并且与第二平面晶体管共享第二共享源极/漏极结构。沟槽晶体管的形成优选地包括以下步骤：将沟槽蚀刻到衬底中，热氧化沟槽的底部以形成沟槽栅极电介质，并用导电材料填充沟槽以形成沟槽栅极结构。沟槽底部通过沟槽深度在衬底的上表面下方垂直移位。沟槽深度优选地大于源极/漏极结构的结深度。在一个实施例中，沟槽晶体管的形成还包括在沟槽底板的热氧化之前，在衬底的第一和第二沟槽区域内形成第一和第二层结构。第一和第二沟槽层结构提供从位于沟槽底部下方的沟槽沟道区域分别延伸到第一和第二共享源极/漏极结构的导电路径。

92. 发明授权

US5679585A Method for forming metal silicide on a semiconductor surface with minimal effect on pre-existing implants 失效
标题翻译：在半导体表面上形成金属硅化物的方法，对预先存在的植入物具有最小的影响
公开(公告)号：US5679585A
公开(公告)日：1997-10-21
申请号：US746774
申请日：1996-11-15
申请人： Mark I. Gardner , Fred N. Hause , Derick J. Wristers , Dim-Lee Kwong
发明人： Mark I. Gardner , Fred N. Hause , Derick J. Wristers , Dim-Lee Kwong
IPC分类号： H01L21/285 , H01L21/283
CPC分类号： H01L21/28518 , Y10S438/909
摘要： An method is provided for fabricating a metal silicide upon a semiconductor topography. The method advantageously performs the anneal cycles at a substantially lower temperature. By employing a high pressure anneal chamber, temperature equilibrium is achieved across the semiconductor topography and especially in small silicide formation areas. The higher pressure helps ensure thermal contact of heated, flowing gas across relatively small geometries in which silicide is to be formed. Substantial metal silicide formation can occur at the higher pressures even under relatively lower temperature conditions. The lower temperature process helps ensure that pre-existing implant regions remain at their initial position. The present metal silicide process and lower temperature anneal is therefore well suited to avoid impurity migration problems such as, for example, threshold skew, parasitic junction capacitance enhancement, and gate oxide degradation.
摘要翻译：提供了一种在半导体形貌上制造金属硅化物的方法。该方法有利地在基本上较低的温度下进行退火循环。通过采用高压退火室，在半导体形貌特别是在小的硅化物形成区域中实现了温度平衡。较高的压力有助于确保加热的流动气体在要形成硅化物的较小几何形状上的热接触。即使在相对较低的温度条件下，也可能在更高的压力下发生大量金属硅化物的形成。较低的温度过程有助于确保预先存在的植入区域保持在其初始位置。因此，目前的金属硅化物工艺和较低温度退火非常适合于避免杂质迁移问题，例如阈值偏移，寄生结电容增强和栅极氧化物降解。

93. 发明授权

US6137182A Method of reducing via and contact dimensions beyond photolithography equipment limits 有权
标题翻译：降低光刻设备限制以外的通孔和接触尺寸的方法
公开(公告)号：US6137182A
公开(公告)日：2000-10-24
申请号：US137471
申请日：1998-08-20
申请人： Fred N. Hause , Mark I. Gardner , Robert Dawson
发明人： Fred N. Hause , Mark I. Gardner , Robert Dawson
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76816
摘要： A semiconductor process for forming an interlevel contact. A semiconductor wafer is provided with a semiconductor substrate, a first conductive layer formed on the substrate, and a dielectric layer formed on the conductive layer. A border layer, preferably comprised of polysilicon or silicon nitride is formed on the dielectric layer. Portions of the border layer are then selectively removed to expose an upper surface of a spacer region of the dielectric layer, the selective removal of the border layer resulting in a border layer having an annular sidewall extending upward from the dielectric layer and encircling the spacer region. A spacer structure is then formed on the annular sidewall, preferably, the spacer structure is formed by chemically vapor depositing a spacer material and anisotropically etching the spacer material to just clear in the planar regions with minimum overetch. The spacer structure thereby covering peripheral portions of the spacer region such that an upper surface of a contact region remains exposed. Portions of the dielectric layer within the contact region are then removed to form a via extending from an upper surface of the spacer structure to an upper surface of the first conductive layer. Preferably, the lateral dimension of the spacer region is approximately equal to the minimum feature size of a photolithography exposure apparatus in the lateral dimension of the via at substantially less than the minimum feature size of the photolithography exposure apparatus.
摘要翻译：一种用于形成层间接触的半导体工艺。半导体晶片设置有半导体衬底，形成在衬底上的第一导电层和形成在导电层上的电介质层。在电介质层上形成优选由多晶硅或氮化硅构成的边界层。然后选择性地去除边界层的部分以暴露电介质层的间隔区域的上表面，选择性地去除边界层，导致边界层具有从电介质层向上延伸并环绕间隔区域的环形侧壁。然后在环形侧壁上形成间隔结构，优选地，间隔物结构通过化学气相沉积间隔物材料形成，并且各向异性地蚀刻间隔物材料，以便在具有最小过氧化物的平面区域中刚好清除。间隔结构由此覆盖间隔区域的周边部分，使得接触区域的上表面保持暴露。然后去除接触区域内的电介质层的部分以形成从间隔物结构的上表面延伸到第一导电层的上表面的通孔。优选地，间隔区域的横向尺寸基本上等于光刻曝光装置在通孔的横向尺寸中的最小特征尺寸，其基本上小于光刻曝光装置的最小特征尺寸。

94. 发明授权

US6051863A Transistor gate conductor having sidewall surfaces upon which a spacer having a profile that substantially prevents silicide bridging is formed 失效
标题翻译：具有侧壁表面的晶体管栅极导体形成具有基本上防止硅化物桥接的轮廓的间隔件
公开(公告)号：US6051863A
公开(公告)日：2000-04-18
申请号：US975582
申请日：1997-11-21
申请人： Fred N. Hause , Mark I. Gardner , Charles E. May
发明人： Fred N. Hause , Mark I. Gardner , Charles E. May
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/6659 , H01L29/665
摘要： A method is provided for fabricating a transistor gate conductor having opposed sidewall surfaces upon which dielectric spacers are formed such that the spacer profile substantially tapers toward the adjacent gate conductor sidewall surface as it approaches the base of the gate conductor. More particularly, formation of the sidewall spacers involves anisotropically etching a dielectric material deposited across a semiconductor topography in the presence of a passivant source to form a passivant upon portions of the dielectric material. The passivant primarily accumulates upon the upper portion of lateral surfaces of the dielectric material. An isotropic etch which occurs at the same rate in all directions is used to etch portions of the dielectric material not completely covered by the passivant. The resulting spacers have a varying thickness which decreases from top to bottom. Thus, when a silicide-forming metal is deposited, the metal accumulates at the peak of each spacer and is inhibited from being deposited upon the lower portions of the spacers, thereby preventing silicide bridging between the gate conductor and ensuing source/drain regions of the transistor.
摘要翻译：提供了一种用于制造具有相对侧壁表面的晶体管栅极导体的方法，在该侧壁表面上形成有电介质间隔物，使得当栅极导体侧壁表面接近栅极导体的基极时，间隔物轮廓基本上逐渐朝着相邻的栅极导体侧壁表面逐渐变细。更具体地说，侧壁间隔物的形成涉及各向异性蚀刻在钝化源的存在下横跨半导体形貌沉积的电介质材料，以在介电材料的一部分上形成钝化剂。钝化剂主要积聚在电介质材料的侧表面的上部。使用在所有方向上以相同速率发生的各向同性蚀刻来蚀刻未被钝化剂完全覆盖的介电材料的部分。所得的间隔物具有从顶部到底部减小的变化的厚度。因此，当沉积硅化物形成金属时，金属在每个间隔物的峰处积聚，并且被抑制沉积在间隔物的下部，从而防止栅极导体与随后的源极/漏极区之间的硅化物桥接晶体管。

95. 发明授权

US5905285A Ultra short trench transistors and process for making same 失效
标题翻译：超短沟槽晶体管及其制造方法
公开(公告)号：US5905285A
公开(公告)日：1999-05-18
申请号：US31570
申请日：1998-02-26
申请人： Mark I. Gardner , Fred N. Hause
发明人： Mark I. Gardner , Fred N. Hause
IPC分类号： H01L21/336 , H01L29/78 , H01L27/088
CPC分类号： H01L29/66621 , H01L29/7834 , Y10S257/90
摘要： A field effect transistor comprising a semiconductor substrate having a transistor trench extending downward from an upper surface of the semiconductor substrate. The trench extends to a trench depth below an upper surface of the semiconductor substrate. The transistor further includes a gate dielectric layer that is formed on a floor of the transistor trench over a channel region of the semiconductor substrate. A conductive gate structure is formed above and in contact with the gate dielectric layer. A source/drain impurity distribution is formed within a source/drain region of the semiconductor substrate. The source/drain region is laterally disposed on either side of the channel region of the semiconductor substrate. In a preferred embodiment, the trench depth is between 1,000-5,000 angstroms and a thickness of the conductive gate structure is less than 5,000 angstroms such that an upper surface of the conductive gate structure is level with or below an upper surface of the semiconductor substrate. The gate dielectric layer suitably comprises a thermal oxide having a thickness of approximately 20-200 angstroms. In a lightly doped drain (LDD) embodiment, the source/drain impurity distribution includes a lightly doped region and a heavily doped region. The lightly doped region extends laterally from the channel region of the transistor to the heavily doped region. In the preferred embodiment, a lateral dimension of the channel region of the transistor is approximately 100-300 nm.
摘要翻译：一种场效应晶体管，包括具有从半导体衬底的上表面向下延伸的晶体管沟槽的半导体衬底。沟槽延伸到半导体衬底的上表面下方的沟槽深度。晶体管还包括形成在半导体衬底的沟道区上的晶体管沟槽的底板上的栅介质层。导电栅极结构形成在栅介电层的上方并与其接触。源极/漏极杂质分布形成在半导体衬底的源极/漏极区域内。源极/漏极区域横向地设置在半导体衬底的沟道区域的任一侧上。在优选实施例中，沟槽深度在1,000-5,000埃之间，并且导电栅极结构的厚度小于5000埃，使得导电栅极结构的上表面与半导体衬底的上表面平行或低于半导体衬底的上表面。栅介质层适当地包括厚度约为20-200埃的热氧化物。在轻掺杂漏极（LDD）实施例中，源极/漏极杂质分布包括轻掺杂区域和重掺杂区域。轻掺杂区域从晶体管的沟道区域横向延伸到重掺杂区域。在优选实施例中，晶体管的沟道区的横向尺寸约为100-300nm。

96. 发明授权

US5851921A Semiconductor device and method for forming the device using a dual layer, self-aligned silicide to enhance contact performance 失效
标题翻译：用于使用双层自对准硅化物形成器件以提高接触性能的半导体器件和方法
公开(公告)号：US5851921A
公开(公告)日：1998-12-22
申请号：US832747
申请日：1997-04-04
申请人： Mark I. Gardner , Fred N. Hause
发明人： Mark I. Gardner , Fred N. Hause
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L29/665
摘要： An integrated circuit is formed by a process which can produce highly conductive contact structures. The contact structures result from a dual layer of titanium and cobalt reacted upon silicon-rich source/drain junctions and gate conductor upper surfaces. Reaction on the silicon-rich regions occur concurrent with one another using a self-aligned salicidation process, whereby the titanium layer can consume relatively large amounts of native oxide formed on the silicon-rich regions. In addition to interdiffusion of titanium, cobalt placed upon the titanium enhances the overall conductivity of the contact while providing some barrier properties against undue, additional interdiffusion of titanium and underlying silicon.
摘要翻译：通过可产生高导电性接触结构的工艺形成集成电路。接触结构是由在富含硅的源极/漏极结和栅极导体上表面上反应的钛和钴的双层产生的。在富含硅的区域上的反应使用自对准的盐析过程彼此并发，由此钛层可以消耗相对大量在富硅区域上形成的天然氧化物。除了钛的相互扩散之外，放置在钛上的钴增强了触点的整体电导率，同时提供了一些屏障性能，防止钛和下面的硅的不适当的额外相互扩散。

97. 发明授权

US5851883A High density integrated circuit process 失效
标题翻译：高密度集成电路工艺
公开(公告)号：US5851883A
公开(公告)日：1998-12-22
申请号：US844975
申请日：1997-04-23
申请人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
发明人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
IPC分类号： H01L21/8234
CPC分类号： H01L21/823437 , Y10S438/947
摘要： A semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region. Thereafter, proximal and distal spacer structures are formed on the proximal and distal sidewalls respectively of the first and second silicon-dielectric stacks. A gate dielectric layer is then formed on exposed portions of the silicon base layer over a channel region of the base silicon layer. Portions of the first and second silicon-dielectric stacks located over respective source/drain regions of the base silicon layer are then selectively removed. Silicon is then deposited to fill first and second voids created by the selected removal of the stacks. The silicon deposition also fills a silicon gate region above the gate dielectric over the channel region. Thereafter, an impurity distribution is introduced into the deposited silicon. The deposited silicon is then planarized to physically isolate the silicon within the gate region from the silicon within the first and second voids resulting in the formation of a transistor including a silicon gate structure and first and second source/drain structures.
摘要翻译：在包括硅基层的半导体衬底的上表面上形成介电层的半导体工艺。此后，在电介质层的上表面上形成上硅层。然后对电介质层和上硅层进行构图以在基底硅层的上表面上形成第一和第二硅 - 电介质叠层。第一和第二硅 - 电介质堆叠在硅衬底的沟道区域的任一侧上横向移位，并且每个包括近侧壁和远侧壁。近侧侧壁与通道区域的各个边界大致重合。此后，分别在第一和第二硅 - 电介质堆叠的近侧和远侧壁上形成近端和远端间隔结构。然后在硅基层的暴露部分上在基底硅层的沟道区上形成栅极电介质层。然后选择性地去除位于基底硅层的相应源极/漏极区域之上的第一和第二硅 - 电介质叠层的部分。然后沉积硅以填充由所选择的堆叠移除产生的第一和第二空隙。硅沉积还在沟道区域上填充栅极电介质上方的硅栅极区域。此后，将杂质分布引入沉积的硅中。沉积的硅然后被平坦化以物理地隔离第一和第二空隙内的栅极区域内的硅，从而形成包括硅栅极结构和第一和第二源极/漏极结构的晶体管。

98. 发明授权

US5843625A Method of reducing via and contact dimensions beyond photolithography equipment limits 失效
标题翻译：降低光刻设备限制以外的通孔和接触尺寸的方法
公开(公告)号：US5843625A
公开(公告)日：1998-12-01
申请号：US685144
申请日：1996-07-23
申请人： Fred N. Hause , Mark I. Gardner , Robert Dawson
发明人： Fred N. Hause , Mark I. Gardner , Robert Dawson
IPC分类号： H01L21/768 , G03F7/00
CPC分类号： H01L21/76816
摘要： A semiconductor process for forming an interlevel contact. A semiconductor wafer is provided with a semiconductor substrate, a first conductive layer formed on the substrate, and a dielectric layer formed on the conductive layer. A border layer, preferably comprising polysilicon or silicon nitride is formed on the dielectric layer. Portions of the border layer are then selectively removed to expose an upper surface of a spacer region of the dielectric layer, the selective removal of the border layer resulting in a border layer having an annular sidewall extending upward from the dielectric layer and encircling the spacer region. A spacer structure is then formed on the annular sidewall. Preferably, the spacer structure is formed by chemically vapor depositing a spacer material and anisotropically etching the spacer material to just clear in the planar regions with minimum overetch. The spacer structure thereby covers peripheral portions of the spacer region such that an upper surface of a contact region remains exposed. Portions of the dielectric layer within the contact region are then removed to form a via extending from an upper surface of the spacer structure to an upper surface of the first conductive layer. Preferably, the lateral dimension of the spacer region is approximately equal to the minimum feature size of a photolithography exposure apparatus in the lateral dimension of the via at substantially less than the minimum feature size of the photolithography exposure apparatus.
摘要翻译：一种用于形成层间接触的半导体工艺。半导体晶片设置有半导体衬底，形成在衬底上的第一导电层和形成在导电层上的电介质层。优选地包括多晶硅或氮化硅的边界层形成在电介质层上。然后选择性地去除边界层的部分以暴露电介质层的间隔区域的上表面，选择性地去除边界层，导致边界层具有从电介质层向上延伸并环绕间隔区域的环形侧壁。然后在环形侧壁上形成间隔结构。优选地，通过化学气相沉积间隔物材料并且各向异性地蚀刻间隔物材料来形成间隔结构，以便在具有最小过蚀刻的平面区域中刚好清除。间隔结构由此覆盖间隔区域的周边部分，使得接触区域的上表面保持暴露。然后去除接触区域内的电介质层的部分以形成从间隔物结构的上表面延伸到第一导电层的上表面的通孔。优选地，间隔区域的横向尺寸基本上等于光刻曝光装置在通孔的横向尺寸中的最小特征尺寸，其基本上小于光刻曝光装置的最小特征尺寸。

99. 发明授权

US5770517A Semiconductor fabrication employing copper plug formation within a contact area 失效
标题翻译：在接触区域内使用铜插塞形成的半导体制造
公开(公告)号：US5770517A
公开(公告)日：1998-06-23
申请号：US823046
申请日：1997-03-21
申请人： Mark I. Gardner , Fred N. Hause
发明人： Mark I. Gardner , Fred N. Hause
IPC分类号： H01L21/768 , H01L23/485 , H01L23/532 , H01L21/265 , H01L21/283
CPC分类号： H01L23/485 , H01L21/76838 , H01L23/53238 , H01L2924/0002 , Y10S257/915
摘要： An integrated circuit fabrication process is provided in which copper is used as the contact plug material for a via. The via is a hole etched through an interlevel dielectric which is disposed upon a semiconductor topography, e.g., a silicon-based substrate having junctions therein. An inert implant may form an implant region within the semiconductor topography lying underneath the via. The process for forming the copper plug involves depositing a diffusion barrier upon the interlevel dielectric and within the via. Copper is then deposited via chemical vapor deposition upon the diffusion barrier such that the copper fills the entire via and forms a layer above the via. The copper is etched from all areas except from within the via, thereby forming a copper plug in the via. The resulting surface is then subjected to chemical-mechanical polishing before the diffusion barrier is removed from areas exclusive of the via. A conductive layer can be placed upon the interlevel dielectric and the copper plug to form a contact between the conductive layer and the semiconductor topography.
摘要翻译：提供了一种集成电路制造工艺，其中使用铜作为通孔的接触插塞材料。通孔是通过层间电介质蚀刻的孔，其布置在半导体形貌上，例如其中具有结的硅基衬底。惰性植入物可以在位于通孔下方的半导体形貌内形成植入区域。形成铜插塞的过程包括在层间电介质和通孔内沉积扩散阻挡层。然后通过化学气相沉积将铜沉积在扩散阻挡层上，使得铜填充整个通孔并形成通孔上方的层。从除了通孔内的所有区域蚀刻铜，从而在通孔中形成铜塞。然后将所得表面进行化学机械抛光，然后从不包括通孔的区域除去扩散阻挡层。可以将导电层放置在层间电介质和铜插塞上以形成导电层和半导体形貌之间的接触。

100. 发明授权

US5719067A Trench transistor and method for making same 失效
标题翻译：沟槽晶体管及其制作方法
公开(公告)号：US5719067A
公开(公告)日：1998-02-17
申请号：US709378
申请日：1996-09-06
申请人： Mark I. Gardner , Fred N. Hause
发明人： Mark I. Gardner , Fred N. Hause
IPC分类号： H01L21/265 , H01L29/423 , H01L21/266
CPC分类号： H01L21/26506 , H01L29/4236
摘要： A field effect transistor and method for making same in which a first source/drain impurity distribution is located at a first depth below an upper surface of the semiconductor substrate and a second source/drain impurity distribution is located at a second depth below the upper surface. In a presently preferred embodiment, the first depth is greater than the second depth such that the transistor includes a channel region having a vertical component. The channel region extends from the first source/drain impurity distribution to the second source/drain impurity distribution. The field effect transistor further includes a gate dielectric which is in contact with the channel region and a conductive gate structure in contact with the gate dielectric layer. The vertical component of the transistor channel length can be accurately controlled with plasma etch techniques. In this manner, the transistor channel length is not defined by a photolithography process and, therefore, dimensions smaller than the minimum feature size resolvable by a photolithography aligner can be achieved.
摘要翻译：一种场效应晶体管及其制造方法，其中第一源极/漏极杂质分布位于半导体衬底的上表面下方的第一深度处，并且第二源极/漏极杂质分布位于上表面下方的第二深度。在当前优选的实施例中，第一深度大于第二深度，使得晶体管包括具有垂直分量的沟道区。沟道区域从第一源极/漏极杂质分布延伸到第二源极/漏极杂质分布。场效应晶体管还包括与沟道区域接触的栅极电介质和与栅极介电层接触的导电栅极结构。晶体管沟道长度的垂直分量可以用等离子蚀刻技术精确控制。以这种方式，晶体管沟道长度不由光刻工艺限定，因此可以实现小于由光刻对准器可分辨的最小特征尺寸的尺寸。

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