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91. 发明申请

US20120070973A1 Methods of Forming Diodes 有权
标题翻译：形成二极管的方法
公开(公告)号：US20120070973A1
公开(公告)日：2012-03-22
申请号：US13305072
申请日：2011-11-28
申请人： Gurtej S. Sandhu , Bhaskar Srinivasan
发明人： Gurtej S. Sandhu , Bhaskar Srinivasan
IPC分类号： H01L21/04
CPC分类号： H01L21/04 , H01L27/1021 , H01L27/2418 , H01L29/1606 , H01L45/00
摘要： Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed.
摘要翻译：一些实施例包括形成二极管的方法。可以在第一导电材料上形成堆叠。堆叠可以按升序包括牺牲材料，至少一种电介质材料和第二导电材料。间隔物可以沿着堆叠的相对侧壁形成，然后可以去除整个牺牲材料以在第一导电材料和至少一种电介质材料之间留下间隙。在形成二极管的一些实施例中，可以在第一导电材料上形成层，其中包含支撑体的层散布在牺牲材料中。可以在该层上形成至少一种介电材料，并且可以在该至少一种电介质材料的上方形成第二导电材料。然后可以去除整个牺牲材料。

92. 发明申请

US20120068143A1 Memory Arrays And Methods Of Forming Memory Cells 有权
标题翻译：内存阵列和形成记忆体的方法
公开(公告)号：US20120068143A1
公开(公告)日：2012-03-22
申请号：US12886283
申请日：2010-09-20
申请人： John Smythe , Gurtej S. Sandhu
发明人： John Smythe , Gurtej S. Sandhu
IPC分类号： H01L45/00 , H01L21/16
CPC分类号： H01L45/145 , H01L27/2409 , H01L27/2472 , H01L27/2481
摘要： Some embodiments include methods of forming memory cells utilizing various arrangements of conductive lines, electrodes and programmable material; with the programmable material containing high k dielectric material directly against multivalent metal oxide. Some embodiments include arrays of memory cells, with the memory cells including programmable material containing high k dielectric material directly against multivalent metal oxide.
摘要翻译：一些实施例包括利用导电线，电极和可编程材料的各种布置形成存储单元的方法; 其中可编程材料含有高k电介质材料直接抵抗多价金属氧化物。一些实施例包括存储器单元的阵列，其中存储单元包括直接对抗多价金属氧化物的包含高k电介质材料的可编程材料。

93. 发明授权

US08133664B2 Methods of forming patterns 有权
标题翻译：形成图案的方法
公开(公告)号：US08133664B2
公开(公告)日：2012-03-13
申请号：US12397083
申请日：2009-03-03
申请人： Scott Sills , Gurtej S. Sandhu , John Smythe , Ming Zhang
发明人： Scott Sills , Gurtej S. Sandhu , John Smythe , Ming Zhang
IPC分类号： G03F7/26
CPC分类号： H01L21/0274 , G03F7/20 , G03F7/40 , H01L21/0337 , H01L21/0338
摘要： Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops and may have sidewalls extending downwardly from the tops. A first material may be formed along the tops and sidewalls of the features. The first material may be formed by spin-casting a conformal layer of the first material across the features, or by selective deposition along the features relative to the substrate. After the first material is formed, fill material may be provided between the features while leaving regions of the first material exposed. The exposed regions of the first material may then be selectively removed relative to both the fill material and the features to create the pattern of openings.
摘要翻译：一些实施例包括形成开口图案的方法。所述方法可以包括在衬底上形成间隔的特征。特征可以具有顶部并且可以具有从顶部向下延伸的侧壁。第一材料可以沿着特征的顶部和侧壁形成。第一材料可以通过将特征上的第一材料的共形层旋转浇铸而形成，或通过相对于基底的特征的选择性沉积来形成。在形成第一材料之后，可以在特征之间提供填充材料，同时使第一材料的区域暴露。然后可以相对于填充材料和特征来选择性地去除第一材料的暴露区域以产生开口图案。

94. 发明授权

US08129289B2 Method to deposit conformal low temperature SiO2 有权
标题翻译：沉积保温低温SiO2的方法
公开(公告)号：US08129289B2
公开(公告)日：2012-03-06
申请号：US11543515
申请日：2006-10-05
申请人： John A. Smythe , Gurtej S. Sandhu , Brian J. Coppa , Shyam Surthi , Shuang Meng
发明人： John A. Smythe , Gurtej S. Sandhu , Brian J. Coppa , Shyam Surthi , Shuang Meng
IPC分类号： H01L21/00
CPC分类号： H01L21/3088 , H01L21/02164 , H01L21/02211 , H01L21/0228 , H01L21/3086 , H01L21/3141 , H01L21/31612
摘要： Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.
摘要翻译：公开了通过间距倍增来控制半导体制造期间尺寸减小的特征的关键尺寸的方法。间距倍增通过通过常规光致抗蚀剂技术图案化掩模结构并随后将图案转移到牺牲材料来实现。然后通过原子层沉积沉积保形材料之后，在转印图案的垂直表面上形成间隔区。然后将间隔区域以及因此减小的特征转移到半导体衬底。

95. 发明申请

US20120052662A1 METHOD FOR PURIFICATION OF SEMICONDUCTING SINGLE WALL NANOTUBES 有权
标题翻译：半导体单壁纳米管的纯化方法
公开(公告)号：US20120052662A1
公开(公告)日：2012-03-01
申请号：US13290648
申请日：2011-11-07
申请人： Eugene P. Marsh , Gurtej S. Sandhu
发明人： Eugene P. Marsh , Gurtej S. Sandhu
IPC分类号： H01L21/04 , H01B1/04 , B82B3/00 , B82Y40/00
CPC分类号： B82Y30/00 , B82Y40/00 , C01B32/17 , C01B2202/02 , C01B2202/06 , C01B2202/22 , C01B2202/34 , Y10T428/249924 , Y10T428/249953 , Y10T428/2918
摘要： A process of forming a semiconductive carbon nanotube structure includes imposing energy on a mixture that contains metallic carbon nanotubes and semiconductive carbon nanotubes under conditions to cause the metallic carbon nanotubes to be digested or to decompose so that they may be separated away from the semiconductive carbon nanotubes.
摘要翻译：形成半导体碳纳米管结构的方法包括在使金属碳纳米管被消化或分解的条件下在包含金属碳纳米管和半导体碳纳米管的混合物上施加能量，使得它们可以与半导体碳纳米管分离。

96. 发明申请

US20120051132A1 MEMORY CELL STRUCTURES AND METHODS 有权
公开(公告)号：US20120051132A1
公开(公告)日：2012-03-01
申请号：US12872368
申请日：2010-08-31
申请人： Gurtej S. Sandhu , Bhaskar Srinivasan
发明人： Gurtej S. Sandhu , Bhaskar Srinivasan
IPC分类号： G11C11/36 , G11C11/34
CPC分类号： G11C16/0416 , G11C16/0483
摘要： Memory cell structures and methods are described herein. One or more memory cells include a transistor having a charge storage node, a dielectric material positioned between the charge storage node and a channel region of the transistor, the channel region positioned between a source region and a drain region, and a first electrode of a diode coupled to the charge storage node.

97. 发明申请

US20120039790A1 Nanotube Separation Methods 有权
标题翻译：纳米管分离方法
公开(公告)号：US20120039790A1
公开(公告)日：2012-02-16
申请号：US13276150
申请日：2011-10-18
申请人： Gurtej S. Sandhu
发明人： Gurtej S. Sandhu
IPC分类号： D01F9/12 , B82Y40/00
CPC分类号： B01D21/262 , B01D43/00 , B82Y30/00 , B82Y40/00 , C01B32/172 , Y10S977/745 , Y10S977/746 , Y10S977/845 , Y10S977/847
摘要： A nanotube separation method includes depositing a tag on a nanotube in a nanotube mixture. The nanotube has a defect and the tag deposits at the defect where a deposition rate is greater than on another nanotube in the mixture lacking the defect. The method includes removing the tagged nanotube from the mixture by using the tag. As one option, the tag may contain a ferromagnetic material and the removing may include applying a magnetic field. As another option, the tag may contain an ionic material and the removing may include applying an electric field. As a further option, the tag may contain an atom having an atomic mass greater than the atomic mass of carbon and the removing may include applying a centrifugal force to the nanotube mixture. Any two or more of the indicated removal techniques may be combined.
摘要翻译：纳米管分离方法包括在纳米管混合物中的纳米管上沉积标签。纳米管具有缺陷，并且标记沉积在缺陷处，其中沉积速率大于缺少缺陷的混合物中的另一纳米管上的沉积速率。该方法包括通过使用标签从混合物中去除标记的纳米管。作为一种选择，标签可以包含铁磁材料，并且去除可以包括施加磁场。作为另一选择，标签可以包含离子材料，并且去除可以包括施加电场。作为另一选择，标签可以包含原子质量大于碳原子质量的原子，并且除去可包括向纳米管混合物施加离心力。可以组合指示的去除技术中的任何两种或更多种。

98. 发明申请

US20120006580A1 Electrically Conductive Laminate Structures, Electrical Interconnects, And Methods Of Forming Electrical Interconnects 有权
标题翻译：导电层压结构，电气互连和形成电气互连的方法
公开(公告)号：US20120006580A1
公开(公告)日：2012-01-12
申请号：US12833074
申请日：2010-07-09
申请人： Gurtej S. Sandhu
发明人： Gurtej S. Sandhu
IPC分类号： H01B5/00 , H05K13/00 , B05D5/12
CPC分类号： H01L23/53276 , H01L21/76805 , H01L21/76843 , H01L21/76847 , H01L21/76865 , H01L21/76877 , H01L23/53209 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene regions. In some embodiments the graphene and non-graphene regions may be nested within one another. In some embodiments an electrically insulative material may be over an upper surface of the laminate structure, and an opening may extend through the insulative material to a portion of the laminate structure. Electrically conductive material may be within the opening and in electrical contact with at least one of the non-graphene regions of the laminate structure. Some embodiments include methods of forming electrical interconnects in which non-graphene material and graphene are alternately formed within a trench to form nested non-graphene and graphene regions.
摘要翻译：一些实施例包括电互连。互连可以包含层压结构，其具有夹在非石墨烯区域之间的石墨烯区域。在一些实施例中，石墨烯和非石墨烯区域可以彼此嵌套。在一些实施例中，电绝缘材料可以在层压结构的上表面之上，并且开口可以延伸穿过绝缘材料到层压结构的一部分。导电材料可以在开口内并且与层压结构的非石墨烯区域中的至少一个电接触。一些实施例包括形成电互连的方法，其中在沟槽内交替形成非石墨烯材料和石墨烯以形成嵌套的非石墨烯和石墨烯区域。

99. 发明授权

US08093658B2 Electronic device with asymmetric gate strain 有权
标题翻译：具有不对称栅极应变的电子器件
公开(公告)号：US08093658B2
公开(公告)日：2012-01-10
申请号：US12697991
申请日：2010-02-01
申请人： Gurtej S. Sandhu , Kunal R. Parekh
发明人： Gurtej S. Sandhu , Kunal R. Parekh
IPC分类号： H01L29/76
CPC分类号： H01L29/4983 , H01L21/28114 , H01L21/823437 , H01L21/823456 , H01L21/823468 , H01L21/823807 , H01L21/823828 , H01L29/1033 , H01L29/1054 , H01L29/401 , H01L29/42376 , H01L29/6656 , H01L29/66659 , H01L29/7843 , H01L29/7845 , Y10S257/90
摘要： The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing structures as part of the gate electrode.
摘要翻译：在集成电路中使用应变栅电极导致晶体管具有改善的载流子迁移率，改进的驱动特性和减少的源极漏极结泄漏。栅电极应变可以通过不对称放置应力诱导结构作为栅电极的一部分获得。

100. 发明授权

US08084142B2 Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects 有权
标题翻译：向源极/漏极区形成导电接触的方法以及形成局部互连的方法
公开(公告)号：US08084142B2
公开(公告)日：2011-12-27
申请号：US11525762
申请日：2006-09-21
申请人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
发明人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
IPC分类号： H01L21/44 , H01L21/4763 , H01L29/40
CPC分类号： H01L21/76823 , H01L21/28512 , H01L21/76895 , Y10T428/12542
摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成对场效应晶体管的源极/漏极区的导电接触的方法，以及形成局部互连的方法。在一个实施方案中，形成到场效应晶体管的源/漏区的导电接触的方法包括在晶体管栅极和场效应晶体管的沟道区之间提供栅介质材料。至少一些栅极电介质材料延伸以在场效应晶体管的至少一个源极/漏极区域上接收。接收在一个源极/漏极区域上的栅极电介质材料暴露于有效地将其从电绝缘转变为导电并与一个源极/漏极区域导电接触的条件。考虑了其他方面和实现。

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