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91. 发明申请

US20100040114A1 INTRA-BODY COMMUNICATION SYSTEM FOR HIGH-SPEED DATA TRANSMISSION 审中-公开
标题翻译：用于高速数据传输的内部通信系统
公开(公告)号：US20100040114A1
公开(公告)日：2010-02-18
申请号：US12442971
申请日：2007-09-28
申请人： Tae-Joon Kim , Sung-Weon Kang , Kyung-Soo Kim , Jung-Bum Kim , In-Gi Lim , Chang-Hee Hyoung , Hyung-II Park , Duck-Gun Park , Sung-Eun Kim , Jin-Kyung Kim , Jung-Hwan Hwang , Jin-Bong Sung , Hyuk Kim , Ki-Hyuk Park
发明人： Tae-Joon Kim , Sung-Weon Kang , Kyung-Soo Kim , Jung-Bum Kim , In-Gi Lim , Chang-Hee Hyoung , Hyung-II Park , Duck-Gun Park , Sung-Eun Kim , Jin-Kyung Kim , Jung-Hwan Hwang , Jin-Bong Sung , Hyuk Kim , Ki-Hyuk Park
IPC分类号： H04B1/69 , H04L27/22
CPC分类号： H04B13/005
摘要： Provided is an intra-body communication system which enables high-speed data transmission while limiting the frequency band of a signal being transmitted through a human body to a frequency range (e.g., 30-40 MHz) where the human body can maintain waveguide properties and enables stable intra-body communication by minimizing interference by other users or other electronic devices. A transceiver of the intra-body communication system for high-speed data transmission includes: a source encoder for encoding source information to digital transmission data; a channel error prevention unit for inserting a redundant bit to the encoded transmission data; a mapper for symbolizing the transmission data outputted from the channel error prevention unit; a spreader for performing spread spectrum on the symbolized transmission data in a frequency domain; and a pulse shaping and modulator for generating a baseband signal with a band range limited to a frequency range where the human body retains waveguide properties.
摘要翻译：提供一种体内通信系统，其能够将通过人体传播的信号的频带限制在人体可以保持波导特性的频率范围（例如，30-40MHz）的同时进行高速数据传输，并且通过最小化其他用户或其他电子设备的干扰来实现稳定的体内通信。用于高速数据传输的身体内通信系统的收发机包括：源编码器，用于将源信息编码为数字传输数据; 通道错误防止单元，用于将冗余位插入到编码的发送数据中; 映射器，用于对从信道错误防止单元输出的发送数据进行符号化; 用于对频域中的符号化传输数据进行扩展频谱的扩展器; 以及用于产生频带范围限于人体保持波导特性的频率范围的基带信号的脉冲整形和调制器。

92. 发明授权

US07571203B2 Processing device for a pseudo inverse matrix and V-BLAST system 失效
标题翻译：用于伪逆矩阵和V-BLAST系统的处理装置
公开(公告)号：US07571203B2
公开(公告)日：2009-08-04
申请号：US10972235
申请日：2004-10-21
申请人： In-San Jeon , Hyuk Kim , Jae-Seok Kim , Kyung-Soo Kim , Hee-Bum Jung , Jong-Dae Kim
发明人： In-San Jeon , Hyuk Kim , Jae-Seok Kim , Kyung-Soo Kim , Hee-Bum Jung , Jong-Dae Kim
IPC分类号： G06F7/32
CPC分类号： H04L1/0656 , G06F17/16 , H04L25/0242
摘要： Disclosed is a V-BLAST system for a MIMO communication system.In the V-BLAST system for a MIMO communication system, a pseudo inverse matrix calculator receives a channel transfer function matrix including channel information and produces a cofactor matrix and a determinant for a pseudo inverse matrix. A norm & minimum calculator calculates a minimum index for the cofactor matrix outputted from the pseudo inverse matrix calculator, a weight vector selector selects a row vector having the minimum index and calculates a transposed matrix for the row vector; an adder adds the transposed matrix to a received input symbol, and a subtractor subtracts the determinant to the output. A demapper performs a determined function operation to the output and produces estimated information.
摘要翻译：公开了一种用于MIMO通信系统的V-BLAST系统。在用于MIMO通信系统的V-BLAST系统中，伪逆矩阵计算器接收包括信道信息的信道传递函数矩阵，并产生用于伪逆矩阵的辅因子矩阵和行列式。规范和最小计算器计算从伪逆矩阵计算器输出的辅因子矩阵的最小索引，权重向量选择器选择具有最小索引的行向量并计算行向量的转置矩阵; 加法器将转置的矩阵添加到接收到的输入符号，并且减法器将输出的行列式减去。解映射器对输出执行确定的功能操作并产生估计信息。

93. 发明申请

US20080130576A1 APPARATUS AND METHOD FOR INTERWORKING WIRELESS LAN AND PORTABLE INTERNET 失效
标题翻译：无线局域网和便携式互联网的装置和方法
公开(公告)号：US20080130576A1
公开(公告)日：2008-06-05
申请号：US11926650
申请日：2007-10-29
申请人： Sun-Mi Jun , Kyung-Soo Kim , Jee-Hwan Ahn , Song-In Choi , Dong-Soo Jung , Byoung-Chun Jeon
发明人： Sun-Mi Jun , Kyung-Soo Kim , Jee-Hwan Ahn , Song-In Choi , Dong-Soo Jung , Byoung-Chun Jeon
IPC分类号： H04Q7/20 , H04Q7/36
CPC分类号： H04W76/15 , H04W28/18 , H04W92/02
摘要： The present invention relates to a device for interworking a wireless local area network (WLAN) and a portable Internet. The device establishes a first wireless data path following a first wireless communication protocol with a first network, and establishes a plurality of the second wireless data paths through the first wireless data paths. Here, the plurality of the second wireless data paths follow a second wireless communication protocol and respectively correspond to a plurality of terminal devices. Subsequently, the device establishes a plurality of first network links respectively corresponding to the plurality of terminal devices with the first network, and stores mapping information for the first network link corresponding to a relationship between the plurality of terminal devices and the plurality of first network links.
摘要翻译：本发明涉及一种用于互连无线局域网（WLAN）和便携式因特网的装置。该装置根据第一无线通信协议与第一网络建立第一无线数据路径，并且通过第一无线数据路径建立多个第二无线数据路径。这里，多个第二无线数据路径遵循第二无线通信协议，并且分别对应于多个终端设备。随后，设备分别与具有第一网络的多个终端设备相对应地建立多个第一网络链路，并存储对应于多个终端设备与多个第一网络链路之间的关系的第一网络链路的映射信息。

94. 发明申请

US20070274403A1 Method for Constituting Layered Cell in Ofdma System 审中-公开
标题翻译：在系统中构建分层细胞的方法
公开(公告)号：US20070274403A1
公开(公告)日：2007-11-29
申请号：US10584437
申请日：2004-12-22
申请人： Sung-Cheol Chang , Jae-Sun Cha , Kyung-Soo Kim , Jee Hwan Ahn
发明人： Sung-Cheol Chang , Jae-Sun Cha , Kyung-Soo Kim , Jee Hwan Ahn
IPC分类号： H04L27/28
CPC分类号： H04L5/023 , H04L27/2608 , H04W16/02
摘要： Disclosed is a method for constituting a layered cell, which is for constituting a cell in an OFDMA (Orthogonal Frequency Division Multiple Access) mobile communication system. The method includes: (a) dividing L carriers having orthogonality into M sub-channels; (b) dividing the carriers into N groups each having the M sub-channels; (c) grouping the N groups by an arbitrary integer into K classes; and (d) constituting a plurality of layered cells corresponding to the K classes. According to the present invention, the conception of the independent classes is introduced for a plurality of carriers to facilitate the use of the carriers to a system requiring an independent wireless area, allowing design of sectors and cells at a single frequency.
摘要翻译：公开了一种用于构成OFDMA（正交频分多址）移动通信系统中的小区的分层小区的方法。该方法包括：（a）将具有正交性的L个载波分成M个子信道; （b）将载波划分成各具有M个子信道的N个组; （c）将N组按任意整数分组为K类; 和（d）构成对应于K类的多个分层单元。根据本发明，针对多个载波引入独立类的概念，以便于将载波用于需要独立无线区域的系统，允许在单个频率上设计扇区和小区。

95. 发明申请

US20060240636A1 Trench isolation methods of semiconductor device 审中-公开
标题翻译：半导体器件的沟槽隔离方法
公开(公告)号：US20060240636A1
公开(公告)日：2006-10-26
申请号：US11358454
申请日：2006-02-21
申请人： Hyuk-Ju Ryu , Heon-Jong Shin , Hee-Sung Kang , Choong-Ryul Ryou , Mu-Kyeng Jung , Kyung-Soo Kim
发明人： Hyuk-Ju Ryu , Heon-Jong Shin , Hee-Sung Kang , Choong-Ryul Ryou , Mu-Kyeng Jung , Kyung-Soo Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/76237 , H01L21/76224 , H01L21/823878
摘要： In a trench isolation method, a semiconductor substrate having an N-MOS region and a P-MOS region is prepared. A first mask pattern exposing an N-MOS field region is formed on the N-MOS region, and a second mask pattern exposing a P-MOS field region is formed on the P-MOS region. A first photoresist pattern is formed to cover the P-MOS region and expose the N-MOS region. First impurity ions are implanted into the N-MOS region, using the first mask pattern and the first photoresist pattern as ion implantation masks, thereby forming a first impurity layer in the N-MOS field region. In this case, a portion of the first impurity layer is formed to extend below the first mask pattern. The first photoresist pattern is removed. The semiconductor substrate is etched using the first and second mask patterns as etch masks, thereby forming trenches in the N-MOS field region and the P-MOS field region and concurrently, forming a first impurity pattern of the first impurity layer remaining below the first mask pattern. A trench isolation layer filling the trenches is then formed.
摘要翻译：在沟槽隔离方法中，制备具有N-MOS区和P-MOS区的半导体衬底。在N-MOS区形成露出N-MOS场区的第一掩模图案，在P-MOS区形成露出P-MOS场区的第二掩模图案。形成第一光致抗蚀剂图案以覆盖P-MOS区域并暴露N-MOS区域。使用第一掩模图案和第一光致抗蚀剂图案作为离子注入掩模将第一杂质离子注入到N-MOS区域中，从而在N-MOS场区域中形成第一杂质层。在这种情况下，第一杂质层的一部分形成为延伸到第一掩模图案的下方。去除第一光致抗蚀剂图案。使用第一和第二掩模图案作为蚀刻掩模蚀刻半导体衬底，从而在N-MOS场区和P-MOS场区中形成沟槽，同时，形成第一杂质图案的第一杂质图案保留在第一掩模图案。然后形成填充沟槽的沟槽隔离层。

96. 发明授权

US07094694B2 Semiconductor device having MOS varactor and methods for fabricating the same 有权
标题翻译：具有MOS变容二极管的半导体器件及其制造方法
公开(公告)号：US07094694B2
公开(公告)日：2006-08-22
申请号：US11023623
申请日：2004-12-29
申请人： Kong-Soo Cheong , Ki-Seog Youn , Kyung-Soo Kim
发明人： Kong-Soo Cheong , Ki-Seog Youn , Kyung-Soo Kim
IPC分类号： H01L21/44
CPC分类号： H01L29/6659 , H01L27/0629 , H01L29/665 , H01L29/6656
摘要： In a method for manufacturing a semiconductor device, a gate electrode is formed in a first region. A silicide blocking layer is patterned such that a first gate spacer is formed on sidewalls of the gate electrode, and a silicide blocking layer pattern is formed in a second region. A lightly doped source/drain region is formed on surface of the first region. A second gate spacer is formed on sidewalls of the first gate spacer. A heavily doped source/drain region is formed on the surface of the first region. A silicide layer is formed on the gate electrode and the heavily doped source/drain region in the first region.
摘要翻译：在制造半导体器件的方法中，栅电极形成在第一区域中。图案化硅化物阻挡层，使得第一栅极间隔物形成在栅电极的侧壁上，并且在第二区域中形成硅化物阻挡层图案。在第一区域的表面上形成轻掺杂的源极/漏极区域。在第一栅极间隔物的侧壁上形成第二栅极间隔物。在第一区域的表面上形成重掺杂的源极/漏极区域。在栅电极和第一区域中的重掺杂源极/漏极区域上形成硅化物层。

97. 发明申请

US20050149596A1 Processing device for a pseudo inverse matrix and V-BLAST system 失效
标题翻译：用于伪逆矩阵和V-BLAST系统的处理装置
公开(公告)号：US20050149596A1
公开(公告)日：2005-07-07
申请号：US10972235
申请日：2004-10-21
申请人： In-San Jeon , Hyuk Kim , Jae-Seok Kim , Kyung-Soo Kim , Hee-Bum Jung , Jong-Dae Kim
发明人： In-San Jeon , Hyuk Kim , Jae-Seok Kim , Kyung-Soo Kim , Hee-Bum Jung , Jong-Dae Kim
IPC分类号： H04B7/02 , G06F17/10 , G06F17/16 , H04L1/06 , H04L25/02
CPC分类号： H04L1/0656 , G06F17/16 , H04L25/0242
摘要： Disclosed is a V-BLAST system for a MIMO communication system. In the V-BLAST system for a MIMO communication system, a pseudo inverse matrix calculator receives a channel transfer function matrix including channel information and produces a cofactor matrix and a determinant for a pseudo inverse matrix. A norm & minimum calculator calculates a minimum index for the cofactor matrix outputted from the pseudo inverse matrix calculator, a weight vector selector selects a row vector having the minimum index and calculates a transposed matrix for the row vector; an adder adds the transposed matrix to a received input symbol, and a subtractor subtracts the determinant to the output. A demapper performs a determined function operation to the output and produces estimated information.
摘要翻译：公开了一种用于MIMO通信系统的V-BLAST系统。在用于MIMO通信系统的V-BLAST系统中，伪逆矩阵计算器接收包括信道信息的信道传递函数矩阵，并产生用于伪逆矩阵的辅因子矩阵和行列式。规范和最小计算器计算从伪逆矩阵计算器输出的辅因子矩阵的最小索引，权重向量选择器选择具有最小索引的行向量并计算行向量的转置矩阵; 加法器将转置的矩阵添加到接收到的输入符号，并且减法器将输出的行列式减去。解映射器对输出执行确定的功能操作并产生估计信息。

98. 发明申请

US20050144209A1 Apparatus and method for selectively performing Fast Hadamard Transform or fast fourier transform 失效
标题翻译：用于选择性地执行快速Hadamard变换或快速傅立叶变换的装置和方法
公开(公告)号：US20050144209A1
公开(公告)日：2005-06-30
申请号：US10969504
申请日：2004-10-19
申请人： Ik-Soo Eo , Young-Seok Baek , Jung-Bum Kim , Hee-Bum Jung , Kyung-Soo Kim
发明人： Ik-Soo Eo , Young-Seok Baek , Jung-Bum Kim , Hee-Bum Jung , Kyung-Soo Kim
IPC分类号： H04L27/38 , G06F15/00 , G06F17/14
CPC分类号： G06F17/142 , G06F17/145
摘要： Disclosed is an apparatus for performing both FHT (Fast Hadamard Transform) and FFT (Fast Fourier Transform). This apparatus determines the phase coefficients as constantly “1” when performing the FHT, and changes the input order of input data to a reverse order of bits when performing the FFT. In addition, the apparatus, which can process a plurality of input data sets simultaneously, classifies the received signals into multi-path signals and multi-antenna signals, thus processing the multi-path signals separately from the multi-antenna signals, or directly processes multi-antenna signals.
摘要翻译：公开了一种用于执行FHT（Fast Hadamard Transform）和FFT（快速傅立叶变换）的装置。该装置在执行FHT时确定相位系数恒定为“1”，并且在执行FFT时将输入数据的输入顺序改变为相反的位数。另外，可以同时处理多个输入数据集的装置将接收到的信号分类成多径信号和多天线信号，从而与多天线信号分开处理多路信号，或直接处理多天线信号。

99. 发明授权

US6011425A CMOS offset trimming circuit and offset generation circuit 失效
标题翻译： CMOS偏移调整电路和偏移生成电路
公开(公告)号：US6011425A
公开(公告)日：2000-01-04
申请号：US893459
申请日：1997-07-11
申请人： Chang-Jun Oh , Ook Kim , Jong-Kee Kwon , Jong-Ryul Lee , Won-Chul Song , Kyung-Soo Kim
发明人： Chang-Jun Oh , Ook Kim , Jong-Kee Kwon , Jong-Ryul Lee , Won-Chul Song , Kyung-Soo Kim
IPC分类号： H03K19/00 , G11C17/18 , H01H37/76
CPC分类号： G11C17/18
摘要： A CMOS offset trimming circuit and offset generation circuit for obtaining the corrected optimum offset value for correcting the offset generated in the CMOS analog circuit. An offset trimming circuit comprises a flip-flop for loading a data to be used for obtaining an optimum offset value or a data to be trimmed according to an input clock, a fuse circuit for setting the circuit with a corrected optimum offset value obtained in a corresponding mode by receiving the data loaded on the flip-flop and the mode selection signal as an input signal, and a selection logic circuit for outputting a selected signal as a trimming output signal by selecting one from the group consisting of the data loaded on the flip-flop and the data output from the fuse circuit according to the operation mode.
摘要翻译： CMOS偏移调整电路和偏移生成电路，用于获得用于校正在CMOS模拟电路中产生的偏移的校正的最佳偏移值。偏移修整电路包括用于根据输入时钟加载要用于获得最佳偏移值的数据或要修整的数据的触发器，用于设置具有校正的最佳偏移值的电路的熔丝电路，通过接收加载在触发器上的数据和模式选择信号作为输入信号的相应模式，以及选择逻辑电路，用于通过从由加载在所述触发器上的数据组合的组中选择一个来选择所选择的信号作为微调输出信号触发器和根据操作模式从熔丝电路输出的数据。

100. 发明授权

US5886550A Integrated circuit built-in type supply power delay circuit 失效
标题翻译：集成电路内置式电源延时电路
公开(公告)号：US5886550A
公开(公告)日：1999-03-23
申请号：US877408
申请日：1997-06-16
申请人： Jong-Kee Kwon , Gyu-Dong Kim , Ook Kim , Chang-Jun Oh , Jong-Ryul Lee , Won-Chul Song , Kyung-Soo Kim
发明人： Jong-Kee Kwon , Gyu-Dong Kim , Ook Kim , Chang-Jun Oh , Jong-Ryul Lee , Won-Chul Song , Kyung-Soo Kim
IPC分类号： G11C5/14 , H03K17/22
CPC分类号： H03K17/223
摘要： An integrated circuit built-in type power delay circuit which is capable of supplying a stable supply power to each circuit of the integrated circuit by generating a supply power control signal voltage after a predetermined time. The circuit includes a receiving unit for receiving a supply voltage VDD and charging the same, a supplying unit for supplying a current, an inverting unit for inverting an output value from the charging unit, a switching unit controlled in accordance with an output value from the inverting unit for switching an output from the current supply unit, a current regenerating unit for receiving a control of the switching unit and discharging an output value from the charging unit, an electric potential value conversion unit controlled by an output value from the inverting unit for converting an output value from the charging unit into a low level, and a buffering unit for receiving an output value from the inverting unit for buffering the output value and outputting a non-inverted signal.
摘要翻译：一种集成电路内置型功率延迟电路，其能够通过在预定时间之后产生电源功率控制信号电压来向集成电路的每个电路提供稳定的供电。该电路包括：接收单元，用于接收电源电压VDD并对其进行充电;提供单元，用于提供电流;反相单元，用于反转来自充电单元的输出值;开关单元，根据来自用于切换来自电流供应单元的输出的反相单元，用于接收开关单元的控制并从充电单元放电输出值的电流再生单元，由来自反相单元的输出值控制的电位值转换单元，将来自充电单元的输出值转换为低电平;以及缓冲单元，用于从反相单元接收输出值，用于缓冲输出值并输出非反相信号。

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