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1. 发明授权

US07094694B2 Semiconductor device having MOS varactor and methods for fabricating the same 有权
标题翻译：具有MOS变容二极管的半导体器件及其制造方法
公开(公告)号：US07094694B2
公开(公告)日：2006-08-22
申请号：US11023623
申请日：2004-12-29
申请人： Kong-Soo Cheong , Ki-Seog Youn , Kyung-Soo Kim
发明人： Kong-Soo Cheong , Ki-Seog Youn , Kyung-Soo Kim
IPC分类号： H01L21/44
CPC分类号： H01L29/6659 , H01L27/0629 , H01L29/665 , H01L29/6656
摘要： In a method for manufacturing a semiconductor device, a gate electrode is formed in a first region. A silicide blocking layer is patterned such that a first gate spacer is formed on sidewalls of the gate electrode, and a silicide blocking layer pattern is formed in a second region. A lightly doped source/drain region is formed on surface of the first region. A second gate spacer is formed on sidewalls of the first gate spacer. A heavily doped source/drain region is formed on the surface of the first region. A silicide layer is formed on the gate electrode and the heavily doped source/drain region in the first region.
摘要翻译：在制造半导体器件的方法中，栅电极形成在第一区域中。图案化硅化物阻挡层，使得第一栅极间隔物形成在栅电极的侧壁上，并且在第二区域中形成硅化物阻挡层图案。在第一区域的表面上形成轻掺杂的源极/漏极区域。在第一栅极间隔物的侧壁上形成第二栅极间隔物。在第一区域的表面上形成重掺杂的源极/漏极区域。在栅电极和第一区域中的重掺杂源极/漏极区域上形成硅化物层。

2. 发明申请

US20050142779A1 Semiconductor device having MOS varactor and methods for fabricating the same 有权
标题翻译：具有MOS变容二极管的半导体器件及其制造方法
公开(公告)号：US20050142779A1
公开(公告)日：2005-06-30
申请号：US11023623
申请日：2004-12-29
申请人： Kong-Soo Cheong , Ki-Seog Youn , Kyung-Soo Kim
发明人： Kong-Soo Cheong , Ki-Seog Youn , Kyung-Soo Kim
IPC分类号： H01L21/336 , H01L27/06
CPC分类号： H01L29/6659 , H01L27/0629 , H01L29/665 , H01L29/6656
摘要： In a method for manufacturing a semiconductor device, a gate electrode is formed in a first region. A silicide blocking layer is patterned such that a first gate spacer is formed on sidewalls of the gate electrode, and a silicide blocking layer pattern is formed in a second region. A lightly doped source/drain region is formed on surface of the first region. A second gate spacer is formed on sidewalls of the first gate spacer. A heavily doped source/drain region is formed on the surface of the first region. A silicide layer is formed on the gate electrode and the heavily doped source/drain region in the first region.
摘要翻译：在制造半导体器件的方法中，栅电极形成在第一区域中。图案化硅化物阻挡层，使得第一栅极间隔物形成在栅电极的侧壁上，并且在第二区域中形成硅化物阻挡层图案。在第一区域的表面上形成轻掺杂的源极/漏极区域。在第一栅极间隔物的侧壁上形成第二栅极间隔物。在第一区域的表面上形成重掺杂的源极/漏极区域。在栅电极和第一区域中的重掺杂源极/漏极区域上形成硅化物层。

3. 发明申请

US20080188057A1 Trench isolation type semiconductor device which prevents a recess from being formed in a field region and method of fabricating the same 有权
标题翻译：防止在场区域形成凹部的沟槽隔离型半导体器件及其制造方法
公开(公告)号：US20080188057A1
公开(公告)日：2008-08-07
申请号：US12070808
申请日：2008-02-21
申请人： Ki-Seog Youn , Jong-Hyon Ahn , Deok-Hyung Lee , Sung-Gun Kang , Kong-Soo Cheong
发明人： Ki-Seog Youn , Jong-Hyon Ahn , Deok-Hyung Lee , Sung-Gun Kang , Kong-Soo Cheong
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.
摘要翻译：提供其中防止在场区域中形成凹部的沟槽隔离型半导体器件及其制造方法。沟槽隔离型半导体器件包括由有源区和场区定义的半导体衬底，在场区中形成的沟槽，沿着沟内部保形地形成的氧化物层，沿着氧化物层保形地形成的衬层，形成在包括氧化物层和衬垫层的沟槽内的场绝缘层，以及形成在场绝缘层上的场保护层，使得半导体衬底上不发生阶差。

4. 发明申请

US20070293045A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070293045A1
公开(公告)日：2007-12-20
申请号：US11808981
申请日：2007-06-14
申请人： Ki-Seog Youn , Jong-Hyon Ahn , Joo-Hyoung Lee , Kwang-Duk Kim
发明人： Ki-Seog Youn , Jong-Hyon Ahn , Joo-Hyoung Lee , Kwang-Duk Kim
IPC分类号： H01L21/302
CPC分类号： H01L21/76224
摘要： A semiconductor device may include a semiconductor substrate having a trench, a device isolation layer filling the trench, and a liner nitride layer disposed between the semiconductor substrate and the device isolation layer. The device isolation layer may additionally cover a portion of the substrate surrounding the trench. The liner nitride layer may have an upper portion and a lower portion, wherein the upper portion may be thinner than the lower portion. The liner nitride layer may reduce or prevent a recess from being generated between an active region and a device isolation region. Accordingly, a relatively high-quality semiconductor device may be fabricated using a simplified process.
摘要翻译：半导体器件可以包括具有沟槽的半导体衬底，填充沟槽的器件隔离层以及设置在半导体衬底和器件隔离层之间的衬里氮化物层。器件隔离层可以另外覆盖围绕沟槽的衬底的一部分。衬里氮化物层可以具有上部和下部，其中上部可以比下部更薄。衬里氮化物层可以减少或防止在有源区和器件隔离区之间产生凹陷。因此，可以使用简化的工艺来制造相对高质量的半导体器件。

5. 发明授权

US6100164A Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US6100164A
公开(公告)日：2000-08-08
申请号：US990720
申请日：1997-12-15
申请人： Kang-Sik Youn , Ki-Seog Youn , Ku-Chul Joung
发明人： Kang-Sik Youn , Ki-Seog Youn , Ku-Chul Joung
IPC分类号： H01L21/316 , H01L21/32 , H01L21/76
CPC分类号： H01L21/32
摘要： A semiconductor device and a method of fabricating the same are disclosed. The method includes the steps of forming an anti-oxidation layer on a substrate, forming an oxidizable layer on portions of the anti-oxidation layer to expose a portion of the anti-oxidation layer, varying a size of the exposed portion of the anti-oxidation layer by oxidizing at least a portion of the oxidizable layer, and forming a trench in the substrate according to the size of the exposed portion of the anti-oxidation layer. The semiconductor device includes an anti-oxidation layer formed on a substrate an oxidation layer formed on portions of the anti-oxidation layer by oxidizing at least a portion of an oxidizable layer, so as to define an isolation region of the semiconductor device, a trench formed in the substrate using the oxidation layer, and a field oxide layer formed in the trench.
摘要翻译：公开了一种半导体器件及其制造方法。该方法包括以下步骤：在基底上形成抗氧化层，在抗氧化层的部分上形成可氧化层，以暴露部分抗氧化层，改变抗氧化层的暴露部分的尺寸，通过氧化至少一部分可氧化层，以及根据抗氧化层的暴露部分的尺寸在衬底中形成沟槽。半导体器件包括通过氧化至少一部分可氧化层而形成在基底上的形成在抗氧化层的部分上的氧化层的抗氧化层，以便限定半导体器件的隔离区，沟槽使用氧化层在基板中形成，并且在沟槽中形成场氧化物层。

6. 发明授权

US07364987B2 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07364987B2
公开(公告)日：2008-04-29
申请号：US11034981
申请日：2005-01-14
申请人： Ki-Seog Youn , Jong-Hyon Ahn , Hee-Sung Kang , Tae-Woong Kang
发明人： Ki-Seog Youn , Jong-Hyon Ahn , Hee-Sung Kang , Tae-Woong Kang
IPC分类号： H01L21/322
CPC分类号： H01L29/6659 , H01L23/3171 , H01L23/564 , H01L29/665 , H01L2924/0002 , Y10S438/928 , H01L2924/00
摘要： In a method of forming a semiconductor device, a copper diffusion-prevention layer is formed underneath a substrate. Impurity regions are formed on the surface of the substrate. A copper wiring is electrically connected to the impurity regions. The copper diffusion-prevention layer is formed before forming the lightly doped source/drain regions to prevent copper atoms from diffusing into the substrate.
摘要翻译：在形成半导体器件的方法中，在衬底下形成铜扩散防止层。在基板的表面上形成杂质区域。铜布线与杂质区电连接。在形成轻掺杂源极/漏极区之前形成铜扩散防止层，以防止铜原子扩散到衬底中。

7. 发明申请

US20050158984A1 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20050158984A1
公开(公告)日：2005-07-21
申请号：US11034981
申请日：2005-01-14
申请人： Ki-Seog Youn , Jong-Hyon Ahn , Hee-Sung Kang , Tae-Woong Kang
发明人： Ki-Seog Youn , Jong-Hyon Ahn , Hee-Sung Kang , Tae-Woong Kang
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L23/00 , H01L23/31
CPC分类号： H01L29/6659 , H01L23/3171 , H01L23/564 , H01L29/665 , H01L2924/0002 , Y10S438/928 , H01L2924/00
摘要： In a method of forming a semiconductor device, a copper diffusion-prevention layer is formed underneath a substrate. Impurity regions are formed on the surface of the substrate. A copper wiring is electrically connected to the impurity regions. The copper diffusion-prevention layer is formed before forming the lightly doped source/drain regions to prevent copper atoms from diffusing into the substrate.
摘要翻译：在形成半导体器件的方法中，在衬底下形成铜扩散防止层。在基板的表面上形成杂质区域。铜布线与杂质区电连接。在形成轻掺杂源极/漏极区之前形成铜扩散防止层，以防止铜原子扩散到衬底中。

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