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91. 发明授权

US07977218B2 Thin oxide dummy tiling as charge protection 有权
标题翻译：薄氧化虚拟平铺作为电荷保护
公开(公告)号：US07977218B2
公开(公告)日：2011-07-12
申请号：US11645475
申请日：2006-12-26
申请人： Cinti Chen , Yi He , Wenmei Li , Zhizheng Liu , Ming-Sang Kwan , Yu Sun , Jean Yee-Mei Yang
发明人： Cinti Chen , Yi He , Wenmei Li , Zhizheng Liu , Ming-Sang Kwan , Yu Sun , Jean Yee-Mei Yang
IPC分类号： H01L21/00
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11568
摘要： Novel fabrication methods implement the use of dummy tiles to avoid the effects of in-line charging, ESD events, and such charge effects in the formation of a memory device region region. One method involves forming at least a portion of a memory core array upon a semiconductor substrate that involves forming STI structures in the substrate substantially surrounding a memory device region region within the array. An oxide layer is formed over the substrate in the memory device region region and over the STI's, wherein an inner section of the oxide layer formed over the memory device region region is thicker than an outer section of the oxide layer formed over the STI's. A first polysilicon layer is then formed over the inner and outer sections comprising one or more dummy tiles formed over one or more outer sections and electrically connected to at least one inner section.
摘要翻译：新颖的制造方法实现使用虚拟瓦片以避免在形成存储器件区域区域中的在线充电，ESD事件和这种电荷效应的影响。一种方法包括在半导体衬底上形成至少一部分存储器芯阵列，该半导体衬底涉及在衬底中形成基本上围绕阵列内的存储器件区域区域的STI结构。在存储器件区域和STI之上的衬底上形成氧化物层，其中形成在存储器件区域上的氧化物层的内部部分比在STI上形成的氧化物层的外部部分更厚。然后在内部和外部部分上形成第一多晶硅层，包括形成在一个或多个外部部分上并且电连接到至少一个内部部分的一个或多个虚拟瓦片。

92. 发明申请

US20110077358A1 Functional Polymer With Pendant Color Changing Indicator 失效
标题翻译：功能聚合物与吊坠颜色变化指示器
公开(公告)号：US20110077358A1
公开(公告)日：2011-03-31
申请号：US12666796
申请日：2008-06-27
申请人： Yifan Zhang , Yi He , Diane R. Wolk , Mark W. Nelson , Larry Richard Krepski , Stephen Richard Hartshorn , Douglas Eugend Weiss
发明人： Yifan Zhang , Yi He , Diane R. Wolk , Mark W. Nelson , Larry Richard Krepski , Stephen Richard Hartshorn , Douglas Eugend Weiss
IPC分类号： C08G73/06 , C08B15/06
CPC分类号： C09B69/103 , C08F8/00 , C08J3/20 , D06P1/004 , D06P1/0072 , D06P1/647 , D06P1/65112 , D06P5/2005
摘要： A functionalized polymer is disclosed that comprises the reaction product of a polymer having one or more pendant reactive functional groups and a color changing indictor having a co-reactive functional group. The co-reactive functional group of the color changing is able to react with the reactive functional group of the polymer to form a covalent bond. Therefore, the color changing indicator is pendant from the polymer. The color changing indicator maintains its ability to produce a visually discernable color change in the presence of an associated stimulus.
摘要翻译：公开了包含具有一个或多个侧链反应性官能团的聚合物和具有共反应性官能团的变色指示剂的反应产物的官能化聚合物。颜色变化的共反应性官能团能够与聚合物的反应性官能团反应以形成共价键。因此，变色指示剂从聚合物悬挂。颜色变化指示器保持其在相关联的刺激的存在下产生视觉上可辨别的颜色变化的能力。

93. 发明授权

US07720137B2 Characterization of a frequency response for a frequency translation device 有权
标题翻译：频率转换装置的频率响应的表征
公开(公告)号：US07720137B2
公开(公告)日：2010-05-18
申请号：US11583188
申请日：2006-10-18
申请人： Yi He , Marcus K. Da Silva
发明人： Yi He , Marcus K. Da Silva
IPC分类号： H04B17/00
CPC分类号： G01R31/2839 , G01R27/28 , G01R31/2822
摘要： A method of characterizing the frequency response of a frequency translation device over a wide IF bandwidth is based on a two-dimensional model to generate calibration data for a device at run-time. The model is a function of a center frequency and frequency offset for a plurality of center frequencies over a wide system bandwidth to produce a frequency response at each center frequency. The frequency responses at each center frequency are scaled and normalized relative to a reference frequency and stored.
摘要翻译：在宽IF带宽上表征频率转换设备的频率响应的方法基于二维模型，以在运行时产生设备的校准数据。该模型是在宽系统带宽上的多个中心频率的中心频率和频率偏移的函数，以在每个中心频率处产生频率响应。在每个中心频率处的频率响应相对于参考频率被缩放和归一化并被存储。

94. 发明申请

US20100075560A1 Ligand Graft Functionalized Substrates 有权
公开(公告)号：US20100075560A1
公开(公告)日：2010-03-25
申请号：US12562381
申请日：2009-09-18
申请人： Kannan Seshadri , Jerald K. Rasmussen , Clinton P. Waller, JR. , Douglas E. Weiss , Yi He
发明人： Kannan Seshadri , Jerald K. Rasmussen , Clinton P. Waller, JR. , Douglas E. Weiss , Yi He
IPC分类号： C07C279/26 , D04H13/00 , C08G73/04 , B05D3/06
CPC分类号： B01D39/1676 , C07K1/34 , C08J7/18 , C08J2327/14 , Y10T428/249978 , Y10T428/249991 , Y10T428/2935 , Y10T442/2033 , Y10T442/2525 , Y10T442/60
摘要： Polyethyleneimine and polyalkylene biguanide ligand functionalized substrates, methods of making ligand functionalized substrates, and methods of using functionalized substrates are disclosed.

95. 发明申请

US20090161462A1 CONTROLLING AC DISTURBANCE WHILE PROGRAMMING 有权
标题翻译：控制交流干扰编程
公开(公告)号：US20090161462A1
公开(公告)日：2009-06-25
申请号：US11963508
申请日：2007-12-21
申请人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
发明人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
IPC分类号： G11C7/02
CPC分类号： G11C16/3418 , G11C16/0416 , G11C16/24 , G11C16/3427
摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.
摘要翻译：提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

96. 发明申请

US20080151644A1 Cycling improvement using higher erase bias 有权
标题翻译：使用更高的擦除偏置循环改进
公开(公告)号：US20080151644A1
公开(公告)日：2008-06-26
申请号：US11724711
申请日：2007-03-16
申请人： Sheung-Hee Park , Xuguang Wang , Wing Leung , Ming-Sang Kwan , Yi He , Edward Franklin Runnion
发明人： Sheung-Hee Park , Xuguang Wang , Wing Leung , Ming-Sang Kwan , Yi He , Edward Franklin Runnion
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/16 , G11C16/14
摘要： Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cells for a predetermined number of gate pulses or until all the memory cells are erased. In another embodiment, an erase bias circuit is provided for erasing a sector of flash memory cells, the circuit comprising row and column decoders that selects wordline rows and columns of cells, respectively, a supply bias arrangement that provides source and drain supply voltages for the sector, and a patterned pulse bias arrangement configured to provide a pulsed gate voltage pattern to gates of the cells selected by the row decoder and a drain voltage pattern to the drains of the cells selected by the column decoder.
摘要翻译：提供了擦除闪存单元的方法，其提高了擦除循环速度和可靠性。一个实施例包括将阶梯式或倾斜的漏极电压图案交互地施加到存储器单元的漏极，以及脉冲栅极电压图案到达预定数量的栅极脉冲的存储器单元的栅极，或者直到所有存储器单元被擦除。在另一个实施例中，提供擦除偏置电路用于擦除闪速存储器单元的扇区，该电路包括分别选择字线行和单元列的行和列解码器，该电源偏置装置为以及图案化脉冲偏压装置，其被配置为向由行解码器选择的单元的栅极和漏极电压图案提供脉冲栅极电压图案到由列解码器选择的单元的漏极。

97. 发明申请

US20080150006A1 Using implanted poly-1 to improve charging protection in dual-poly process 有权
标题翻译：使用植入poly-1改善双重聚合过程中的充电保护
公开(公告)号：US20080150006A1
公开(公告)日：2008-06-26
申请号：US11724726
申请日：2007-03-16
申请人： Ming-Sang Kwan , Bradley Marc Davis , Jean Yee-Mei Yang , Zhizheng Liu , Yi He
发明人： Ming-Sang Kwan , Bradley Marc Davis , Jean Yee-Mei Yang , Zhizheng Liu , Yi He
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L29/7923 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.
摘要翻译：本发明涉及在形成基于晶体管的存储器件中实现双重聚合工艺。该过程允许在沉积第二多晶硅层之后选择性地掺杂第一多晶硅层。该掺杂增加了第一多晶硅层的导电性，其可以实现针对多位磁芯阵列的更强鲁棒的充电保护和更均匀的电荷分布。

98. 发明申请

US20080024193A1 APPARATUS, SYSTEM, AND METHOD FOR MULTIFUNCTIONAL PIN IN AN INTEGRATED CIRCUIT 失效
标题翻译：集成电路中多功能引脚的装置，系统和方法
公开(公告)号：US20080024193A1
公开(公告)日：2008-01-31
申请号：US11461303
申请日：2006-07-31
申请人： Tuck Meng Chan , Xiao Wu Gong , Yi He , Meng Kiat Jeoh , Junyang Luo
发明人： Tuck Meng Chan , Xiao Wu Gong , Yi He , Meng Kiat Jeoh , Junyang Luo
IPC分类号： H03K17/687
CPC分类号： H03K17/0822 , H03K17/133
摘要： Some embodiments of the invention include an integrated circuit having a node or pin to detect a first information during a first a detection period and to detect a second information during a second detection period. In some embodiments, the information at the pin may allow the integrated circuit to operate in a quasi-resonant operation. Other embodiments are described and claimed.
摘要翻译：本发明的一些实施例包括具有节点或引脚以在第一检测周期期间检测第一信息并在第二检测周期期间检测第二信息的集成电路。在一些实施例中，引脚处的信息可以允许集成电路在准谐振操作中操作。描述和要求保护其他实施例。

99. 发明授权

US07215577B2 Flash memory cell and methods for programming and erasing 有权
标题翻译：闪存单元和编程和擦除的方法
公开(公告)号：US07215577B2
公开(公告)日：2007-05-08
申请号：US11511763
申请日：2006-08-29
申请人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
发明人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
IPC分类号： G11C11/34 , G11C16/04 , H01L29/78
CPC分类号： G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/66833
摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.
摘要翻译：提供了闪存单元，其包括形成在衬底沟道区上方的电介质材料，在电介质材料上形成的电荷俘获材料，以及形成在电荷俘获材料上的控制栅。可以通过将电子从控制栅极引导到电荷捕获材料中来提高电池阈值电压来编程电池。电子可以通过将衬底耦合到衬底电压电势，并将控制栅极耦合到栅极电压电位，其中栅极电压电位低于衬底电压电位，从控制栅极引导到电荷俘获材料。可以通过将电子从电荷捕获材料引入控制栅极来降低闪速存储器单元的阈值电压，例如通过将衬底耦合到衬底电压电位，以及将控制栅极耦合到栅极电压电位来擦除电池，其中栅极电压电位高于衬底电压电位。

100. 发明申请

US20060091439A1 System and method for protecting semiconductor devices 有权
标题翻译：用于保护半导体器件的系统和方法
公开(公告)号：US20060091439A1
公开(公告)日：2006-05-04
申请号：US10976816
申请日：2004-11-01
申请人： Ihsan Djomehri , Mark Randolph , Yi He , Wei Zheng
发明人： Ihsan Djomehri , Mark Randolph , Yi He , Wei Zheng
IPC分类号： H01L29/94
CPC分类号： H01L27/115 , H01L27/0288
摘要： A semiconductor memory device includes a group of word lines and a structure that is configured to dissipate current from the group of word lines during fabrication of the semiconductor memory device.
摘要翻译：半导体存储器件包括一组字线和被配置成在制造半导体存储器件期间消散来自字线组的电流的结构。

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