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91. 发明授权

US08030709B2 Metal gate stack and semiconductor gate stack for CMOS devices 有权
标题翻译： CMOS器件的金属栅极堆叠和半导体栅极堆叠
公开(公告)号：US08030709B2
公开(公告)日：2011-10-04
申请号：US11954918
申请日：2007-12-12
申请人： Charlotte D. Adams , Bruce B. Doris , Philip Fisher , William K. Henson , Jeffrey W. Sleight
发明人： Charlotte D. Adams , Bruce B. Doris , Philip Fisher , William K. Henson , Jeffrey W. Sleight
IPC分类号： H01L21/70 , H01L27/148 , H01L27/12 , H01L21/84 , H01L21/338
CPC分类号： H01L29/4983 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L27/092 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/78
摘要： A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed on the semiconductor substrate. Oxygen-impermeable dielectric spacers are formed on the sidewalls of the semiconductor gate stack and the high-k material metal gate stack. The oxygen-impermeable dielectric spacer on the semiconductor gate stack is removed, while the oxygen impermeable dielectric spacer on the high-k material metal gate electrode is preserved. A low-k dielectric spacer is formed on the semiconductor gate stack, which provides a low parasitic capacitance for the device employing the semiconductor gate stack.
摘要翻译：包括基于氧化硅的栅极电介质和掺杂的半导体材料的半导体栅极堆叠形成在半导体衬底上。还在半导体衬底上形成包括高k栅极电介质和金属栅极部分的高k材料金属栅电极。在半导体栅极堆叠和高k材料金属栅极堆叠的侧壁上形成氧气不可渗透的电介质间隔物。除去半导体栅极堆叠上的不透氧电介质间隔物，同时保留高k材料金属栅电极上的不透氧电介质间隔物。在半导体栅极叠层上形成一个低k电介质隔离层，为采用半导体栅极堆叠的器件提供了低寄生电容。

92. 发明授权

US07943460B2 High-K metal gate CMOS 有权
标题翻译：高K金属门CMOS
公开(公告)号：US07943460B2
公开(公告)日：2011-05-17
申请号：US12426457
申请日：2009-04-20
申请人： Renee T. Mo , Huiming Bu , Michael P. Chudzik , William K. Henson , Mukesh V. Khare , Vijay Narayanan
发明人： Renee T. Mo , Huiming Bu , Michael P. Chudzik , William K. Henson , Mukesh V. Khare , Vijay Narayanan
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28097 , H01L21/28194 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66651 , H01L29/78
摘要： A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.
摘要翻译：提供一种形成半导体器件的方法，包括在基板的p型器件区域的顶部形成含Ge层。此后，在衬底的第二部分中形成第一电介质层，并且在衬底的第二部分中覆盖第一介电层并覆盖衬底的第一部分上形成第二电介质层。然后，栅极结构可以形成在衬底的p型器件区域和n型器件区域的顶部，其中n型器件区域的栅极结构包括稀土金属。

93. 发明授权

US07838908B2 Semiconductor device having dual metal gates and method of manufacture 有权
标题翻译：具有双金属栅极的半导体器件及其制造方法
公开(公告)号：US07838908B2
公开(公告)日：2010-11-23
申请号：US12359520
申请日：2009-01-26
申请人： Unoh Kwon , Siddarth A. Krishnan , Takashi Ando , Michael P. Chudzik , Martin M. Frank , William K. Henson , Rashmi Jha , Yue Liang , Vijay Narayanan , Ravikumar Ramachandran , Keith Kwong Hon Wong
发明人： Unoh Kwon , Siddarth A. Krishnan , Takashi Ando , Michael P. Chudzik , Martin M. Frank , William K. Henson , Rashmi Jha , Yue Liang , Vijay Narayanan , Ravikumar Ramachandran , Keith Kwong Hon Wong
IPC分类号： H01L27/10
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/4966 , H01L29/517
摘要： A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.
摘要翻译：半导体器件包括：半导体衬底; 形成在衬底上的PFET，PFET包括设置在衬底上的SiGe层，设置在SiGe层上的高K电介质层，设置在高k电介质层上的第一金属层，设置在第一中间层上的第一中间层第一金属层，设置在第一中间层上的第二金属层，设置在第二金属层上的第二中间层和设置在第二中间层上的第三金属层; 形成在衬底上的NFET，NFET包括高k电介质层，高k电介质层设置在衬底上，第二中间层，第二中间层设置在高k电介质层上，并且第三金属层，第三金属层设置在第二中间层上。或者，省略第一金属层。制造该器件的方法包括提供SiO 2和α-硅层或dBARC层。

94. 发明授权

US07749822B2 Method of forming a resistor and an FET from the metal portion of a MOSFET metal gate stack 有权
标题翻译：从MOSFET金属栅极叠层的金属部分形成电阻和FET的方法
公开(公告)号：US07749822B2
公开(公告)日：2010-07-06
申请号：US11869271
申请日：2007-10-09
申请人： Gregory G. Freeman , William K. Henson
发明人： Gregory G. Freeman , William K. Henson
IPC分类号： H01L21/00 , H01L27/12
CPC分类号： H01L27/0629 , H01L21/28088 , H01L28/20 , H01L29/4966 , H01L29/6659 , H01L29/7833
摘要： An integrated semiconductor device includes a resistor and an FET device formed from a stack of layers. The stack of layers includes a dielectric layer formed on a substrate; a metal conductor layer having lower electrical resistance formed on the dielectric layer; and a polysilicon layer formed on the metal conductor layer. A resistor stack is formed by patterning a portion of the original stack of layers into a resistor. An FET stack is formed from another portion of the original stack of layers. The FET stack is doped to form a gate electrode and the resistor stack is doped aside from the resistor portion thereof. Then terminals are formed at distal ends of the resistor in a doped portion of the polysilicon layer. Alternatively, the polysilicon layer is etched away from the resistor stack followed by forming terminals at distal ends of the metal conductor in the resistor stack.
摘要翻译：集成半导体器件包括由一叠层形成的电阻器和FET器件。层叠层包括在基板上形成的电介质层; 在电介质层上形成具有较低电阻的金属导体层; 以及形成在金属导体层上的多晶硅层。通过将原始堆叠层的一部分图案化成电阻器形成电阻器堆叠。 FET堆叠由原始层叠层的另一部分形成。掺杂FET堆叠以形成栅电极，并且电阻器堆叠从其电阻器部分被掺杂。然后，端子形成在多晶硅层的掺杂部分中的电阻器的远端处。或者，将多晶硅层从电阻器堆叠中蚀刻掉，然后在电阻器堆叠中的金属导体的远端形成端子。

95. 发明授权

US07666790B2 Silicide gate field effect transistors and methods for fabrication thereof 失效
标题翻译：硅化物栅场效应晶体管及其制造方法
公开(公告)号：US07666790B2
公开(公告)日：2010-02-23
申请号：US11380528
申请日：2006-04-27
申请人： Zhijiong Luo , William K. Henson , Christian Lavoie , Huilong Zhu
发明人： Zhijiong Luo , William K. Henson , Christian Lavoie , Huilong Zhu
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/28097 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method for fabricating a silicide gate field effect transistor includes masking a silicon source/drain region prior to forming the silicide gate by annealing a metal silicide forming metal layer contacting a silicon-containing gate. The silicide gate may be either a fully silicided gate or a partially silicided gate. After unmasking the source/drain region a silicide layer may be formed upon the source/drain region, and also upon the partially silicided gate. The second silicide layer and the partially silicided gate also provide a fully silicided gate.
摘要翻译：一种用于制造硅化物栅极场效应晶体管的方法，包括：在形成硅化物栅极之前，通过使接触含硅栅极的金属硅化物形成金属层退火来掩蔽硅源/漏极区。硅化物栅极可以是完全硅化的栅极或部分硅化的栅极。在去掩蔽源/漏区之后，可以在源极/漏极区上形成硅化物层，并且还可以在部分硅化物栅极上形成硅化物层。第二硅化物层和部分硅化物栅极还提供完全硅化的栅极。

96. 发明申请

US20090194820A1 CMOS (COMPLEMENTARY METAL OXIDE SEMICONDUCTOR) DEVICES HAVING METAL GATE NFETS AND POLY-SILICON GATE PFETS 失效
标题翻译：具有金属栅极NFET和聚硅栅极的CMOS（补充金属氧化物半导体）器件
公开(公告)号：US20090194820A1
公开(公告)日：2009-08-06
申请号：US12026793
申请日：2008-02-06
申请人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
发明人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
IPC分类号： H01L27/00 , H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor structure fabrication method. The method includes providing a structure which includes (a) first and second semiconductor regions, (b) first and second gate dielectric regions on the first and second semiconductor regions, respectively, (c) a high-K dielectric region on the first gate dielectric region, K being greater than 4, (d) an electrically conductive layer on the high-K dielectric region, (e) a poly-silicon layer on the electrically conductive layer and the second gate dielectric region, and (f) a hard mask layer on the poly-silicon layer. The hard mask layer is patterned resulting in first and second hard mask regions. The poly-silicon layer is etched with the first and second hard mask regions as blocking masks resulting in first and second poly-silicon regions. The first and second poly-silicon regions are exposed to a surrounding ambient.
摘要翻译：半导体结构制造方法。该方法包括提供一种结构，该结构包括（a）分别在第一和第二半导体区域上的第一和第二半导体区域，（b）第一和第二栅极电介质区域，（c）第一栅极电介质上的高K电介质区域区域，K大于4，（d）高K电介质区域上的导电层，（e）导电层和第二栅极电介质区域上的多晶硅层，以及（f）硬掩模层在多晶硅层上。对硬掩模层进行图案化，形成第一和第二硬掩模区域。用第一和第二硬掩模区域蚀刻多晶硅层作为阻挡掩模，产生第一和第二多晶硅区域。第一和第二多晶硅区域暴露于周围环境。

97. 发明授权

US07538339B2 Scalable strained FET device and method of fabricating the same 有权
标题翻译：可扩展应变FET器件及其制造方法
公开(公告)号：US07538339B2
公开(公告)日：2009-05-26
申请号：US11615153
申请日：2006-12-22
申请人： Brian J. Greene , Sameer H. Jain , William K. Henson
发明人： Brian J. Greene , Sameer H. Jain , William K. Henson
IPC分类号： H01L29/94
CPC分类号： H01L29/7843 , H01L21/31641 , H01L21/31645 , H01L21/3185 , H01L21/823807 , H01L21/823828
摘要： An integrated circuit including pairs of strained complementary CMOS field-effect devices consisting of n-FET and p-FET transistors on a substrate. The n-FET is provided with a compressive dielectric stressor, while the p-FET is provided with a tensile stressed dielectric. Each dielectric stressor includes a discrete horizontal segment on a surface overlying and contacting the gate of the respective FET. The stress enhancement is insensitive to PC pitch, and by reducing the height of the polysilicon stack, the scalability which is achieved contributes to a performance improvement. The n-FET leverages higher stress values that are obtainable in the compressive liners are greater than 3 GPa compared to less than 1.5 GPa for tensile liners.
摘要翻译：一种集成电路，包括在衬底上由n-FET和p-FET晶体管组成的应变互补CMOS场效应器件对。 n-FET设置有压缩介电应力源，而p-FET设置有拉伸应力电介质。每个介电应力器包括覆盖并接触相应FET的栅极的表面上的离散水平段。应力增强对PC间距不敏感，并且通过降低多晶硅堆叠的高度，实现的可扩展性有助于性能改进。 n-FET利用在压缩衬里中可获得的较高应力值大于3GPa，而拉伸衬垫的应力值小于1.5GPa。

98. 发明申请

US20090090977A1 RESISTOR AND FET FORMED FROM THE METAL PORTION OF A MOSFET METAL GATE STACK 有权
标题翻译：从MOSFET金属栅极堆叠的金属部分形成的电阻和场效应晶体管
公开(公告)号：US20090090977A1
公开(公告)日：2009-04-09
申请号：US11869271
申请日：2007-10-09
申请人： Gregory G. Freeman , William K. Henson
发明人： Gregory G. Freeman , William K. Henson
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L27/0629 , H01L21/28088 , H01L28/20 , H01L29/4966 , H01L29/6659 , H01L29/7833
摘要： An integrated semiconductor device includes a resistor and an FET device formed from a stack of layers. The stack of layers includes a dielectric layer formed on a substrate; a metal conductor layer having lower electrical resistance formed on the dielectric layer; and a polysilicon layer formed on the metal conductor layer. A resistor stack is formed by patterning a portion of the original stack of layers into a resistor. An FET stack is formed from another portion of the original stack of layers. The FET stack is doped to form a gate electrode and the resistor stack is doped aside from the resistor portion thereof. Then terminals are formed at distal ends of the resistor in a doped portion of the polysilicon layer. Alternatively, the polysilicon layer is etched away from the resistor stack followed by forming terminals at distal ends of the metal conductor in the resistor stack.
摘要翻译：集成半导体器件包括由一叠层形成的电阻器和FET器件。层叠层包括在基板上形成的电介质层; 在电介质层上形成具有较低电阻的金属导体层; 以及形成在金属导体层上的多晶硅层。通过将原始堆叠层的一部分图案化成电阻器形成电阻器堆叠。 FET堆叠由原始层叠层的另一部分形成。掺杂FET堆叠以形成栅电极，并且电阻器堆叠从其电阻器部分被掺杂。然后，端子形成在多晶硅层的掺杂部分中的电阻器的远端处。或者，将多晶硅层从电阻器堆叠中蚀刻掉，然后在电阻器堆叠中的金属导体的远端形成端子。

99. 发明申请

US20080150033A1 SCALABLE STRAINED FET DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：可扩展应变FET器件及其制造方法
公开(公告)号：US20080150033A1
公开(公告)日：2008-06-26
申请号：US11615153
申请日：2006-12-22
申请人： Brian J. Greene , Sameer H. Jain , William K. Henson
发明人： Brian J. Greene , Sameer H. Jain , William K. Henson
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/7843 , H01L21/31641 , H01L21/31645 , H01L21/3185 , H01L21/823807 , H01L21/823828
摘要： A CMOS FET device having an enhanced performance is described by taking advantage of known dual-stress-liner effects and by making use of compressive nitride in an appropriate geometric configuration to induce compressive stress in the n-FET channel, and a tensile stress in the p-FET. The stress enhancement is designed to be insensitive to PC pitch, and to increase by reducing the height of the polysilicon stack, such that scalability contributes to the stated performance improvement. The n-FET leverages higher stress values that are obtainable in the compressive liners to be greater than 3 GPa, compared to less than 1.5 GPa for tensile liners.
摘要翻译：通过利用已知的双重应力衬垫效应并且通过利用适当几何构型的压缩氮化物来诱导n-FET通道中的压应力来描述具有增强性能的CMOS FET器件，并且在 p-FET。应力增强被设计为对PC间距不敏感，并且通过降低多晶硅堆叠的高度来增加，使得可扩展性有助于所述的性能改进。 n-FET利用在压缩衬里中可获得的较高应力值大于3GPa，而拉伸衬垫的应力值小于1.5GPa。

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