专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US5984312A Sealing device 失效
标题翻译：密封装置
公开(公告)号：US5984312A
公开(公告)日：1999-11-16
申请号：US931402
申请日：1997-09-15
申请人： Armin Hintenlang , Klaus Schafer , Reinhold Kraus , Kurt Ewald , Andreas Jaekel , Rolf Weis , Erwin Schafer , Bernd Stichler
发明人： Armin Hintenlang , Klaus Schafer , Reinhold Kraus , Kurt Ewald , Andreas Jaekel , Rolf Weis , Erwin Schafer , Bernd Stichler
IPC分类号： F16J15/34 , F16J15/36 , F16J15/38
CPC分类号： F16J15/348 , F16J15/36
摘要： A sealing device comprises a slide ring and a counterring having sealing surfaces, the slide ring and counterring contacting one another under axial prestressing in a sealing manner and capable of rotating relative to one another, the counterring and a substantially L-shaped engaging ring being interconnected, the engaging ring being affixed to a shaft to be sealed, and the counterring and the engaging ring being sealed relatively to each other by a sealing ring. The counterring contacts a radial segment of the engaging ring and surrounds an axial segment with radial clearance, and the sealing ring is sealingly arranged, under elastic prestressing, in the gap formed by the clearance. The counterring has an inner peripheral surface which forms an angle .alpha. of about 0.5.degree. to about 60.degree. with an axis of rotation, and the radial clearance in which the sealing ring is arranged is greater on the side facing the radial segment of the engaging ring than on the side facing the slide ring.
摘要翻译：密封装置包括滑环和具有密封表面的反转器，滑动环和反向旋转体在轴向预应力下以密封方式彼此接触并且能够相对于彼此旋转，所述反转环和基本上L形的接合环互连所述接合环被固定在要被密封的轴上，并且所述接合环和所述接合环通过密封环相对彼此密封。反向器接触接合环的径向段并围绕具有径向间隙的轴向段，并且密封环在弹性预应力下密封地布置在由间隙形成的间隙中。反转环具有内圆周表面，其与旋转轴线形成约0.5°至约60°的角度α，并且在该接合环的径向部分的面向上设置密封环的径向间隙较大而不是面对滑环的一侧。

92. 发明授权

US09859274B2 Integrated circuit with at least two switches 有权
公开(公告)号：US09859274B2
公开(公告)日：2018-01-02
申请号：US13546555
申请日：2012-07-11
申请人： Rolf Weis
发明人： Rolf Weis
IPC分类号： H01L27/088 , H03K17/10
CPC分类号： H01L27/0886 , H03K17/102
摘要： A circuit includes first and second semiconductor switches each having a load path and control terminal and their load paths connected in series. At least one of the first and second switches includes a first semiconductor device having a load path and a control terminal, the control terminal coupled to the control terminal of the switch. A plurality of second semiconductor devices each have a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device.

93. 发明授权

US08970262B2 Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices 有权
标题翻译：具有第一半导体器件和多个第二半导体器件的半导体器件布置
公开(公告)号：US08970262B2
公开(公告)日：2015-03-03
申请号：US13978373
申请日：2012-01-09
申请人： Rolf Weis , Franz Hirler , Martin Feldtkeller , Gerald Deboy , Matthias Stecher , Armin Willmeroth
发明人： Rolf Weis , Franz Hirler , Martin Feldtkeller , Gerald Deboy , Matthias Stecher , Armin Willmeroth
IPC分类号： H03B1/00 , H03K3/00 , H01L27/088 , H03K17/06 , H01L21/8234 , H01L29/78 , H01L29/423 , H01L27/098 , H01L29/06
CPC分类号： H01L27/0207 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L27/0623 , H01L27/0629 , H01L27/0727 , H01L27/088 , H01L27/0883 , H01L27/0886 , H01L27/098 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/4236 , H01L29/4238 , H01L29/78 , H01L29/7817 , H01L29/7824 , H01L29/7825 , H01L29/7835 , H01L29/7838 , H03K17/06
摘要： Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.
摘要翻译：公开了一种包括具有负载路径的第一半导体器件和多个第二晶体管的半导体器件布置，每个第二晶体管具有在第一和第二负载端子与控制端子之间的负载路径。第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接，每个第二晶体管的控制端连接到其它第二晶体管之一的负载端，第二晶体管中的一个晶体管的控制端子连接到第一半导体器件的负载端子之一。

94. 发明授权

US08866253B2 Semiconductor arrangement with active drift zone 有权
标题翻译：具有主动漂移区的半导体装置
公开(公告)号：US08866253B2
公开(公告)日：2014-10-21
申请号：US13362038
申请日：2012-01-31
申请人： Rolf Weis , Gerald Deboy , Michael Treu , Armin Willmeroth , Hans Weber
发明人： Rolf Weis , Gerald Deboy , Michael Treu , Armin Willmeroth , Hans Weber
IPC分类号： H01L27/00
CPC分类号： H01L27/0207 , H01L21/84 , H01L21/845 , H01L27/06 , H01L27/0629 , H01L27/088 , H01L27/0886 , H01L27/1211 , H01L29/4236 , H01L29/78 , H03K17/063 , H03K17/102
摘要： A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.
摘要翻译：半导体器件布置包括具有负载路径的第一半导体器件和多个第二半导体器件，每个第二半导体器件具有在第一和第二负载端子与控制端子之间的负载路径。第二半导体器件的负载路径串联连接并与第一半导体器件的负载路径串联连接。每个第二半导体器件的控制端子连接到其它第二半导体器件之一的负载端子，并且其中一个第二半导体器件的控制端子连接到第一半导体器件的负载端子之一。每个第二半导体器件具有至少一个器件特性。第二半导体器件中的至少一个的至少一个器件特征与第二半导体器件中的其它器件的相应器件特性不同。

95. 发明申请

US20140062544A1 Semiconductor Device Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices 有权
标题翻译：具有第一半导体器件和多个第二半导体器件的半导体器件布置
公开(公告)号：US20140062544A1
公开(公告)日：2014-03-06
申请号：US13978373
申请日：2012-01-09
申请人： Rolf Weis , Franz Hirler , Martin Feldtkeller , Gerald Deboy , Matthias Stecher , Armin Willmeroth
发明人： Rolf Weis , Franz Hirler , Martin Feldtkeller , Gerald Deboy , Matthias Stecher , Armin Willmeroth
IPC分类号： H01L27/088 , H03K17/06
CPC分类号： H01L27/0207 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L27/0623 , H01L27/0629 , H01L27/0727 , H01L27/088 , H01L27/0883 , H01L27/0886 , H01L27/098 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/4236 , H01L29/4238 , H01L29/78 , H01L29/7817 , H01L29/7824 , H01L29/7825 , H01L29/7835 , H01L29/7838 , H03K17/06
摘要： Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.
摘要翻译：公开了一种包括具有负载路径的第一半导体器件和多个第二晶体管的半导体器件布置，每个第二晶体管具有在第一和第二负载端子与控制端子之间的负载路径。第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接，每个第二晶体管的控制端连接到其它第二晶体管之一的负载端，第二晶体管中的一个晶体管的控制端子连接到第一半导体器件的负载端子之一。

96. 发明申请

US20130193512A1 Semiconductor Arrangement with Active Drift Zone 失效
公开(公告)号：US20130193512A1
公开(公告)日：2013-08-01
申请号：US13362033
申请日：2012-01-31
申请人： Rolf Weis
发明人： Rolf Weis
IPC分类号： H01L27/088 , H01L27/04
CPC分类号： H01L27/0207 , H01L21/84 , H01L27/0629 , H01L27/088 , H01L27/0886 , H01L27/105 , H01L27/1211 , H01L29/0619 , H01L29/0692 , H01L29/404
摘要： A semiconductor device arrangement includes a semiconductor layer and at least one series circuit with a first semiconductor device and a plurality of n second semiconductor devices, with n>1. The first semiconductor device has a load path and active device regions integrated in the semiconductor layer. Each second semiconductor device has active device regions integrated in the semiconductor layer and a load path between a first and second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each second semiconductor device has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. The arrangement further includes an edge termination structure.

97. 发明申请

US20120175635A1 Semiconductor Device Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices 有权
标题翻译：具有第一半导体器件和多个第二半导体器件的半导体器件布置
公开(公告)号：US20120175635A1
公开(公告)日：2012-07-12
申请号：US13275151
申请日：2011-10-17
申请人： Rolf Weis , Franz Hirler , Matthias Stecher , Armin Willmeroth , Gerald Deboy , Martin Feldtkeller
发明人： Rolf Weis , Franz Hirler , Matthias Stecher , Armin Willmeroth , Gerald Deboy , Martin Feldtkeller
IPC分类号： H01L27/06 , H01L29/778 , H01L29/788 , H01L29/20 , H01L29/161 , H01L27/088 , H01L27/098
CPC分类号： H01L27/0207 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L27/0623 , H01L27/0629 , H01L27/0727 , H01L27/088 , H01L27/0883 , H01L27/0886 , H01L27/098 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/4236 , H01L29/4238 , H01L29/78 , H01L29/7817 , H01L29/7824 , H01L29/7825 , H01L29/7835 , H01L29/7838 , H03K17/06
摘要： A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.
摘要翻译：半导体器件布置包括具有负载路径的第一半导体器件和多个第二晶体管，每个具有第一和第二负载端子与控制端子之间的负载路径。第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接。每个第二晶体管的控制端连接到其它第二晶体管的负载端子。第二晶体管中的一个具有其控制端子连接到第一半导体器件的负载端子之一。

98. 发明授权

US07994536B2 Integrated circuit including U-shaped access device 有权
标题翻译：集成电路包括U型接入装置
公开(公告)号：US07994536B2
公开(公告)日：2011-08-09
申请号：US12033533
申请日：2008-02-19
申请人： Rolf Weis , Thomas Happ
发明人： Rolf Weis , Thomas Happ
IPC分类号： H01L29/00 , H01L21/00 , G11C19/00
CPC分类号： H01L27/24
摘要： An integrated circuit includes a U-shaped access device and a first line coupled to a first side of the access device. The integrated circuit includes a contact coupled to a second side of the access device and self-aligned dielectric material isolating the first line from the contact.
摘要翻译：集成电路包括U形接入设备和耦合到接入设备的第一侧的第一线路。集成电路包括耦合到存取装置的第二侧的触点和将第一线与触点隔离的自对准电介质材料。

99. 发明申请

US20090315090A1 Isolation Trenches with Conductive Plates 有权
标题翻译：带导电板的隔离沟
公开(公告)号：US20090315090A1
公开(公告)日：2009-12-24
申请号：US12144482
申请日：2008-06-23
申请人： Rolf Weis , Thomas D. Happ
发明人： Rolf Weis , Thomas D. Happ
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L21/76224 , H01L27/2409 , H01L27/2445 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： Methods of forming isolation trenches, semiconductor devices, structures thereof, and methods of operating memory arrays are disclosed. In one embodiment, an isolation trench includes a recess disposed in a workpiece. A conductive material is disposed in a lower portion of the channel. An insulating material is disposed in an upper portion of the recess over the conductive material.
摘要翻译：公开了形成隔离沟槽的方法，半导体器件，其结构以及操作存储器阵列的方法。在一个实施例中，隔离沟槽包括设置在工件中的凹部。导电材料设置在通道的下部。绝缘材料设置在导电材料上的凹部的上部。

100. 发明申请

US20090218690A1 Reduced-Stress Through-Chip Feature and Method of Making the Same 有权
标题翻译：降低应力芯片的特点及其制作方法
公开(公告)号：US20090218690A1
公开(公告)日：2009-09-03
申请号：US12039232
申请日：2008-02-28
申请人： Harry Hedler , Roland Irsigler , Rolf Weis , Detlef Weber
发明人： Harry Hedler , Roland Irsigler , Rolf Weis , Detlef Weber
IPC分类号： H01L23/52 , H05K1/00 , H01L21/4763
CPC分类号： H01L23/564 , H01L23/481 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A feature is inscribed in a major surface of a microelectronic workpiece having a material property expressed as a reference coefficient value. The feature includes a first material having a first coefficient value for the material property and a second material having a second coefficient value for the material property. The first coefficient value is different from the reference coefficient value different from the first coefficient value and the second coefficient value is different from the first coefficient value. The first and second materials behave as an aggregate having an aggregate coefficient value for the material property between the first coefficient value and the reference coefficient value.
摘要翻译：特征是刻在具有表示为参考系数值的材料性质的微电子工件的主表面上。该特征包括具有用于材料性质的第一系数值的第一材料和具有用于材料性质的第二系数值的第二材料。第一系数值不同于与第一系数值不同的参考系数值，第二系数值与第一系数值不同。第一和第二材料表现为具有第一系数值和参考系数值之间的材料特性的聚集系数值的聚集体。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式