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1. 发明申请

US20090218690A1 Reduced-Stress Through-Chip Feature and Method of Making the Same 有权
标题翻译：降低应力芯片的特点及其制作方法
公开(公告)号：US20090218690A1
公开(公告)日：2009-09-03
申请号：US12039232
申请日：2008-02-28
申请人： Harry Hedler , Roland Irsigler , Rolf Weis , Detlef Weber
发明人： Harry Hedler , Roland Irsigler , Rolf Weis , Detlef Weber
IPC分类号： H01L23/52 , H05K1/00 , H01L21/4763
CPC分类号： H01L23/564 , H01L23/481 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A feature is inscribed in a major surface of a microelectronic workpiece having a material property expressed as a reference coefficient value. The feature includes a first material having a first coefficient value for the material property and a second material having a second coefficient value for the material property. The first coefficient value is different from the reference coefficient value different from the first coefficient value and the second coefficient value is different from the first coefficient value. The first and second materials behave as an aggregate having an aggregate coefficient value for the material property between the first coefficient value and the reference coefficient value.
摘要翻译：特征是刻在具有表示为参考系数值的材料性质的微电子工件的主表面上。该特征包括具有用于材料性质的第一系数值的第一材料和具有用于材料性质的第二系数值的第二材料。第一系数值不同于与第一系数值不同的参考系数值，第二系数值与第一系数值不同。第一和第二材料表现为具有第一系数值和参考系数值之间的材料特性的聚集系数值的聚集体。

2. 发明授权

US08106511B2 Reduced-stress through-chip feature and method of making the same 有权
标题翻译：降低应力芯片的特点及制作方法
公开(公告)号：US08106511B2
公开(公告)日：2012-01-31
申请号：US12039232
申请日：2008-02-28
申请人： Harry Hedler , Roland Irsigler , Rolf Weis , Detlef Weber
发明人： Harry Hedler , Roland Irsigler , Rolf Weis , Detlef Weber
IPC分类号： H01L21/44
CPC分类号： H01L23/564 , H01L23/481 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A feature is inscribed in a major surface of a microelectronic workpiece having a material property expressed as a reference coefficient value. The feature includes a first material having a first coefficient value for the material property and a second material having a second coefficient value for the material property. The first coefficient value is different from the reference coefficient value different from the first coefficient value and the second coefficient value is different from the first coefficient value. The first and second materials behave as an aggregate having an aggregate coefficient value for the material property between the first coefficient value and the reference coefficient value.
摘要翻译：特征是刻在具有表示为参考系数值的材料特性的微电子工件的主表面上。该特征包括具有用于材料性质的第一系数值的第一材料和具有用于材料性质的第二系数值的第二材料。第一系数值不同于与第一系数值不同的参考系数值，第二系数值与第一系数值不同。第一和第二材料表现为具有第一系数值和参考系数值之间的材料特性的聚集系数值的聚集体。

3. 发明授权

US08598716B2 Semiconductor apparatus having stacked semiconductor components 失效
标题翻译：半导体装置具有堆叠的半导体元件
公开(公告)号：US08598716B2
公开(公告)日：2013-12-03
申请号：US11210723
申请日：2005-08-24
申请人： Harry Hedler , Roland Irsigler , Thorsten Meyer
发明人： Harry Hedler , Roland Irsigler , Thorsten Meyer
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06586 , H01L2924/01078 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012
摘要： The present invention provides an apparatus having stacked semiconductor components. Two semiconductor components (21, 26) are arranged such that their contact regions (28, 22) are opposite one another. A contact-connection device (29) forms a short electrical connection between the two contact regions (28, 22). The contact regions (28, 22) are connected to external contact regions (36) of the apparatus via a rewiring (23).
摘要翻译：本发明提供一种具有层叠半导体元件的装置。两个半导体部件（21,26）被布置成使得它们的接触区域（28,22）彼此相对。接触连接装置（29）在两个接触区域（28,22）之间形成短路电连接。接触区域（28,22）经由重新布线（23）连接到设备的外部接触区域（36）。

4. 发明申请

US20100065949A1 Stacked Semiconductor Chips with Through Substrate Vias 审中-公开
标题翻译：堆叠的半导体芯片通过基板通孔
公开(公告)号：US20100065949A1
公开(公告)日：2010-03-18
申请号：US12212498
申请日：2008-09-17
申请人： Andreas Thies , Harry Hedler , Roland Irsigler
发明人： Andreas Thies , Harry Hedler , Roland Irsigler
IPC分类号： H01L23/538 , H01L21/60
CPC分类号： H01L24/16 , H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/12 , H01L24/17 , H01L24/81 , H01L24/83 , H01L24/90 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/13099 , H01L2224/16145 , H01L2224/81136 , H01L2224/81801 , H01L2224/83194 , H01L2224/838 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/01007 , H01L2224/05552
摘要： Structures and methods of forming stacked chips are disclosed. In one embodiment, a first chip is disposed over a second chip, a top surface of the first and the second chip includes active circuitry. A first through substrate via is disposed within the first chip, the first through substrate via includes a protruding tip projecting below a bottom surface of the first chip, the bottom surface being opposite the top surface. A second through substrate via is disposed on the second chip, the second through substrate via including an opening, wherein the first protruding tip of the first chip is disposed within the opening of the second chip.
摘要翻译：公开了形成堆叠芯片的结构和方法。在一个实施例中，第一芯片设置在第二芯片上，第一芯片和第二芯片的顶表面包括有源电路。第一穿通基板通孔设置在第一芯片内，第一通孔基板通孔包括在第一芯片的底表面下方突出的突出尖端，底表面与顶表面相对。第二穿通基板通孔设置在第二芯片上，第二通孔基板通孔包括开口，其中第一芯片的第一突出末端设置在第二芯片的开口内。

5. 发明授权

US07247948B2 Semiconductor device and method for fabricating the semiconductor device 有权
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US07247948B2
公开(公告)日：2007-07-24
申请号：US10836143
申请日：2004-04-30
申请人： Harry Hedler , Roland Irsigler , Thorsten Meyer
发明人： Harry Hedler , Roland Irsigler , Thorsten Meyer
IPC分类号： H01L21/82 , H01L23/48
CPC分类号： H01L25/0657 , H01L23/481 , H01L24/48 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48471 , H01L2224/73265 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/00015 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/85399 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012 , H01L2224/0401 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has a semiconductor substrate, at least a first and second rewiring device on a first surface of the semiconductor substrate for the provision of an electrical contact-connection of the semiconductor substrate, and a tapering, continuous opening from a first surface to a second, opposite surface of the semiconductor substrate. At least a third and fourth rewiring device is disposed on the second surface of the semiconductor substrate and a patterned metallization on the side areas of the opening for the separate contact-connection of the first and at least the second rewiring device.
摘要翻译：半导体器件具有半导体衬底，至少第一和第二重新布线装置在半导体衬底的第一表面上，用于提供半导体衬底的电接触连接，以及从第一表面到第二表面的渐缩连续的开口第二，半导体衬底的相对表面。至少第三和第四重新布线装置设置在半导体衬底的第二表面上，并且在开口的侧面区域上形成图案化金属化，用于第一和第二重新布线装置的单独接触连接。

6. 发明申请

US20070032059A1 Method of manufacturing a semiconductor structure having a wafer through-contact and a corresponding semiconductor structure 审中-公开
标题翻译：制造具有晶片通孔接触和相应的半导体结构的半导体结构的方法
公开(公告)号：US20070032059A1
公开(公告)日：2007-02-08
申请号：US11195462
申请日：2005-08-02
申请人： Harry Hedler , Roland Irsigler
发明人： Harry Hedler , Roland Irsigler
IPC分类号： H01L21/44
CPC分类号： H01L21/76898
摘要： A method of manufacturing a semiconductor structure having a wafer through-contact and a corresponding semiconductor structure This invention provides a method of manufacturing a semiconductor structure having a wafer through-contact and a corresponding semiconductor structure. The method comprises the steps of: providing a semiconductor wafer (1) having a bulk region (1a) and an active region (1b); forming a plurality of contact trenches (5a-5f) in said semiconductor wafer (1) which extend from an upper surface (O) of said active region (1b) into said bulk region (1a); forming a first dielectric isolation layer (8) on the sidewalls and the bottoms of said contact trenches (5a-5f); providing a first conductive filling (10) in said plurality of contact trenches (5a-5f); forming an aligned via (V) in said semiconductor wafer (1) which extends from a backside (B) of said bulk region (1a) into said plurality of contact trenches (5a-5f) and exposes the conductive filling (10) of said plurality of contact trenches (5a-5f); providing a second dielectric isolation layer (15) on the sidewall of said via (V); and providing a second conductive filling (20) in said via (V) which contacts the exposed conductive filling (10) of said plurality of contact trenches (5a-5f) thus forming said wafer through-contact.
摘要翻译：一种制造具有晶片通孔接触和相应的半导体结构的半导体结构的方法本发明提供一种制造具有晶片通孔接触和相应的半导体结构的半导体结构的方法。该方法包括以下步骤：提供具有体区（1a）和有源区（1b）的半导体晶片（1）; 在所述半导体晶片（1）中形成从所述有源区（1b）的上表面（O）延伸到所述体区（1a）中的多个接触沟槽（5a-5f）; 在所述接触沟槽（5a-5f）的侧壁和底部上形成第一介电隔离层（8）; 在所述多个接触沟槽（5a-5f）中提供第一导电填料（10）; 在所述半导体晶片（1）中形成对准的通孔（V），所述半导体晶片从所述主体区域（1a）的背面（B）延伸到所述多个接触沟槽（5a-5f）中并且暴露所述导电填料）所述多个接触沟槽（5a-5f）中; 在所述通孔（V）的侧壁上提供第二介电隔离层（15）; 以及在所述通孔（V）中提供与所述多个接触沟槽（5a-5f）的暴露的导电填料（10）接触从而形成所述晶片通过接触的第二导电填料（20）。

7. 发明申请

US20060091561A1 Electronic component comprising external surface contacts and a method for producing the same 审中-公开
标题翻译：包括外表面接触的电子部件及其制造方法
公开(公告)号：US20060091561A1
公开(公告)日：2006-05-04
申请号：US10515613
申请日：2003-05-23
申请人： Jochen Dangelmaier , Harry Hedler , Roland Irsigler , Stefan Paulus
发明人： Jochen Dangelmaier , Harry Hedler , Roland Irsigler , Stefan Paulus
IPC分类号： H01L23/48 , H01L21/48
CPC分类号： H01L21/568 , B29C2043/5825 , H01L21/4846 , H01L23/3121 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2224/16503 , H01L2224/32225 , H01L2224/45015 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2224/81001 , H01L2224/8181 , H01L2224/83385 , H01L2224/85424 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01052 , H01L2924/01058 , H01L2924/01068 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01327 , H01L2924/07802 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/01026 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/207 , H01L2224/05599
摘要： The invention relates to an electronic device and a method for producing it having external area contacts and having a rewiring structure and also having a semiconductor chip, which has contact areas, the external area contacts being electrically connected to the contact areas at least by means of the rewiring structure, and the external area contacts and/or the rewiring structure having chemically or galvanically selectively deposited metal.
摘要翻译：本发明涉及一种电子器件及其制造方法，该电子器件及其制造方法具有外部区域接触并且具有重新布线结构，并且还具有具有接触区域的半导体芯片，所述外部区域触点至少借助于重新布线结构以及具有化学或电化学选择性沉积金属的外部区域接触和/或重新布线结构。

8. 发明申请

US20050250304A1 Method for fabricating connection regions of an integrated circuit, and integrated circuit having connection regions 有权
标题翻译：用于制造集成电路的连接区域的方法，以及具有连接区域的集成电路
公开(公告)号：US20050250304A1
公开(公告)日：2005-11-10
申请号：US10642092
申请日：2003-08-15
申请人： Harry Hedler , Roland Irsigler , Thorsten Meyer , Barbara Vasquez
发明人： Harry Hedler , Roland Irsigler , Thorsten Meyer , Barbara Vasquez
IPC分类号： H01L21/60 , H01L23/485 , H01L21/44
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05026 , H01L2224/05568 , H01L2224/05569 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/05541 , H01L2224/05005 , H01L2224/05644 , H01L2924/00014 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166
摘要： A method for fabricating an integrated circuit connection region includes application of a dielectric to an integrated circuit with a connection region, application of a corrodible metalization layer to the dielectric, application of a protection device to the metalization layer, and removal of the protection device in a region around the connection region.
摘要翻译：一种用于制造集成电路连接区域的方法包括将电介质施加到具有连接区域的集成电路，向电介质施加可腐蚀金属化层，向金属化层施加保护装置，以及将保护装置移除到连接区域周围的区域。

9. 发明授权

US06861291B2 Method producing a contact connection between a semiconductor chip and a substrate and the contact connection 有权
标题翻译：在半导体芯片和基板之间产生接触连接的方法和接触连接
公开(公告)号：US06861291B2
公开(公告)日：2005-03-01
申请号：US10135273
申请日：2002-04-30
申请人： Harry Hedler , Barbara Vasquez , Roland Irsigler
发明人： Harry Hedler , Barbara Vasquez , Roland Irsigler
IPC分类号： H01L21/60 , H01L23/485 , H01L23/498 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L24/29 , H01L23/49811 , H01L24/12 , H01L24/83 , H01L2224/13099 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29324 , H01L2224/29339 , H01L2224/29344 , H01L2224/29347 , H01L2224/29355 , H01L2224/29369 , H01L2224/8319 , H01L2224/838 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/07811 , H01L2924/00 , H01L2924/00014 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299
摘要： A contact connection between a semiconductor chip and a substrate has a conductive adhesive extending between each contact of the chip and the substrate. The conductive adhesive includes a matrix component, a filler component, a hardener component and at least one decomposable component so that after curing at a curing temperature T1, the adhesive can be decomposed either by applying thermal energy at a temperature T2>T1 or by radiation so that the two contact surfaces can be separated smoothly. After separation the purposes of replacing a defective semiconductor chip, a second chip can be mechanically connected by applying the adhesive and curing it.
摘要翻译：半导体芯片和基板之间的接触连接具有在芯片的每个接触件和基板之间延伸的导电粘合剂。导电粘合剂包括基质组分，填料组分，硬化剂组分和至少一种可分解组分，使得在固化温度T1固化后，粘合剂可以通过在温度T2> T1或辐射下施加热能来分解使得两个接触表面可以平滑地分离。分离后更换有缺陷的半导体芯片的目的，可以通过施加粘合剂并固化第二芯片来机械地连接第二芯片。

10. 发明授权

US08124521B2 Electrical through contact 有权
标题翻译：电气通过接触
公开(公告)号：US08124521B2
公开(公告)日：2012-02-28
申请号：US11745145
申请日：2007-05-07
申请人： Harry Hedler , Roland Irsigler , Volker Lehmann , Judith Lehmann, legal representative , Thorsten Meyer , Octavio Trovarelli
发明人： Harry Hedler , Roland Irsigler , Volker Lehmann , Thorsten Meyer , Octavio Trovarelli
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898 , H01L24/05 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/13025 , H01L2224/83894 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2224/05552 , H01L2924/00
摘要： A method of fabricating an electrical contact through a through hole in a substrate, wherein the through hole is at least in part filled with a liquid conductive material and the solidified liquid conductive material provides an electrical contact through the through hole.
摘要翻译：一种通过衬底中的通孔制造电接触的方法，其中所述通孔至少部分地填充有液体导电材料，并且所述固化的液体导电材料通过所述通孔提供电接触。

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