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91. 发明申请

US20080147964A1 USING VARIOUS FLASH MEMORY CELLS TO BUILD USB DATA FLASH CARDS WITH MULTIPLE PARTITIONS AND AUTORUN FUNCTION 审中-公开
标题翻译：使用各种闪存存储器来构建具有多个分区和自动功能的USB数据闪存卡
公开(公告)号：US20080147964A1
公开(公告)日：2008-06-19
申请号：US11867610
申请日：2007-10-04
申请人： David Q. Chow , Charles C. Lee , Frank I-Kang Yu , Abraham C. Ma , Ming-Shiang Shen
发明人： David Q. Chow , Charles C. Lee , Frank I-Kang Yu , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F21/34 , G06F3/0632 , G06F3/0644 , G06F3/0664 , G06F3/0679 , G06F21/32
摘要： An electronic data flash card includes a processor and at least one flash memory device. The flash memory is partitioned such that it includes a first partition that is formatted using a file system that supports an Autorun function (e.g., CD-ROM file system (CDFS) format, fixed-disk format or Universal Disk Format (UDF)), and a disk partition that is formatted using a typical controller-based flash device file system (e.g., 16-bit File Allocation Table (FAT16) file system, 32-bit FAT (FAT32) file system, or New Technology File System (NTFS)). The electronic data flash card is produced such that Autorun-enabled application automatically executes a predetermined application or action when the electronic data flash card is installed in a host system. In one embodiment, the Autorun application includes an advertisement displayed on the host system prior to allowing access to data stored in the disk partition.
摘要翻译：电子数据闪存卡包括处理器和至少一个闪存设备。闪存被分区，使得其包括使用支持自动运行功能的文件系统（例如，CD-ROM文件系统（CDFS）格式，固定磁盘格式或通用磁盘格式（UDF））格式化的第一分区，以及使用典型的基于控制器的闪存设备文件系统（例如，16位文件分配表（FAT16）文件系统，32位FAT（FAT32）文件系统或新技术文件系统（NTFS））格式化的磁盘分区，）。生成电子数据闪存卡，使得当电子数据闪存卡安装在主机系统中时，自动运行应用程序自动执行预定的应用或动作。在一个实施例中，自动运行应用程序在允许访问存储在磁盘分区中的数据之前包括在主机系统上显示的广告。

92. 发明申请

US20080071976A1 ELECTRONIC DATA FLASH CARD WITH VARIOUS FLASH MEMORY CELLS 审中-公开
公开(公告)号：US20080071976A1
公开(公告)日：2008-03-20
申请号：US11929825
申请日：2007-10-30
申请人： David Q. Chow , Frank I Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
发明人： David Q. Chow , Frank I Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/1416 , G06F21/32 , G06F21/78 , G06F2212/7202 , G06F2212/7208 , G06K9/00087 , G06K19/07 , G06K19/07354 , G07C9/00087
摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

93. 发明授权

US07934074B2 Flash module with plane-interleaved sequential writes to restricted-write flash chips 有权
标题翻译：闪存模块，具有平面交错顺序写入限制写入闪存芯片
公开(公告)号：US07934074B2
公开(公告)日：2011-04-26
申请号：US11871011
申请日：2007-10-11
申请人： Charles C. Lee , Frank Yu , Ming-Shiang Shen , Abraham C. Ma , David Q. Chow
发明人： Charles C. Lee , Frank Yu , Ming-Shiang Shen , Abraham C. Ma , David Q. Chow
IPC分类号： G06F12/06
CPC分类号： G06F12/0246 , G06F12/0607 , G06F2212/7201 , G06F2212/7208 , G11C11/5621 , G11C16/0408
摘要： A flash memory controller on a PCIE bus controls flash-memory modules on a flash bus. The flash-memory modules are plane-interleaved using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. A physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. A RAM physical page valid table tracks valid pages in the four planes, while a RAM mapping table stores the plane, block, and page addresses for logical sectors generated by the physical sequential address counter.
摘要翻译： PCIE总线上的闪存控制器控制闪存总线上的闪存模块。闪存模块使用从逻辑块索引的最低位提取的交错比特进行平面交织。这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。物理顺序地址计数器通过在中间物理块比特之前递增平面交织比特，然后将MSB重新定位到中间物理块比特之上来生成物理块号。这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。 RAM物理页有效表跟踪四个平面中的有效页面，而RAM映射表存储由物理顺序地址计数器生成的逻辑扇区的平面，块和页面地址。

94. 发明授权

US07707321B2 Chained DMA for low-power extended USB flash device without polling 失效
标题翻译：用于低功耗扩展USB闪存设备的链接DMA，无轮询
公开(公告)号：US07707321B2
公开(公告)日：2010-04-27
申请号：US11928124
申请日：2007-10-30
申请人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
发明人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
IPC分类号： G06F3/00 , G06F13/38
CPC分类号： G06F13/28 , Y02D10/14
摘要： An extended Universal-Serial Bus (EUSB) host has reduced loading by using radio frequency (RF) transceivers or direct wiring traces rather than a pair of legacy USB cables. The reduced loading opens the eye pattern. The EUSB device transfers internal data using chained Direct-Memory Access (DMA). Registers in a DMA controller point to a vector table that has vector entries, each pointing to a destination and a source. The source is a memory table for a memory group. The memory table has entries for several memory segments. Each memory-table entry has a pointer to a memory segment and a byte count for the segment. Once all bytes in the segment are transferred, a flag in the entry indicates when another memory segment follows within the memory group. When an END flag is read, then vector table is advanced to the next vector entry, and another memory group of memory segments processed.
摘要翻译：扩展的通用串行总线（EUSB）主机通过使用射频（RF）收发器或直接布线轨迹而不是一对传统的USB电缆减少了负载。减少负荷打开眼睛图案。 EUSB设备使用链接的直接内存访问（DMA）传输内部数据。 DMA控制器中的寄存器指向具有向量条目的向量表，每个向量表指向一个目的地和一个源。源是内存组的内存表。内存表有几个内存段的条目。每个存储表条目具有指向存储器段的指针和段的字节计数。一旦片段中的所有字节都被传送，该条目中的标志表示在存储器组中跟随其他内存段的时间。读取END标志时，向量表前进到下一个向量条目，并处理另一个内存段的内存组。

95. 发明申请

US20100082893A1 Flash Memory Controller For Electronic Data Flash Card 审中-公开
标题翻译：闪存控制器用于电子数据闪存卡
公开(公告)号：US20100082893A1
公开(公告)日：2010-04-01
申请号：US12631761
申请日：2009-12-04
申请人： Abraham C. Ma , Charles C. Lee , I-Kang Yu , Edward W. Lee , Ming-Shiang Shen
发明人： Abraham C. Ma , Charles C. Lee , I-Kang Yu , Edward W. Lee , Ming-Shiang Shen
IPC分类号： G06F12/00 , G06F12/02 , G06F12/10
CPC分类号： G06F12/0246 , G06F12/1416 , G06F21/32 , G06F21/78 , G06F21/79 , G06K9/00087 , G06K19/07 , G06K19/07354 , G07C9/00087
摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.
摘要翻译：电子数据闪存卡可由主机访问，并且包括连接到存储数据文件的闪存设备的处理单元，以及被激活以便与主计算机建立通信的输入 - 输出接口电路。在一个实施例中，电子数据闪存卡使用USB输入/输出接口电路与主计算机进行通信。闪速存储器控制器包括用于将由主计算机发送的逻辑地址转换成与闪存器件的扇区相关联的物理地址的索引。该索引由参考来自各种查找表中的值和存储在闪存设备中的有效数据的仲裁逻辑控制。闪存控制器还包括先进先出单元（FIFO），用于在后台进程中回收闪速存储器件的过时扇区，使得它们可用于重新编程。

96. 发明申请

US20100082892A1 Flash Memory Controller For Electronic Data Flash Card 审中-公开
标题翻译：闪存控制器用于电子数据闪存卡
公开(公告)号：US20100082892A1
公开(公告)日：2010-04-01
申请号：US12631748
申请日：2009-12-04
申请人： Abraham C. Ma , Charles C. Lee , I-Kang Yu , Edward W. Lee , Ming-Shiang Shen
发明人： Abraham C. Ma , Charles C. Lee , I-Kang Yu , Edward W. Lee , Ming-Shiang Shen
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F12/1416 , G06F21/32 , G06F21/78 , G06F21/79 , G06K9/00087 , G06K19/07 , G06K19/07354 , G07C9/00087
摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input— output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.
摘要翻译：电子数据闪存卡可由主机访问，并且包括连接到存储数据文件的闪存设备的处理单元，以及被激活以便与主计算机建立通信的输入 - 输出接口电路。在一个实施例中，电子数据闪存卡使用USB输入/输出接口电路与主计算机进行通信。闪速存储器控制器包括用于将由主计算机发送的逻辑地址转换成与闪存器件的扇区相关联的物理地址的索引。该索引由参考来自各种查找表中的值和存储在闪存设备中的有效数据的仲裁逻辑控制。闪存控制器还包括先进先出单元（FIFO），用于在后台进程中回收闪速存储器件的过时扇区，使得它们可用于重新编程。

97. 发明申请

US20100030961A9 FLASH MEMORY CONTROLLER FOR ELECTRONIC DATA FLASH CARD 失效
标题翻译：电子数据闪存卡闪存控制器
公开(公告)号：US20100030961A9
公开(公告)日：2010-02-04
申请号：US11466759
申请日：2006-08-23
申请人： Abraham C. Ma , Charles C. Lee , I-Kang Yu , Edward W. Lee , Ming-Shiang Shen
发明人： Abraham C. Ma , Charles C. Lee , I-Kang Yu , Edward W. Lee , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/1416 , G06F21/32 , G06F21/78 , G06F21/79 , G06K9/00087 , G06K19/07 , G06K19/07354 , G07C9/00087
摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.
摘要翻译：电子数据闪存卡可由主机访问，并且包括连接到存储数据文件的闪存设备的处理单元，以及被激活以便与主计算机建立通信的输入 - 输出接口电路。在一个实施例中，电子数据闪存卡使用USB输入/输出接口电路与主计算机进行通信。闪速存储器控制器包括用于将由主计算机发送的逻辑地址转换成与闪存器件的扇区相关联的物理地址的索引。该索引由参考来自各种查找表中的值和存储在闪存设备中的有效数据的仲裁逻辑控制。闪存控制器还包括先进先出单元（FIFO），用于在后台进程中回收闪速存储器件的过时扇区，使得它们可用于重新编程。

98. 发明申请

US20080313388A1 ELECTRONIC DATA FLASH CARD WITH VARIOUS FLASH MEMORY CELLS 审中-公开
公开(公告)号：US20080313388A1
公开(公告)日：2008-12-18
申请号：US11929776
申请日：2007-10-30
申请人： David Q. Chow , Frank I. Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
发明人： David Q. Chow , Frank I. Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/1416 , G06F21/32 , G06F21/78 , G06F2212/7202 , G06F2212/7208 , G06K9/00087 , G06K19/07 , G06K19/07354 , G07C9/00087
摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

99. 发明申请

US20080250195A1 Multi-Operation Write Aggregator Using a Page Buffer and a Scratch Flash Block in Each of Multiple Channels of a Large Array of Flash Memory to Reduce Block Wear 失效
标题翻译：多操作写入聚合器使用大量Flash存储器的多个通道中的每一个中的页面缓冲区和划痕闪存块来减少块磨损
公开(公告)号：US20080250195A1
公开(公告)日：2008-10-09
申请号：US12139842
申请日：2008-06-16
申请人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
发明人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F21/32 , G06F21/78 , G06F2212/1036 , G06F2212/7202 , G06F2212/7208 , G06K19/07 , G06K19/07354
摘要： A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer is reached, the page buffer is written to a target physical block if full, or combined with old data fragments in an Aggregating Flash Block (AFB) when the logical-sector addresses (LSA's) match. Thus small fragments are aggregated using the AFB, reducing erases and wear of flash blocks. The page buffer is copied to the AFB when a STOP command occurs. Each channel has one or more AFB's, which are tracked by an AFB tracking table.
摘要翻译：闪存系统具有可以并行访问的多个闪存芯片的通道。主机数据被多通道控制器处理器分配给一个通道，并且累积在多通道页缓冲器中。当到达页面缓冲区中的页面边界时，如果逻辑扇区地址（LSA）匹配，则页缓冲区将被写入目标物理块（如果已满）或与聚合闪存块（AFB）中的旧数据片段组合。因此，使用AFB聚集小片段，减少闪存块的擦除和磨损。发生STOP命令时，页面缓冲区被复制到AFB。每个通道都有一个或多个AFB，它们由AFB跟踪表进行跟踪。

100. 发明申请

US20080235443A1 Intelligent Solid-State Non-Volatile Memory Device (NVMD) System With Multi-Level Caching of Multiple Channels 失效
标题翻译：具有多通道多级缓存的智能固态非易失性存储器件（NVMD）系统
公开(公告)号：US20080235443A1
公开(公告)日：2008-09-25
申请号：US12115128
申请日：2008-05-05
申请人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
发明人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F12/02
CPC分类号： G06F12/1416 , G06F3/0664 , G06F12/0851 , G06F12/0866 , G06F12/0897 , G06F21/32 , G06F21/78 , G06F21/79 , G06F2212/2022 , Y02D10/13
摘要： A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.
摘要翻译：闪存系统存储由逻辑块地址（LBA）寻址的非易失性存储器件（NVMD）中的数据块。 NVBA将对LBA进行重新配置以进行磨损均衡和坏块重定位。 NVMD在由NVMD控制器访问的通道中进行交织。 NVMD控制器具有缓存存储在该通道中的NVMD中的块的控制器高速缓存，而NVMD还包含高速缓存。多级缓存可以减少访问延迟。电源由NVMD控制器中的电源控制器以多级管理，为NVMD内的电源管理器设置电源策略。闪存系统中的多个NVMD控制器可以各自控制多个NVMD通道。具有NVMD的闪存系统可能包括用于安全性的指纹读取器。

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