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    • 10. 发明授权
    • SRAM cache and flash micro-controller with differential packet interface
    • 具有差分数据包接口的SRAM缓存和闪存微控制器
    • US07707354B2
    • 2010-04-27
    • US11876251
    • 2007-10-22
    • Charles C. LeeDavid Q. ChowAbraham C. MaFrank YuMing-Shiang Shen
    • Charles C. LeeDavid Q. ChowAbraham C. MaFrank YuMing-Shiang Shen
    • G06F12/00
    • G06F12/0866G06F2212/2022G06F2212/2515
    • A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The SRAM buffer also operates as a cache of flash data after booting is complete. Cache read and write hits use the SRAM cache rather than flash memory, while old cache lines and read misses access the flash memory. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory. The flash microcontroller uses a differential interface to the external host, with a differential transceiver and a differential serial interface. Frame, packet, and encoded clock processing is also performed by the serial interface.
    • 闪存微控制器具有静态随机存取存储器(SRAM)缓冲器,其存储从闪存读取的几个引导代码块。 引导完成后,SRAM缓冲区还可以作为闪存数据缓存。 缓存读取和写入命中使用SRAM缓存而不是闪存,而旧的缓存行和读取未命中访问闪存。 外部主机和微控制器均由缓冲在SRAM缓冲区中的引导代码引导。 引导加载器状态机读取闪存ID,并使用Flash存储器的时序参数对闪存参数寄存器进行编程。 闪存单片机使用与外部主机的差分接口,具有差分收发器和差分串行接口。 帧,分组和编码时钟处理也由串行接口执行。