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1. 发明授权

US07707354B2 SRAM cache and flash micro-controller with differential packet interface 失效
标题翻译：具有差分数据包接口的SRAM缓存和闪存微控制器
公开(公告)号：US07707354B2
公开(公告)日：2010-04-27
申请号：US11876251
申请日：2007-10-22
申请人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen
发明人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F2212/2022 , G06F2212/2515
摘要： A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The SRAM buffer also operates as a cache of flash data after booting is complete. Cache read and write hits use the SRAM cache rather than flash memory, while old cache lines and read misses access the flash memory. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory. The flash microcontroller uses a differential interface to the external host, with a differential transceiver and a differential serial interface. Frame, packet, and encoded clock processing is also performed by the serial interface.
摘要翻译：闪存微控制器具有静态随机存取存储器（SRAM）缓冲器，其存储从闪存读取的几个引导代码块。引导完成后，SRAM缓冲区还可以作为闪存数据缓存。缓存读取和写入命中使用SRAM缓存而不是闪存，而旧的缓存行和读取未命中访问闪存。外部主机和微控制器均由缓冲在SRAM缓冲区中的引导代码引导。引导加载器状态机读取闪存ID，并使用Flash存储器的时序参数对闪存参数寄存器进行编程。闪存单片机使用与外部主机的差分接口，具有差分收发器和差分串行接口。帧，分组和编码时钟处理也由串行接口执行。

2. 发明授权

US08108590B2 Multi-operation write aggregator using a page buffer and a scratch flash block in each of multiple channels of a large array of flash memory to reduce block wear 失效
标题翻译：多操作写入聚合器使用大量闪存存储器的多个通道中的每个通道中的页面缓冲区和划痕闪存块来减少块磨损
公开(公告)号：US08108590B2
公开(公告)日：2012-01-31
申请号：US12139842
申请日：2008-06-16
申请人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
发明人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F21/32 , G06F21/78 , G06F2212/1036 , G06F2212/7202 , G06F2212/7208 , G06K19/07 , G06K19/07354
摘要： A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer is reached, the page buffer is written to a target physical block if full, or combined with old data fragments in an Aggregating Flash Block (AFB) when the logical-sector addresses (LSA's) match. Thus small fragments are aggregated using the AFB, reducing erases and wear of flash blocks. The page buffer is copied to the AFB when a STOP command occurs. Each channel has one or more AFB's, which are tracked by an AFB tracking table.
摘要翻译：闪存系统具有可以并行访问的多个闪存芯片的通道。主机数据被多通道控制器处理器分配给一个通道，并且累积在多通道页缓冲器中。当到达页面缓冲区中的页面边界时，如果逻辑扇区地址（LSA）匹配，则页缓冲区将被写入目标物理块（如果已满）或与聚合闪存块（AFB）中的旧数据片段组合。因此，使用AFB聚集小片段，减少闪存块的擦除和磨损。发生STOP命令时，页面缓冲区被复制到AFB。每个通道都有一个或多个AFB，它们由AFB跟踪表进行跟踪。

3. 发明授权

US07657692B2 High-level bridge from PCIE to extended USB 失效
标题翻译：从PCIE到扩展USB的高级桥
公开(公告)号：US07657692B2
公开(公告)日：2010-02-02
申请号：US11926636
申请日：2007-10-29
申请人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
发明人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
IPC分类号： G06F13/00
CPC分类号： G06F13/28 , G06F12/1416 , G06F21/32 , G06F21/78 , G06K9/00087 , G06K19/07 , G06K19/07354 , G07C9/00087
摘要： An extended universal-serial bus (EUSB) bridge to a host computer can have peripheral component interconnect express (PCIE) protocol layers on one side of the bridge, and EUSB layers on the other side of the bridge, with a high-level bridging converter module connecting the upper layers. The PCIE physical, data-link, and transport layers may be eliminated by integrating the bridge with an I/O controller. PCIE requests and data payloads are directly sent to the bridge, rather than low-level PCIE physical signals. The PCIE data payloads are converted to EUSB data payloads by a high-level direct bridging converter module. Then the EUSB data payloads are passed down to an EUSB transaction layer, an EUSB data-link layer, and an EUSB physical layer which drives and senses physical electrical signals on both differential pairs of the EUSB bus.
摘要翻译：到主机的扩展通用串行总线（EUSB）桥可以在桥的一侧具有外围组件互连快速（PCIE）协议层，并且在桥的另一侧可以具有高级桥接转换器模块连接上层。可以通过将桥与I / O控制器集成来消除PCIE物理，数据链路和传输层。 PCIE请求和数据有效载荷直接发送到桥，而不是低级PCIE物理信号。 PCIE数据有效载荷通过高级直接桥接转换器模块转换为EUSB数据有效载荷。然后，EUSB数据有效载荷被传递到EUSB事务层，EUSB数据链路层和EUSB物理层，其在EUSB总线的两个差分对上驱动和感测物理电信号。

4. 发明授权

US07934074B2 Flash module with plane-interleaved sequential writes to restricted-write flash chips 有权
标题翻译：闪存模块，具有平面交错顺序写入限制写入闪存芯片
公开(公告)号：US07934074B2
公开(公告)日：2011-04-26
申请号：US11871011
申请日：2007-10-11
申请人： Charles C. Lee , Frank Yu , Ming-Shiang Shen , Abraham C. Ma , David Q. Chow
发明人： Charles C. Lee , Frank Yu , Ming-Shiang Shen , Abraham C. Ma , David Q. Chow
IPC分类号： G06F12/06
CPC分类号： G06F12/0246 , G06F12/0607 , G06F2212/7201 , G06F2212/7208 , G11C11/5621 , G11C16/0408
摘要： A flash memory controller on a PCIE bus controls flash-memory modules on a flash bus. The flash-memory modules are plane-interleaved using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. A physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. A RAM physical page valid table tracks valid pages in the four planes, while a RAM mapping table stores the plane, block, and page addresses for logical sectors generated by the physical sequential address counter.
摘要翻译： PCIE总线上的闪存控制器控制闪存总线上的闪存模块。闪存模块使用从逻辑块索引的最低位提取的交错比特进行平面交织。这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。物理顺序地址计数器通过在中间物理块比特之前递增平面交织比特，然后将MSB重新定位到中间物理块比特之上来生成物理块号。这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。 RAM物理页有效表跟踪四个平面中的有效页面，而RAM映射表存储由物理顺序地址计数器生成的逻辑扇区的平面，块和页面地址。

5. 发明授权

US07707321B2 Chained DMA for low-power extended USB flash device without polling 失效
标题翻译：用于低功耗扩展USB闪存设备的链接DMA，无轮询
公开(公告)号：US07707321B2
公开(公告)日：2010-04-27
申请号：US11928124
申请日：2007-10-30
申请人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
发明人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
IPC分类号： G06F3/00 , G06F13/38
CPC分类号： G06F13/28 , Y02D10/14
摘要： An extended Universal-Serial Bus (EUSB) host has reduced loading by using radio frequency (RF) transceivers or direct wiring traces rather than a pair of legacy USB cables. The reduced loading opens the eye pattern. The EUSB device transfers internal data using chained Direct-Memory Access (DMA). Registers in a DMA controller point to a vector table that has vector entries, each pointing to a destination and a source. The source is a memory table for a memory group. The memory table has entries for several memory segments. Each memory-table entry has a pointer to a memory segment and a byte count for the segment. Once all bytes in the segment are transferred, a flag in the entry indicates when another memory segment follows within the memory group. When an END flag is read, then vector table is advanced to the next vector entry, and another memory group of memory segments processed.
摘要翻译：扩展的通用串行总线（EUSB）主机通过使用射频（RF）收发器或直接布线轨迹而不是一对传统的USB电缆减少了负载。减少负荷打开眼睛图案。 EUSB设备使用链接的直接内存访问（DMA）传输内部数据。 DMA控制器中的寄存器指向具有向量条目的向量表，每个向量表指向一个目的地和一个源。源是内存组的内存表。内存表有几个内存段的条目。每个存储表条目具有指向存储器段的指针和段的字节计数。一旦片段中的所有字节都被传送，该条目中的标志表示在存储器组中跟随其他内存段的时间。读取END标志时，向量表前进到下一个向量条目，并处理另一个内存段的内存组。

6. 发明申请

US20080250195A1 Multi-Operation Write Aggregator Using a Page Buffer and a Scratch Flash Block in Each of Multiple Channels of a Large Array of Flash Memory to Reduce Block Wear 失效
标题翻译：多操作写入聚合器使用大量Flash存储器的多个通道中的每一个中的页面缓冲区和划痕闪存块来减少块磨损
公开(公告)号：US20080250195A1
公开(公告)日：2008-10-09
申请号：US12139842
申请日：2008-06-16
申请人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
发明人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F21/32 , G06F21/78 , G06F2212/1036 , G06F2212/7202 , G06F2212/7208 , G06K19/07 , G06K19/07354
摘要： A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer is reached, the page buffer is written to a target physical block if full, or combined with old data fragments in an Aggregating Flash Block (AFB) when the logical-sector addresses (LSA's) match. Thus small fragments are aggregated using the AFB, reducing erases and wear of flash blocks. The page buffer is copied to the AFB when a STOP command occurs. Each channel has one or more AFB's, which are tracked by an AFB tracking table.
摘要翻译：闪存系统具有可以并行访问的多个闪存芯片的通道。主机数据被多通道控制器处理器分配给一个通道，并且累积在多通道页缓冲器中。当到达页面缓冲区中的页面边界时，如果逻辑扇区地址（LSA）匹配，则页缓冲区将被写入目标物理块（如果已满）或与聚合闪存块（AFB）中的旧数据片段组合。因此，使用AFB聚集小片段，减少闪存块的擦除和磨损。发生STOP命令时，页面缓冲区被复制到AFB。每个通道都有一个或多个AFB，它们由AFB跟踪表进行跟踪。

7. 发明申请

US20080235443A1 Intelligent Solid-State Non-Volatile Memory Device (NVMD) System With Multi-Level Caching of Multiple Channels 失效
标题翻译：具有多通道多级缓存的智能固态非易失性存储器件（NVMD）系统
公开(公告)号：US20080235443A1
公开(公告)日：2008-09-25
申请号：US12115128
申请日：2008-05-05
申请人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
发明人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F12/02
CPC分类号： G06F12/1416 , G06F3/0664 , G06F12/0851 , G06F12/0866 , G06F12/0897 , G06F21/32 , G06F21/78 , G06F21/79 , G06F2212/2022 , Y02D10/13
摘要： A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.
摘要翻译：闪存系统存储由逻辑块地址（LBA）寻址的非易失性存储器件（NVMD）中的数据块。 NVBA将对LBA进行重新配置以进行磨损均衡和坏块重定位。 NVMD在由NVMD控制器访问的通道中进行交织。 NVMD控制器具有缓存存储在该通道中的NVMD中的块的控制器高速缓存，而NVMD还包含高速缓存。多级缓存可以减少访问延迟。电源由NVMD控制器中的电源控制器以多级管理，为NVMD内的电源管理器设置电源策略。闪存系统中的多个NVMD控制器可以各自控制多个NVMD通道。具有NVMD的闪存系统可能包括用于安全性的指纹读取器。

8. 发明授权

US08171204B2 Intelligent solid-state non-volatile memory device (NVMD) system with multi-level caching of multiple channels 失效
标题翻译：智能固态非易失性存储器件（NVMD）系统具有多通道多级缓存
公开(公告)号：US08171204B2
公开(公告)日：2012-05-01
申请号：US12115128
申请日：2008-05-05
申请人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
发明人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F13/00
CPC分类号： G06F12/1416 , G06F3/0664 , G06F12/0851 , G06F12/0866 , G06F12/0897 , G06F21/32 , G06F21/78 , G06F21/79 , G06F2212/2022 , Y02D10/13
摘要： A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.
摘要翻译：闪存系统存储由逻辑块地址（LBA）寻址的非易失性存储器件（NVMD）中的数据块。 NVBA将对LBA进行重新配置以进行磨损均衡和坏块重定位。 NVMD在由NVMD控制器访问的通道中进行交织。 NVMD控制器具有缓存存储在该通道中的NVMD中的块的控制器高速缓存，而NVMD还包含高速缓存。多级缓存可以减少访问延迟。电源由NVMD控制器中的电源控制器以多级管理，为NVMD内的电源管理器设置电源策略。闪存系统中的多个NVMD控制器可以各自控制多个NVMD通道。具有NVMD的闪存系统可能包括用于安全性的指纹读取器。

9. 发明授权

US07966462B2 Multi-channel flash module with plane-interleaved sequential ECC writes and background recycling to restricted-write flash chips 有权
标题翻译：具有平面交错顺序ECC的多通道闪存模块写入和背景回收到限制写入闪存芯片
公开(公告)号：US07966462B2
公开(公告)日：2011-06-21
申请号：US11871627
申请日：2007-10-12
申请人： Charles C. Lee , Frank Yu , Ming-Shiang Shen , Abraham C. Ma , David Q. Chow
发明人： Charles C. Lee , Frank Yu , Ming-Shiang Shen , Abraham C. Ma , David Q. Chow
IPC分类号： G06F12/02
CPC分类号： G06F12/0607 , G06F12/0246 , G06F2212/7201 , G06F2212/7203 , G06F2212/7205 , G06F2212/7208 , G11C16/0408 , G11C2211/5649
摘要： A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.
摘要翻译：使用由物理顺序地址计数器生成的平面，块和页面地址从闪存中恢复RAM映射表。 RAM映射表在使用从逻辑块索引的最低位提取的交错比特的物理顺序地址计数器产生的平面交织序列之后恢复。这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。物理顺序地址计数器通过在中间物理块位之前递增平面交织比特，然后将MSB重定位到中间物理块比特之上来生成物理块号。这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。还执行后台回收和ECC写入。

10. 发明授权

US07761653B2 Flash micro-controller with shadow boot-loader SRAM for dual-device booting of micro-controller and host 失效
标题翻译：闪存微控制器带有引导加载器的SRAM，用于微控制器和主机的双设备启动
公开(公告)号：US07761653B2
公开(公告)日：2010-07-20
申请号：US11875648
申请日：2007-10-19
申请人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen
发明人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F9/441
摘要： A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The boot code includes an initial boot loader, boot code and a control program that are executed by the flash microcontroller, and an operating system OS image and an external-host control program that are executed by an external host. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A first-reset-read address from the external host is captured by the microcontroller during its boot sequence and stored in a mapping table along with a physical address of the block in the SRAM buffer with the operating system OS image and the external-host control program. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory.
摘要翻译：闪存微控制器具有静态随机存取存储器（SRAM）缓冲器，其存储从闪存读取的几个引导代码块。引导代码包括由闪存微控制器执行的初始引导加载程序，引导代码和控制程序，以及由外部主机执行的操作系统OS映像和外部主机控制程序。外部主机和微控制器均由缓冲在SRAM缓冲区中的引导代码引导。微控制器在其引导序列期间捕获来自外部主机的第一复位读取地址，并将其与SRAM缓冲器中具有操作系统OS映像和外部主机控制的块的物理地址一起存储在映射表中程序。引导加载器状态机读取闪存ID，并使用Flash存储器的时序参数对闪存参数寄存器进行编程。

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