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91. 发明授权

US5234867A Method for planarizing semiconductor wafers with a non-circular polishing pad 失效
标题翻译：用非圆形抛光垫平面化半导体晶片的方法
公开(公告)号：US5234867A
公开(公告)日：1993-08-10
申请号：US889521
申请日：1992-05-27
申请人： Laurence D. Schultz , Mark E. Tuttle , Trung T. Doan
发明人： Laurence D. Schultz , Mark E. Tuttle , Trung T. Doan
IPC分类号： B24B7/22 , B24B13/01 , B24B37/04 , B24D11/00 , H01L21/304 , H01L21/306 , H01L21/687
CPC分类号： B24B37/04 , B24B37/26 , B24B7/228 , B24D11/00
摘要： An apparatus for planarizing semiconductor wafers in its preferred form includes a rotatable platen for polishing a surface of the semiconductor wafer and a motor for rotating the platen. A non-circular pad is mounted atop the platen to engage and polish the surface of the semiconductor wafer. A polishing head holds the surface of the semiconductor wafer in juxtaposition relative to the non-circular pad. A polishing head displacement mechanism moves the polishing head and semiconductor wafer across and past a peripheral edge of the non-circular pad to effectuate a uniform polish of the semiconductor wafer surface. Also disclosed is a method for planarizing a semiconductor surface using a non-circular polishing pad.
摘要翻译：用于以优选形式平坦化半导体晶片的装置包括用于抛光半导体晶片的表面的可旋转压板和用于旋转压板的电动机。非圆形焊盘安装在压板上方以接合和抛光半导体晶片的表面。抛光头保持半导体晶片的表面相对于非圆形焊盘并置。抛光头位移机构将抛光头和半导体晶片移动并穿过非圆形焊盘的周边边缘，以实现半导体晶片表面的均匀抛光。还公开了使用非圆形抛光垫对半导体表面进行平面化的方法。

92. 发明授权

US5223081A Method for roughening a silicon or polysilicon surface for a semiconductor substrate 失效
标题翻译：用于粗糙化半导体衬底的硅或多晶硅表面的方法
公开(公告)号：US5223081A
公开(公告)日：1993-06-29
申请号：US725357
申请日：1991-07-03
申请人： Trung T. Doan
发明人： Trung T. Doan
IPC分类号： H01L21/02 , H01L21/306 , H01L21/3213
CPC分类号： H01L28/84 , H01L21/306 , H01L21/32134 , Y10S438/964
摘要： This invention relates to a method for roughening a silicon or polysilicon substrate of a semiconductor. The method includes the steps of: depositing a metal layer onto the substrate, heating the metal layer and substrate through to form a metal silicide on the substrate by reaction of the metal layer and substrate, and removing the metal silicide and a metal oxide by selective etching to expose the roughened surface. The actual etching process may be a two-step procedure. A first etch uses ammonium hydroxide and hydrogen peroxide to remove the oxide layer formed with the silicide. A second etch uses hydrofluoric acid to remove the silicide.
摘要翻译：本发明涉及一种用于粗糙化半导体的硅或多晶硅衬底的方法。该方法包括以下步骤：在衬底上沉积金属层，加热金属层和衬底，以通过金属层和衬底的反应在衬底上形成金属硅化物，并通过选择性去除金属硅化物和金属氧化物蚀刻以暴露粗糙表面。实际的蚀刻工艺可以是两步法。第一蚀刻使用氢氧化铵和过氧化氢去除由硅化物形成的氧化物层。第二次蚀刻使用氢氟酸去除硅化物。

93. 发明授权

US5204286A Method of making self-aligned contacts and vertical interconnects to integrated circuits 失效
标题翻译：将自对准触点和垂直互连制成集成电路的方法
公开(公告)号：US5204286A
公开(公告)日：1993-04-20
申请号：US775744
申请日：1991-10-15
申请人： Trung T. Doan
发明人： Trung T. Doan
IPC分类号： H01L27/10 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/108
CPC分类号： H01L21/76805 , H01L21/76831 , Y10S148/05
摘要： A process for making vertical electrical interconnections in a variety of integrated circuits and novel IC structures produced thereby wherein buried conductors are provided within a dielectric layer located above a silicon substrate having active or passive devices formed therein. Internal edges of only one or selected ones of the conductors are provided with an insulating coating, so that an adjacent via may be filled with a conductive material and still be electrically isolated from the one conductor or conductors. One or more vias are etched directly through the other buried conductor or conductors and also filled with a conductive material which electrically connects this buried conductor or conductors to both the substrate and to an upper level of metallization, and alternatively to intermediate conductors or other components. In this manner, lateral offset spacing requirements for masking and etching is minimized to thereby maximize the achievable component packing density within the IC structure being manufactured.
摘要翻译：一种用于在各种集成电路中制造垂直电互连的方法以及由此产生的新型IC结构，其中在位于其上形成有有源或无源器件的硅衬底之上的介电层内提供埋入导体。只有一个或所选导体的内部边缘设置有绝缘涂层，使得相邻的通孔可以填充有导电材料，并且仍然与一个导体或导体电隔离。一个或多个通孔被直接蚀刻通过另一掩埋导体或导体，并且还填充有导电材料，该导电材料将该埋置的导体或导体电连接到基板和上层金属化，以及可替代地到中间导体或其它部件。以这种方式，用于掩模和蚀刻的横向偏移间隔要求最小化，从而使正在制造的IC结构内的可实现的部件堆积密度最大化。

94. 发明授权

US5124780A Conductive contact plug and a method of forming a conductive contact plug in an integrated circuit using laser planarization 失效
标题翻译：导电接触插塞和使用激光平面化在集成电路中形成导电接触插塞的方法
公开(公告)号：US5124780A
公开(公告)日：1992-06-23
申请号：US713187
申请日：1991-06-10
申请人： Gurtej S. Sandhu , Chang Yu , Trung T. Doan , Mark E. Tuttle
发明人： Gurtej S. Sandhu , Chang Yu , Trung T. Doan , Mark E. Tuttle
IPC分类号： H01L21/28 , H01L21/321 , H01L21/768 , H01L23/532
CPC分类号： H01L23/53223 , H01L21/32115 , H01L21/7684 , H01L21/76879 , H01L2924/0002
摘要： The invention is a method of forming a conductive contact plug and an interconnect line independent of each other. The contact plug is formed using laser planarization and a blanket etch back. The invention is also the contact plug thus formed. The contact plug and interconnect line may be fabricated with conductive materials having substantially similar methods of deposition. The integrity of the contact plug is enhanced using laser planarization.The process begins with a wafer having a dielectric layer, the upper surface of which has been planarized. A masking step defines a contact hole. An etch creates the contact hole which passes through the dielectric layer to a conductive region where contact is to be made. A first layer of conductive material is then deposited overlying the dielectric layer. A layer of material having an anti-reflective coating (ARC) (or a layer of material having a higher boiling point than the first layer) is deposited overlying the first layer. The ARC enhances the fluidity of the first layer during a subsequent laser planarization. The first layer and ARC overlying the dielectric are then laser planarized. The laser planarization is followed by a blanket etch of the first layer and ARC. The etch forms a contact plug substantially coplanar with the surface of the dielectric layer. At this juncture a second layer of conductive material may be deposited and masked to form interconnect lines for joining contact plugs.
摘要翻译：本发明是形成彼此独立的导电接触插塞和互连线的方法。接触塞是使用激光平面化和毯式回蚀而形成的。本发明也是如此形成的接触塞。接触插塞和互连线可以用具有基本相似的沉积方法的导电材料制成。使用激光平面化增强了接触插塞的完整性。该方法开始于具有介电层的晶片，其上表面已被平坦化。掩模步骤限定接触孔。蚀刻产生穿过介电层的接触孔到要进行接触的导电区域。然后将第一层导电材料沉积在电介质层上。具有抗反射涂层（ARC）（或具有比第一层沸点高的材料层）的材料层沉积在第一层上。 ARC在随后的激光平面化期间增强了第一层的流动性。然后将覆盖电介质的第一层和ARC激光平面化。激光平面化之后是第一层和ARC的毯式蚀刻。蚀刻形成与电介质层的表面基本上共面的接触插塞。在这个时刻，第二层导电材料可以被沉积和掩蔽以形成用于连接接触插塞的互连线。

95. 发明授权

US5094977A Stress reduction in metal films by laser annealing 失效
标题翻译：通过激光退火对金属膜进行应力减小
公开(公告)号：US5094977A
公开(公告)日：1992-03-10
申请号：US645865
申请日：1991-01-25
申请人： Chang Yu , Trung T. Doan , Gurtej S. Sandhu
发明人： Chang Yu , Trung T. Doan , Gurtej S. Sandhu
IPC分类号： H01L21/285 , H01L21/321
CPC分类号： H01L21/321 , H01L21/28518 , Y10S148/09 , Y10S148/093
摘要： A method of processing a semiconductor wafer comprises, a) chemical vapor depositing (CVD) a metal layer atop a semiconductor substrate; and b) impinging laser energy upon the CVD metal layer at an optical fluence of from 0.05 Joules/cm.sup.2 to 0.30 Joules/cm.sup.2 for a period of time sufficient to relieve mechanical stress associated with the CVD metal layer yet insufficient to melt the CVD metal layer. In accordance with another aspect of the invention, such treatment method could also be used to form a desired silicide layer in the same step.
摘要翻译：一种处理半导体晶片的方法包括：a）化学气相沉积（CVD）在半导体衬底顶上的金属层; 和b）以0.05焦耳/厘米2至0.30焦耳/平方厘米的光能密度将激光能量照射在CVD金属层上足以缓解与CVD金属层相关的机械应力但不足以熔化CVD金属层的时间。根据本发明的另一方面，这种处理方法也可用于在同一步骤中形成所需的硅化物层。

96. 发明授权

US5021353A Split-polysilicon CMOS process incorporating self-aligned silicidation of conductive regions 失效
标题翻译：分离多晶硅CMOS工艺结合导电区域的自对准硅化物
公开(公告)号：US5021353A
公开(公告)日：1991-06-04
申请号：US485029
申请日：1990-02-26
申请人： Tyler A. Lowrey , Dermot M. Durcan , Trung T. Doan , Gordon A. Haller , Mark E. Tuttle
发明人： Tyler A. Lowrey , Dermot M. Durcan , Trung T. Doan , Gordon A. Haller , Mark E. Tuttle
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/665 , H01L21/823835
摘要： An improved CMOS fabrication process which uses separate masking steps to pattern N-channel and P-channel transistor gates from a single layer of conductively-doped polycrystalline silicon (poly) and incorporates self-aligned salicidation of conductive regions. The object of the improved process is to reduce the cost and improve the reliability, performance and manufacturability of CMOS devices by a process which features a dramatically reduced number of photomasking steps and which further allows self-aligned salicidation of transistor conductive regions. By processing N-channel and P-channel devices separately, the number of photomasking steps required to fabricate complete CMOS circuitry in a single-polysilicon-layer or single-metal layer process can be reduced from eleven to eight. Starting with a substrate of P-type material, N-channel devices are formed first, with unetched poly left in the future P-channel regions until N-channel processing is complete. The improved CMOS process provides the following advantages over conventional process technology: Use of a masked high-energy punch-through implant for N-channel devices is not required; individual optimization of N-channel and P-channel transistors is made possible; a lightly-doped drain (LDD) design for both N-channel and P-channel transistors is readily implemented; source/drain-to-gate offset may be changed independently for N-channel and P-channel devices; and N-channel and P-channel transistors can be independently controlled and optimized for best LDD performance and reliability.
摘要翻译：一种改进的CMOS制造工艺，其使用单独的掩模步骤来从单层导电掺杂多晶硅（poly）中的N沟道和P沟道晶体管栅极图案化，并且引入导电区域的自对准的阳离子化。改进方法的目的是降低成本，并且通过具有显着减少的光掩模步骤数目并进一步允许晶体管导电区域的自对准盐化的方法来降低CMOS器件的可靠性，性能和可制造性。通过分别处理N沟道和P沟道器件，在单多晶硅层或单金属层工艺中制造完整的CMOS电路所需的光掩模步骤的数量可以从11减少到8个。从P型材料的衬底开始，首先形成N沟道器件，在未来的P沟道区域中留下未蚀刻的聚合物，直到N沟道处理完成。与传统工艺技术相比，改进的CMOS工艺提供了以下优点：不需要对N沟道器件使用掩模的高能穿孔注入器; N通道和P沟道晶体管的单独优化成为可能; 容易实现用于N沟道和P沟道晶体管的轻掺杂漏极（LDD）设计; 源/漏 - 门偏移可以针对N沟道和P沟道器件独立地改变; 可以独立控制和优化N沟道和P沟道晶体管，以获得最佳的LDD性能和可靠性。

97. 发明授权

US5001085A Process for creating a metal etch mask which may be utilized for halogen-plasma excavation of deep trenches 失效
标题翻译：用于制造可用于深沟槽的卤素等离子体挖掘的金属蚀刻掩模的方法
公开(公告)号：US5001085A
公开(公告)日：1991-03-19
申请号：US554630
申请日：1990-07-17
申请人： David A. Cathey , Trung T. Doan
发明人： David A. Cathey , Trung T. Doan
IPC分类号： H01L21/3065 , H01L21/308
CPC分类号： H01L21/3081 , H01L21/3065 , Y10S148/105 , Y10S438/945
摘要： A process for creating a metal etch mask from either cobalt, nickel, palladium, iron or copper which may be utilized for halogen-plasma excavation of deep trenches. The process begins by creating a thin isolation layer of either silicon nitride or silicon dioxide on top of the layer to be trenched. A thin layer of one of the metals selected from the aforementioned list of five is then created on top of the isolation layer. A layer of polysilicon is then blanket deposited on top of the refractory metal layer. Photoresist masking is then performed as though the photoresist were the actual pattern for the trench etch. Exposed portions of the polysilicon layer are then etched away with an anisotropic etch. Following a photoresist strip, the substrate and overlying layers are subjected to an elevated temperature step, which causes the polysilicon to react with the underlying metal layer to form metal silicide. In substrate regions where no polysilicon overlies the metal layer, no silicide is formed. Next, the metal silicide is removed with a wet etch. A metal mask remains that is essentially an exact image of the original photoresist mask. Trenches may be etched to any desired depth with virtually no consumption of the metal mask. Once the trench etch is complete, the metal etch mask may be stripped utilizing a wet etch reagent such as aqua regia.
摘要翻译：用于从钴，镍，钯，铁或铜制造金属蚀刻掩模的方法，其可用于深沟槽的卤素等离子体挖掘。该过程开始于在待沟槽的层的顶部上形成氮化硅或二氧化硅的薄隔离层。然后在隔离层的顶部上形成从上述五个列表中选出的金属之一的薄层。然后将多晶硅层覆盖在难熔金属层的顶部。然后进行光刻胶掩模，就像光致抗蚀剂是沟槽蚀刻的实际图案一样。然后用各向异性蚀刻蚀刻掉多晶硅层的暴露部分。在光致抗蚀剂条之后，使衬底和覆盖层经受高温步骤，这使得多晶硅与下面的金属层反应形成金属硅化物。在没有多晶硅覆盖金属层的衬底区域中，不形成硅化物。接下来，用湿蚀刻去除金属硅化物。残留的金属掩模基本上是原始光刻胶掩模的精确图像。沟槽可以蚀刻到任何所需的深度，几乎不消耗金属掩模。一旦沟槽蚀刻完成，就可以使用湿蚀刻剂如王水去除金属蚀刻掩模。

98. 发明授权

US08518184B2 Methods and systems for controlling temperature during microfeature workpiece processing, E.G., CVD deposition 有权
标题翻译：在微加工工件加工过程中控制温度的方法和系统，E.G.，CVD沉积
公开(公告)号：US08518184B2
公开(公告)日：2013-08-27
申请号：US12840153
申请日：2010-07-20
申请人： Kevin L. Beaman , Trung T. Doan , Lyle D. Breiner , Ronald A. Weimer , Er-Xuan Ping , David J. Kubista , Cem Basceri , Lingyi A. Zheng
发明人： Kevin L. Beaman , Trung T. Doan , Lyle D. Breiner , Ronald A. Weimer , Er-Xuan Ping , David J. Kubista , Cem Basceri , Lingyi A. Zheng
IPC分类号： C23C16/00
CPC分类号： C23C16/00 , C23C16/46
摘要： The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.
摘要翻译：本公开提供了用于控制温度的方法和系统。该方法在沉积工艺中控制温度，例如通过CVD沉积热反射材料方面具有特别的用途。一个示例性实施例提供了一种方法，其涉及监测沉积室外的第一温度和沉积室内的第二温度。通过（a）将控制温度与目标温度进行比较，可以根据斜坡分布来增加沉积室中的内部温度，以及（b）响应于比较的结果，选择性地将热量输送到沉积室。目标温度可以根据斜坡分布来确定，但是一个实现中的控制温度在第一温度和第二温度之间交替。

99. 发明申请

US20110163416A1 METHODS FOR FORMING SMALL-SCALE CAPACITOR STRUCTURES 有权
标题翻译：形成小尺寸电容器结构的方法
公开(公告)号：US20110163416A1
公开(公告)日：2011-07-07
申请号：US13047430
申请日：2011-03-14
申请人： Lingyi A. Zheng , Trung T. Doan , Lyle D. Breiner , Er-Xuan Ping , Kevin L. Beaman , Ronald A. Weimer , Cem Basceri , David J. Kubista
发明人： Lingyi A. Zheng , Trung T. Doan , Lyle D. Breiner , Er-Xuan Ping , Kevin L. Beaman , Ronald A. Weimer , Cem Basceri , David J. Kubista
IPC分类号： H01L29/92 , G06F19/00
CPC分类号： H01L28/40 , H01L21/3141 , H01L27/10852 , H01L28/60 , H01L28/84
摘要： The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 Å.
摘要翻译：本公开提供小尺寸电容器（例如，DRAM电容器）以及形成这种电容器的方法。一个示例性实施例提供了一种制造电容器的方法，该电容器包括顺序地形成第一电极，电介质层和第二电极。可以通过以下方式形成至少一个电极：a）使两个前体反应以第一沉积速率沉积第一导电层，以及b）通过沉积一个前体的前体层以第二较低沉积速率沉积第二导电层至少一层单层，并将该前体层暴露于另一种前体以形成纳米层反应产物。第二导电层可以与介电层接触并具有不大于约的厚度。

100. 发明申请

US20100102433A1 APPARATUS FOR USE IN SEMICONDUCTOR WAFER PROCESSING FOR LATERALLY DISPLACING INDIVIDUAL SEMICONDUCTOR DEVICES AWAY FROM ONE ANOTHER 审中-公开
标题翻译：用于半导体波浪处理的装置，用于从另一个另外的侧面移除单个半导体器件
公开(公告)号：US20100102433A1
公开(公告)日：2010-04-29
申请号：US12650179
申请日：2009-12-30
申请人： Trung T. Doan
发明人： Trung T. Doan
IPC分类号： H01L23/498
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/3185 , H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05572 , H01L2224/056 , H01L2224/11 , H01L2224/1191 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2224/16 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01032 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2224/29099 , H01L2924/00 , H01L2224/05099
摘要： A chip-scale or wafer-level package, having passivation layers on substantially all surfaces thereof to form a hermetically sealed package, is provided. The package may be formed by disposing a first passivation layer on the passive or back side surface of a semiconductor wafer. The semiconductor wafer may be attached to a flexible membrane and diced, such as by a wafer saw, to separate the semiconductor devices. Once diced, the flexible membrane may be stretched so as to laterally displace the individual semiconductor devices away from one another and substantially expose the side edges thereof. Once the side edges of the semiconductor devices are exposed, a passivation layer may be formed on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device may be removed so as to expose conductive elements formed therebeneath.
摘要翻译：提供了在其基本上所有表面上具有钝化层以形成气密密封封装的芯片级或晶圆级封装。可以通过在半导体晶片的无源或背侧表面上设置第一钝化层来形成封装。半导体晶片可以附接到柔性膜并且例如通过晶片锯切割，以分离半导体器件。一旦切割，柔性膜可以被拉伸，以使各个半导体器件彼此横向移位并且基本上暴露其侧边缘。一旦半导体器件的侧边缘被暴露，就可以在器件的侧边缘和有源表面上形成钝化层。可以去除每个半导体器件的有源表面上的钝化层的一部分，以便暴露在其下形成的导电元件。

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