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91. 发明授权

US07704852B2 Amorphization/templated recrystallization method for hybrid orientation substrates 失效
标题翻译：混合取向基板的非晶化/模板重结晶方法
公开(公告)号：US07704852B2
公开(公告)日：2010-04-27
申请号：US11871694
申请日：2007-10-12
申请人： Keith E. Fogel , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith E. Fogel , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/76
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprising the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches, (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。本发明的工艺流程解决了现有技术ATR方法未公开的两个主要困难：在由沟槽界定的非晶化Si区域的边缘产生“角缺陷”，以及在高温后再结晶缺陷 - 未被沟槽限定的非ATR区域的去除退火。特别地，本发明提供了一种工艺流程，其包括以下步骤：（i）在没有沟槽的衬底区域中进行非晶化和低温重结晶，（ii）形成在ATR'边缘处的缺陷区域的沟槽隔离区域的形成， d区域，以及（iii）在沟槽隔离区域中进行的高温缺陷去除退火。

92. 发明授权

US07691733B2 Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics 失效
标题翻译：激光加工方法用于封闭几何中的无边缘无缺陷固相外延
公开(公告)号：US07691733B2
公开(公告)日：2010-04-06
申请号：US12062749
申请日：2008-04-04
申请人： Keith E. Fogel , Kam-Leung Lee , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith E. Fogel , Kam-Leung Lee , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/20
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。特别地，本发明提供熔融重结晶ATR方法，其单独使用或与非熔融再结晶ATR方法组合使用，其中通过介电填充沟槽界定的选定的Si区域被诱导通过以下步骤进行取向改变：熔融前体变形，激光熔化和无角点缺陷的模板重结晶。

93. 发明申请

US20100006985A1 FORMATION OF SOI BY OXIDATION OF SILICON WITH ENGINEERED POROSITY GRADIENT 失效
标题翻译：通过氧化硅与工程化孔隙度梯度形成SOI
公开(公告)号：US20100006985A1
公开(公告)日：2010-01-14
申请号：US12170459
申请日：2008-07-10
申请人： Joel P. DeSouza , Keith E. Fogel , Alexander Reznicek , Devendra Sadana
发明人： Joel P. DeSouza , Keith E. Fogel , Alexander Reznicek , Devendra Sadana
IPC分类号： H01L29/12 , H01L21/20
CPC分类号： H01L21/76245
摘要： A method is provided for making a silicon-on-insulator substrate. Such method can include epitaxially growing a highly p-type doped silicon-containing layer onto a major surface of an underlying semiconductor region of a substrate. Subsequently, a non-highly p-type doped silicon-containing layer may be epitaxially grown onto a major surface of the p-type highly-doped epitaxial layer to cover the highly p-type doped epitaxial layer. The overlying non-highly p-type doped epitaxial layer can have a dopant concentration substantially lower than the dopant concentration of the highly p-type doped epitaxial layer. The substrate can then be processed to form a buried oxide layer selectively by oxidizing at least portions of the highly p-type doped epitaxial layer covered by the non-highly p-type doped epitaxial layer, the buried oxide layer separating the overlying monocrystalline semiconductor layer from the underlying semiconductor region. Such processing can be performed while simultaneously annealing the non-highly p-type doped epitaxial layer.
摘要翻译：提供了一种制造绝缘体上硅衬底的方法。这种方法可以包括将高p型掺杂的含硅层外延生长到衬底的下面的半导体区域的主表面上。随后，可以在p型高掺杂外延层的主表面上外延生长非高度p型掺杂的含硅层，以覆盖高度p型掺杂的外延层。上覆非高p型掺杂外延层可以具有基本上低于高p型掺杂外延层的掺杂剂浓度的掺杂剂浓度。然后可以通过氧化由非高p型掺杂的外延层覆盖的高p型掺杂外延层的至少一部分来选择性地处理衬底以形成掩埋氧化物层，将覆盖的单晶半导体层从底层半导体区域。可以在非高p型掺杂外延层同时退火的同时执行这种处理。

94. 发明申请

US20090134460A1 STRAINED SEMICONDUCTOR-ON-INSULATOR (sSOI) BY A SIMOX METHOD 有权
标题翻译：应变半导体绝缘体（sSOI）通过SIMOX方法
公开(公告)号：US20090134460A1
公开(公告)日：2009-05-28
申请号：US12363239
申请日：2009-01-30
申请人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
IPC分类号： H01L27/00 , H01L21/71
CPC分类号： H01L21/76243 , H01L29/66772 , H01L29/7849 , H01L29/78654
摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.
摘要翻译：提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

95. 发明授权

US07485539B2 Strained semiconductor-on-insulator (sSOI) by a simox method 有权
标题翻译：应用绝缘体半导体（sSOI）通过simox方法
公开(公告)号：US07485539B2
公开(公告)日：2009-02-03
申请号：US11332564
申请日：2006-01-13
申请人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
IPC分类号： H01L21/76
CPC分类号： H01L21/76243 , H01L29/66772 , H01L29/7849 , H01L29/78654
摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.
摘要翻译：提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

96. 发明申请

US20080277690A1 STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED p+ SILICON GERMANIUM LAYER 审中-公开
标题翻译：通过阳极氧化P +硅锗层的分级制备的绝缘硅绝缘体
公开(公告)号：US20080277690A1
公开(公告)日：2008-11-13
申请号：US12176624
申请日：2008-07-21
申请人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L21/76259 , Y10S438/967
摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.
摘要翻译：提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。

97. 发明授权

US07442993B2 Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer 有权
标题翻译：通过弹性应变转移形成的超薄，高品质应变绝缘体上的绝缘体
公开(公告)号：US07442993B2
公开(公告)日：2008-10-28
申请号：US11293774
申请日：2005-12-02
申请人： Stephen W. Bedell , Anthony G. Domenicucci , Keith E. Fogel , Effendi Leobandung , Devendra K. Sadana
发明人： Stephen W. Bedell , Anthony G. Domenicucci , Keith E. Fogel , Effendi Leobandung , Devendra K. Sadana
IPC分类号： H01L31/392
CPC分类号： H01L29/78696 , H01L21/0237 , H01L21/02439 , H01L21/02488 , H01L21/02502 , H01L21/02521 , H01L21/02667 , H01L21/02694 , H01L21/76251 , H01L29/7842
摘要： A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.
摘要翻译：提供了一种在绝缘层上形成包括第一应变半导体层的半导体结构的方法，其中第一应变半导体层相对较薄（小于约）并且具有低缺陷密度（堆垛层错和穿线缺陷）。本发明的方法开始于在包括位于绝缘层顶部的第一半导体层的结构上形成应力提供层，例如SiGe合金层。然后将应力提供层和第一半导体层图案化成至少一个岛，然后将含有至少一个岛的结构加热到使得应力转移从应力提供层到第一半导体层的温度。在应变转移之后，将应力提供层从结构上去除，以形成直接位于所述绝缘层顶部的第一应变半导体岛层。

98. 发明申请

US20080206979A1 INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION BARRIER LAYERS 有权
标题翻译：使用无铅焊盘和具有反应障碍层的片芯互连
公开(公告)号：US20080206979A1
公开(公告)日：2008-08-28
申请号：US12113152
申请日：2008-04-30
申请人： Keith E. Fogel , Balaram Ghosal , Sung K. Kang , Stephen Kilpatrick , Paul A. Lauro , Henry A. Nye , Da-Yuan Shih , Donna S. Zupanski-Nielsen
发明人： Keith E. Fogel , Balaram Ghosal , Sung K. Kang , Stephen Kilpatrick , Paul A. Lauro , Henry A. Nye , Da-Yuan Shih , Donna S. Zupanski-Nielsen
IPC分类号： H01L21/60
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L24/12 , H01L2224/03912 , H01L2224/0401 , H01L2224/05 , H01L2224/1147 , H01L2224/11849 , H01L2224/119 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01055 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/30107 , H01L2924/00014
摘要： An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.
摘要翻译：一种适于将微电子器件芯片倒装连接到封装的互连结构，包括二层，三层或四层限球组合物，包括粘附/反应阻挡层，并且具有与含锡的组分反应的焊料可湿性层无铅焊料，使得可焊接层在焊接期间可以完全消耗，但在焊接期间与无铅焊料接触后，阻挡层保持不变。一个或多个无铅焊料球选择性地位于焊料润湿层上，该无铅焊球包含锡作为主要成分和一种或多种合金成分。

99. 发明授权

US07410833B2 Interconnections for flip-chip using lead-free solders and having reaction barrier layers 有权
标题翻译：使用无铅焊料并具有反应阻挡层的倒装芯片的互连
公开(公告)号：US07410833B2
公开(公告)日：2008-08-12
申请号：US10815103
申请日：2004-03-31
申请人： Keith E. Fogel , Balaram Ghosal , Sung K. Kang , Stephen Kilpatrick , Paul A. Lauro , Henry A. Nye, III , Da-Yuan Shih , Donna S. Zupanski-Nielsen
发明人： Keith E. Fogel , Balaram Ghosal , Sung K. Kang , Stephen Kilpatrick , Paul A. Lauro , Henry A. Nye, III , Da-Yuan Shih , Donna S. Zupanski-Nielsen
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L24/12 , H01L2224/03912 , H01L2224/0401 , H01L2224/05 , H01L2224/1147 , H01L2224/11849 , H01L2224/119 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01055 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/30107 , H01L2924/00014
摘要： An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.
摘要翻译：一种适于将微电子器件芯片倒装连接到封装的互连结构，包括二层，三层或四层限球组合物，包括粘附/反应阻挡层，并且具有与含锡的组分反应的焊料可湿性层无铅焊料，使得可焊接层在焊接期间可以完全消耗，但在焊接期间与无铅焊料接触后，阻挡层保持不变。一个或多个无铅焊料球选择性地位于焊料润湿层上，该无铅焊球包含锡作为主要成分和一种或多种合金成分。

100. 发明授权

US07317226B2 Patterned SOI by oxygen implantation and annealing 有权
标题翻译：通过氧气注入和退火进行图案化SOI
公开(公告)号：US07317226B2
公开(公告)日：2008-01-08
申请号：US10993270
申请日：2004-11-19
申请人： Keith E. Fogel , Mark C. Hakey , Steven J. Holmes , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Keith E. Fogel , Mark C. Hakey , Steven J. Holmes , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L27/01
CPC分类号： H01L21/76243 , H01L21/26506 , H01L21/76267 , Y10T428/12674 , Y10T428/12681
摘要： Methods for forming a patterned SOI region in a Si-containing substrate is provided which has geometries of about 0.25 μm or less. Specifically, one method includes the steps of: forming a patterned dielectric mask on a surface of a Si-containing substrate, wherein the patterned dielectric mask includes vertical edges that define boundaries for at least one opening which exposes a portion of the Si-containing substrate; implanting oxygen ions through the at least one opening removing the mask and forming a Si layer on at least the exposed surfaces of the Si-containing substrate; and annealing at a temperature of about 1250° C. or above and in an oxidizing ambient so as to form at least one discrete buried oxide region in the Si-containing substrate. In one embodiment, the mask is not removed until after the annealing step; and in another embodiment, the Si-containing layer is formed after annealing and mask removal.
摘要翻译：提供了在含Si衬底中形成图案化SOI区的方法，其具有约0.25μm或更小的几何形状。具体而言，一种方法包括以下步骤：在含Si衬底的表面上形成图案化电介质掩模，其中，图案化电介质掩模包括垂直边缘，其限定至少一个露出一部分含Si衬底的开口的边界 ; 通过所述至少一个开口注入氧离子，去除所述掩模并在至少所述含Si衬底的暴露表面上形成Si层; 并在约1250℃或更高的温度下和在氧化环境中进行退火，以便在含Si衬底中形成至少一个离散的掩埋氧化物区域。在一个实施例中，直到退火步骤之后，掩模才被去除; 并且在另一个实施方案中，在退火和掩模去除之后形成含Si层。

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