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1. 发明授权

US07382023B2 Fully depleted SOI multiple threshold voltage application 有权
标题翻译：完全耗尽的SOI多阈值电压应用
公开(公告)号：US07382023B2
公开(公告)日：2008-06-03
申请号：US11093593
申请日：2005-03-29
申请人： Hao-Yu Chen , Chang-Yun Chang , Di-Hong Lee , Fu-Liang Yang
发明人： Hao-Yu Chen , Chang-Yun Chang , Di-Hong Lee , Fu-Liang Yang
IPC分类号： H01L27/01 , H01L27/12 , H01L31/392
CPC分类号： H01L29/78603 , H01L21/76267 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.
摘要翻译：集成电路包括在衬底中形成的衬底和掩埋电介质。掩埋电介质在第一区域具有第一厚度，在第二区域中具有第二埋入介质厚度，以及在第一和第二区域之间的台阶。半导体层覆盖在埋入的电介质上。

2. 发明授权

US07161211B2 Aluminum-containing film derived from using hydrogen and oxygen gas in sputter deposition 有权
标题翻译：在溅射沉积中使用氢和氧气的含铝膜
公开(公告)号：US07161211B2
公开(公告)日：2007-01-09
申请号：US10289550
申请日：2002-11-06
申请人： Kanwal K. Raina , David H. Wells
发明人： Kanwal K. Raina , David H. Wells
IPC分类号： H01L27/01 , H01L27/12 , H01L31/392 , H01L29/76 , H01L29/94
CPC分类号： H01L21/2855 , C23C14/0057 , C23C14/185 , H01L21/32051 , H01L29/458 , H01L29/4908 , Y10S438/937 , Y10T428/12229
摘要： Aluminum-containing films having an oxygen content within the films. The aluminum-containing film is formed by introducing hydrogen gas along with argon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum or aluminum alloys onto a semiconductor substrate. The aluminum-containing film so formed is hillock-free and has low resistivity, relatively low roughness compared to pure aluminum, good mechanical strength, and low residual stress.
摘要翻译：含有膜的含氧膜含铝。在铝或铝合金溅射沉积到半导体衬底上时，通过将氢气与氩气一起引入溅射沉积真空室中形成含铝膜。这样形成的含铝膜与纯铝相比具有低电阻率，较低的粗糙度，良好的机械强度和较低的残余应力。

3. 发明授权

US07049660B2 High-quality SGOI by oxidation near the alloy melting temperature 失效
公开(公告)号：US07049660B2
公开(公告)日：2006-05-23
申请号：US10448948
申请日：2003-05-30
申请人： Stephen W. Bedell , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
发明人： Stephen W. Bedell , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
IPC分类号： H01L31/392
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/7624 , H01L21/76254 , H01L29/1054
摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.

4. 发明授权

US07679141B2 High-quality SGOI by annealing near the alloy melting point 失效
标题翻译：高品质SGOI通过在合金熔点附近退火
公开(公告)号：US07679141B2
公开(公告)日：2010-03-16
申请号：US12027561
申请日：2008-02-07
申请人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Richard J. Murphy , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Richard J. Murphy , Devendra K. Sadana
IPC分类号： H01L31/392
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/7624 , H01L21/76254 , H01L29/1054
摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.
摘要翻译：提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。

5. 发明授权

US07067884B2 Electrostatic discharge device 有权
标题翻译：静电放电装置
公开(公告)号：US07067884B2
公开(公告)日：2006-06-27
申请号：US10743651
申请日：2003-12-22
申请人： Mototsugu Okushima
发明人： Mototsugu Okushima
IPC分类号： H01L27/01 , H01L27/12 , H01L29/00 , H01L31/392
CPC分类号： H01L27/0255
摘要： M pieces of n-well regions nW are provided on a main surface of a p-type silicon substrate 3, and p-well regions pW are provided among the n-well regions adjacent to one another. Moreover, each of the M pieces of n-well regions nW includes an n-type diffusion region nD and a p-type diffusion region pD1, which are formed therein. Furthermore, the p-well region pW includes a p-type diffusion region pD2 therein. The n-type diffusion region nD in a j-th of the n-well region nW is connected to the p-type diffusion region pD1 in a (j+1)-th of the n-well region 10. The p-type diffusion region pD1 in the first n-well region nW is connected to a first terminal 1. The n-type diffusion region nD in the M-th of the n-well region nW is connected to a second terminal 2. In response to a potential relation between desired terminal to be protected (not depicted) and discharge terminal (not depicted) during a normal operation, the first terminal is connected to either one of the terminals, of which potential is higher, and the second terminal 2 is connected to the other of which potential is lower.
摘要翻译：在p型硅衬底3的主表面上设置m个n阱区域nW，并且在彼此相邻的n个阱区域中设置p阱区域pW。此外，n个n区nW中的每一个包括在其中形成的n型扩散区nD和p型扩散区pD 1。此外，p阱区pW中包括p型扩散区pD 2。 n阱区域nW的第j个中的n型扩散区域nD连接到n阱区域10的第（j + 1）个p型扩散区域pD 1。第一n阱区域nW中的p型扩散区域pD 1连接到第一端子1。 n阱区域nW的M阶中的n型扩散区域nD连接到第二端子2。响应于在正常操作期间期望的待保护端子（未示出）和放电端子（未示出）之间的潜在关系，第一端子连接到电位较高的端子中的任一端，并且第二端子 2连接到另一个电位较低。

6. 发明授权

US07442993B2 Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer 有权
标题翻译：通过弹性应变转移形成的超薄，高品质应变绝缘体上的绝缘体
公开(公告)号：US07442993B2
公开(公告)日：2008-10-28
申请号：US11293774
申请日：2005-12-02
申请人： Stephen W. Bedell , Anthony G. Domenicucci , Keith E. Fogel , Effendi Leobandung , Devendra K. Sadana
发明人： Stephen W. Bedell , Anthony G. Domenicucci , Keith E. Fogel , Effendi Leobandung , Devendra K. Sadana
IPC分类号： H01L31/392
CPC分类号： H01L29/78696 , H01L21/0237 , H01L21/02439 , H01L21/02488 , H01L21/02502 , H01L21/02521 , H01L21/02667 , H01L21/02694 , H01L21/76251 , H01L29/7842
摘要： A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.
摘要翻译：提供了一种在绝缘层上形成包括第一应变半导体层的半导体结构的方法，其中第一应变半导体层相对较薄（小于约）并且具有低缺陷密度（堆垛层错和穿线缺陷）。本发明的方法开始于在包括位于绝缘层顶部的第一半导体层的结构上形成应力提供层，例如SiGe合金层。然后将应力提供层和第一半导体层图案化成至少一个岛，然后将含有至少一个岛的结构加热到使得应力转移从应力提供层到第一半导体层的温度。在应变转移之后，将应力提供层从结构上去除，以形成直接位于所述绝缘层顶部的第一应变半导体岛层。

7. 发明授权

US5359219A Silicon on insulator device comprising improved substrate doping 失效
标题翻译：绝缘体上硅器件包括改进的衬底掺杂
公开(公告)号：US5359219A
公开(公告)日：1994-10-25
申请号：US985976
申请日：1992-12-04
申请人： Jeong-Mo Hwang
发明人： Jeong-Mo Hwang
IPC分类号： H01L27/12 , H01L27/01 , H01L31/392
CPC分类号： H01L27/1203 , Y10S148/15
摘要： A silicon on insulator integrated circuit device is provided which comprises a substrate (10), a buried oxide layer (12), and an outer silicon layer (14). A buried p-layer (16) and a buried n-well region (26) are formed in order to position p-n junctions beneath n-channel and p-channel devices respectively formed in the outer silicon layer (14) outwardly from the p-layer (16) and (n)-well (26).
摘要翻译：提供了一种绝缘体上硅集成电路器件，其包括衬底（10），掩埋氧化层（12）和外硅层（14）。形成掩埋的p层（16）和掩埋的n阱区（26），以便将pn结位于p型结的下方，pn结在分别形成在外硅层（14）中的n沟道和p沟道器件的p- 层（16）和（n） - 孔（26）。

8. 发明授权

US07557411B2 Semi-conductor-on-insulator structure, semiconductor devices using the same and method of manufacturing the same 有权
标题翻译：半导体绝缘体上的结构，使用其的半导体器件及其制造方法
公开(公告)号：US07557411B2
公开(公告)日：2009-07-07
申请号：US11397866
申请日：2006-04-05
申请人： Takashi Noguchi , Hans S. Cho , Wenxu Xianyu , Huaxiang Yin , Xiaoxin Zhang
发明人： Takashi Noguchi , Hans S. Cho , Wenxu Xianyu , Huaxiang Yin , Xiaoxin Zhang
IPC分类号： H01L27/01 , H01L27/12 , H01L31/392
CPC分类号： H01L29/78687 , H01L29/66742 , H01L29/78603
摘要： Semiconductor-on-insulator (SOI) structures, semiconductor devices using the same and methods of manufacturing the same, and more particularly, to a structure with a single-crystalline (for example, germanium (x-Ge)) layer on an insulating layer, semiconductor devices using the same, and methods of manufacturing the same. The SOI structure may include a single-crystalline substrate formed of a first semiconductor material, a first insulating layer formed on the substrate and having at least one window exposing a portion of the substrate, a first epitaxial growth region formed on a surface of the substrate exposed by the window and formed of at least one of the first semiconductor material and a second semiconductor material, and a first single-crystalline layer formed on the first insulating layer and the first epitaxial growth region and formed of the second semiconductor material, and crystallized using a surface of the first epitaxial growth region as a seed layer for crystallization.
摘要翻译：绝缘体上半导体（SOI）结构，使用其的半导体器件及其制造方法，更具体地说，涉及在绝缘层上具有单晶（例如锗（x-Ge））层的结构，使用其的半导体器件及其制造方法。 SOI结构可以包括由第一半导体材料形成的单晶衬底，形成在衬底上的第一绝缘层，并且具有暴露衬底的一部分的至少一个窗口，形成在衬底表面上的第一外延生长区域由窗口露出并由第一半导体材料和第二半导体材料中的至少一个形成，以及形成在第一绝缘层和第一外延生长区上并由第二半导体材料形成的第一单晶层，并且晶化使用第一外延生长区域的表面作为晶种层进行结晶。

9. 发明授权

US07053294B2 Thin-film solar cell fabricated on a flexible metallic substrate 有权
标题翻译：在柔性金属基板上制造的薄膜太阳能电池
公开(公告)号：US07053294B2
公开(公告)日：2006-05-30
申请号：US10480880
申请日：2001-07-13
申请人： John R. Tuttle , Rommel Noufi , Falah S. Hasoon
发明人： John R. Tuttle , Rommel Noufi , Falah S. Hasoon
IPC分类号： H01L31/336 , H01L31/392
CPC分类号： H01L31/0322 , H01L31/03928 , Y02E10/541
摘要： A thin-film solar cell (10) is provided. The thin-film solar cell (10) comprises a flexible metallic substrate (12) having a first surface and a second surface. A back metal contact layer (16) is deposited on the first surface of the flexible metallic substrate (12). A semiconductor absorber layer (14) is deposited on the back metal contact. A photoactive film deposited on the semiconductor absorber layer (14) forms a heterojunction structure and a grid contact (24) deposited on the heterjunction structure. The flexible metal substrate (12) can be constructed of either aluminium or stainless steel. Furthermore, a method of constructing a solar cell is provided. The method comprises providing an aluminum substrate (12), depositing a semiconductor absorber layer (14) on the aluminum substrate (12), and insulating the aluminum substrate (12) from the semiconductor absorber layer (14) to inhibit reaction between the aluminum substrate (12) and the semiconductor absorber layer (14).
摘要翻译：提供薄膜太阳能电池（10）。薄膜太阳能电池（10）包括具有第一表面和第二表面的柔性金属基底（12）。在柔性金属基板（12）的第一表面上沉积背金属接触层（16）。半导体吸收层（14）沉积在背面金属触点上。沉积在半导体吸收层（14）上的光敏膜形成异相结构和沉积在异质结结构上的栅极接触（24）。柔性金属基底（12）可由铝或不锈钢构成。此外，提供了构造太阳能电池的方法。该方法包括提供铝基板（12），在铝基板（12）上沉积半导体吸收层（14），并将铝基板（12）与半导体吸收层（14）绝缘，以抑制铝基板（12）和半导体吸收层（14）。

10. 发明授权

US06933567B2 Substrate pump ESD protection for silicon-on-insulator technologies 有权
标题翻译：衬底泵ESD保护绝缘体上硅技术
公开(公告)号：US06933567B2
公开(公告)日：2005-08-23
申请号：US10146158
申请日：2002-05-15
申请人： Charvaka Duvvury , Sridhar Ramaswamy
发明人： Charvaka Duvvury , Sridhar Ramaswamy
IPC分类号： H01L23/62 , H01L27/02 , H01L31/392
CPC分类号： H01L27/0277
摘要： An electrostatic discharge (ESD) protection device formed in the semiconductor layer of a semiconductor-on-insulator device, wherein the semiconductor layer has first and second wells. A discharge circuit is formed in the first well, operable to discharge the ESD pulse to ground. A pump circuit is formed in the second well, operable to use a portion of an ESD pulse's voltage to pump current into the first well for allowing the discharge circuit to turn on uniformly. The discharge circuit has a plurality of body nodes to the first well. The pump circuit comprises an input pad for receiving a portion of the ESD pulse's voltage; an MOS transistor having source, gate and drain; a capacitor connected between the input pad and the gate, whereby a rising input voltage pulls the gate transiently high for pumping current into the first well; the source is connected to the body nodes of the discharge circuit, and the drain connected to the input pad.
摘要翻译：一种形成在绝缘体上半导体器件的半导体层中的静电放电（ESD）保护器件，其中半导体层具有第一和第二阱。在第一阱中形成放电电路，用于将ESD脉冲放电到地。泵电路形成在第二阱中，可操作以使用ESD脉冲的一部分电压将电流泵入第一阱，以允许放电电路均匀地导通。放电电路具有到第一阱的多个体节点。泵电路包括用于接收ESD脉冲电压的一部分的输入焊盘; 具有源极，栅极和漏极的MOS晶体管; 连接在输入焊盘和栅极之间的电容器，由此上升的输入电压将栅极瞬时拉高以将电流泵入第一阱; 源极连接到放电电路的主体节点，并且漏极连接到输入焊盘。

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