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91. 发明授权

US09411599B2 Operand fetching control as a function of branch confidence 有权
标题翻译：操作数获取控制作为分支置信度的函数
公开(公告)号：US09411599B2
公开(公告)日：2016-08-09
申请号：US12822379
申请日：2010-06-24
申请人： Christian Jacobi , Barry W. Krumm , Brian R. Prasky , Martin Recktenwald , Chung-Lung K. Shum , Charles F. Webb , Joshua M. Weinberg
发明人： Christian Jacobi , Barry W. Krumm , Brian R. Prasky , Martin Recktenwald , Chung-Lung K. Shum , Charles F. Webb , Joshua M. Weinberg
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/3806 , G06F9/3844 , G06F9/3857
摘要： Data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The method also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control, each memory access control specifying a manner of handling data fetching operations. The method further includes performing a memory access operation for the selected instruction based upon the mapping.
摘要翻译：数据操作数获取控制包括计算机处理器，其包括用于确定存储器存取操作的控制单元。控制单元被配置为执行方法。该方法包括：计算流水线中每个指令的求和权重值，求和作为分支不确定度的函数计算的求和权重值以及相对于流水线中的其他指令，指令驻留在流水线中的挂起。该方法还包括将尝试访问系统存储器的所选指令的求和权重值映射到存储器访问控制，每个存储器访问控制指定处理数据获取操作的方式。该方法还包括基于映射执行针对所选择的指令的存储器访问操作。

92. 发明授权

US09015419B2 Avoiding aborts due to associativity conflicts in a transactional environment 有权
标题翻译：避免由于交易环境中的联系冲突而中断
公开(公告)号：US09015419B2
公开(公告)日：2015-04-21
申请号：US13524378
申请日：2012-06-15
申请人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi
发明人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi
IPC分类号： G06F12/00 , G06F9/46 , G06F12/08
CPC分类号： G06F12/0804 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/467
摘要： Embodiments relate to a transactional read footprint after a cache line eviction. An aspect includes executing one or more read instructions in an active transaction. A cross invalidate (XI) request for a target cache line is received, and it is determined if the target cache line is part of a congruence class in a local cache. It is further determined whether an extension flag associated with the congruence class is set. The extension flag is used to indicate that cache lines of the congruence class associated with the active transaction have been replaced based only on being least recently used and that the target cache line is not in the cache. Execution of the active transaction continues based on determining that the extension flag is not set. Execution of the active transaction is aborted based on determining that the extension flag is set.
摘要翻译：实施例涉及缓存线驱逐之后的事务读取占用空间。一个方面包括在活动事务中执行一个或多个读取指令。接收对目标高速缓存行的交叉无效（XI）请求，并且确定目标高速缓存行是否是本地高速缓存中的同余类的一部分。进一步确定是否设置与同余类相关联的扩展标志。扩展标志用于指示仅基于最近最少使用的并且目标高速缓存行不在高速缓存中，与活动事务相关联的一致类的高速缓存行已被替换。基于确定扩展标志未设置，继续执行活动事务。基于确定扩展标志被设置，中止活动事务的执行。

93. 发明授权

US08645669B2 Cracking destructively overlapping operands in variable length instructions 有权
标题翻译：以可变长度指令破坏性地重叠操作数
公开(公告)号：US08645669B2
公开(公告)日：2014-02-04
申请号：US12774299
申请日：2010-05-05
申请人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi
发明人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30043 , G06F9/30149 , G06F9/3016
摘要： A method, information processing system, and computer program product manage computer executable instructions. At least one machine instruction for execution is received. The at least one machine instruction is analyzed. The machine instruction is identified as a predefined instruction for storing a variable length first operand in a memory location. Responsive to this identification and based on fields of the machine instruction, a relative location of a variable length second operand of the instruction with location of the first operand is determined. Responsive to the relative location having the predefined relationship, a first cracking operation is performed. The first cracking operation cracks the instruction into a first set of micro-ops (Uops) to be executed in parallel. The first set of Uops is for storing a first plurality of first blocks in the first operand. Each of said first block to be stored are identical. The first set Uops are executed.
摘要翻译：一种方法，信息处理系统和计算机程序产品管理计算机可执行指令。接收至少一个用于执行的机器指令。分析至少一个机器指令。机器指令被识别为用于将可变长度的第一操作数存储在存储器位置中的预定义指令。响应于该识别并且基于机器指令的字段，确定指令的可变长度第二操作数与第一操作数的位置的相对位置。响应于具有预定关系的相对位置，执行第一裂解操作。第一个破解操作将指令分解为并行执行的第一组微操作（Uop）。第一组Uops用于在第一操作数中存储第一多个第一块。要存储的所述第一块的每个都是相同的。第一组Uops被执行。

94. 发明申请

US20130339650A1 PREFETCH ADDRESS TRANSLATION USING PREFETCH BUFFER 有权
标题翻译：使用PREFETCH BUFFER的前缀地址翻译
公开(公告)号：US20130339650A1
公开(公告)日：2013-12-19
申请号：US13523919
申请日：2012-06-15
申请人： Khary J. Alexander , Ilia Averbouch , Ariel J. Birnbaum , Jonathan T. Hsieh , Christian Jacobi , Shmuel Paycher , Chung-Lung K. Shum
发明人： Khary J. Alexander , Ilia Averbouch , Ariel J. Birnbaum , Jonathan T. Hsieh , Christian Jacobi , Shmuel Paycher , Chung-Lung K. Shum
IPC分类号： G06F12/10
CPC分类号： G06F12/0862 , G06F12/1009
摘要： Embodiments relate to prefetch address translation in a computer processor. An aspect includes issuing, by prefetch logic, a prefetch request comprising a virtual page address. Another aspect includes, based on the prefetch request missing the TLB and the address translation logic of the processor being busy performing a current translation request, comparing a page of the prefetch request to a page of the current translation request. Yet another aspect includes, based on the page of the prefetch request matching the page of the current translation request, storing the prefetch request in a prefetch buffer.
摘要翻译：实施例涉及计算机处理器中的预取地址转换。一方面包括通过预取逻辑发出包括虚拟页面地址的预取请求。另一方面包括：基于预取请求，丢失TLB，处理器的地址转换逻辑正在执行当前转换请求，将预取请求的页面与当前转换请求的页面进行比较。另一方面包括：基于与当前转换请求的页面匹配的预取请求的页面，将预取请求存储在预取缓冲器中。

95. 发明申请

US20130339615A1 MANAGING TRANSACTIONAL AND NON-TRANSACTIONAL STORE OBSERVABILITY 有权
标题翻译：管理交易和非交易商店的可观察性
公开(公告)号：US20130339615A1
公开(公告)日：2013-12-19
申请号：US13524386
申请日：2012-06-15
申请人： Khary J. Alexander , Christian Jacobi , Hans-Werner Tast , Patrick M. West
发明人： Khary J. Alexander , Christian Jacobi , Hans-Werner Tast , Patrick M. West
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F9/467 , G06F11/1474 , G06F12/0828
摘要： Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional.
摘要翻译：实施例涉及控制事务和非交易存储的可观察性。一方面包括接收一个或多个存储指令。一个或多个存储指令在活动事务中启动并且包括存储数据。活动事务有效地延迟将存储提交到存储器，直到成功完成活动事务。存储数据存储在本地存储缓冲器中，导致本地存储缓冲器从第一状态到第二状态的改变。接收到有效事务终止的信号。如果活动事务已经异常终止，则：如果存储数据由事务存储指令存储，则本地存储缓冲区被恢复到第一状态，并且如果存储指令是非事务性的则将其传播到共享高速缓存。

96. 发明授权

US08229989B2 Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units 有权
标题翻译：用于控制单指令多数据（SIMD）浮点单元中舍入模式的方法
公开(公告)号：US08229989B2
公开(公告)日：2012-07-24
申请号：US12238500
申请日：2008-09-26
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译：公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的方法。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

97. 发明授权

US08166085B2 Reducing the latency of sum-addressed shifters 失效
标题翻译：减少和寻址移位器的延迟
公开(公告)号：US08166085B2
公开(公告)日：2012-04-24
申请号：US12105726
申请日：2008-04-18
申请人： Sang Hoo Dhong , Christian Jacobi , Silvia Melitta Mueller , Hiroo Nishikawa , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Christian Jacobi , Silvia Melitta Mueller , Hiroo Nishikawa , Hwa-Joon Oh
IPC分类号： G06F15/00 , G06F7/38
CPC分类号： G06F5/012
摘要： The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.
摘要翻译：本发明提供了作为多个数字的函数的移位量的计算。至少一个解码器和至少一个加法器并联耦合。移位器被配置为计算多个移位级中的值，并且其中移位量的位组可用于影响多个移位级中的至少一个，从而减少处理时间。

98. 发明申请

US20110276764A1 CRACKING DESTRUCTIVELY OVERLAPPING OPERANDS IN VARIABLE LENGTH INSTRUCTIONS 有权
标题翻译：在可变长度指令中打破破坏性重复操作
公开(公告)号：US20110276764A1
公开(公告)日：2011-11-10
申请号：US12774299
申请日：2010-05-05
申请人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi
发明人： Khary J. Alexander , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi
IPC分类号： G06F9/30 , G06F12/08 , G06F9/312
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30043 , G06F9/30149 , G06F9/3016
摘要： A method, information processing system, and computer program product manage computer executable instructions. At least one machine instruction for execution is received. The at least one machine instruction is analyzed. The machine instruction is identified as a predefined instruction for storing a variable length first operand in a memory location. Responsive to this identification and based on fields of the machine instruction, a relative location of a variable length second operand of the instruction with location of the first operand is determined. Responsive to the relative location having the predefined relationship, a first cracking operation is performed. The first cracking operation cracks the instruction into a first set of micro-ops (Uops) to be executed in parallel. The second set of Uops is for storing a first plurality of first blocks in the first operand. Each of said first block to be stored are identical. The first set Uops are executed.
摘要翻译：一种方法，信息处理系统和计算机程序产品管理计算机可执行指令。接收至少一个用于执行的机器指令。分析至少一个机器指令。机器指令被识别为用于将可变长度的第一操作数存储在存储器位置中的预定义指令。响应于该识别并且基于机器指令的字段，确定指令的可变长度第二操作数与第一操作数的位置的相对位置。响应于具有预定关系的相对位置，执行第一裂解操作。第一个破解操作将指令分解为并行执行的第一组微操作（Uop）。第二组Uop用于在第一操作数中存储第一多个第一块。要存储的所述第一块的每个都是相同的。第一组Uops被执行。

99. 发明申请

US20110154298A1 COLLECTING COMPUTER PROCESSOR INSTRUMENTATION DATA 失效
标题翻译：收集计算机处理器仪表数据
公开(公告)号：US20110154298A1
公开(公告)日：2011-06-23
申请号：US12645687
申请日：2009-12-23
申请人： Gregory W. Alexander , Jane Bartik , Michael Billeci , David Hutton , Christian Jacobi , Jang-Soo Lee , Eric Schwarz , Chung-Lung Shum , Phil C. Yeh
发明人： Gregory W. Alexander , Jane Bartik , Michael Billeci , David Hutton , Christian Jacobi , Jang-Soo Lee , Eric Schwarz , Chung-Lung Shum , Phil C. Yeh
IPC分类号： G06F9/44
CPC分类号： G06F11/348 , G06F11/3409
摘要： A system and method for collecting instrumentation data in a processor with a pipelined instruction execution stages arranged in an out-of-order execution architecture. One instruction group in a Global Completion Table is marked as a tagged group. Instrumentation data is stored for processing stages processing instructions associated with the tagged group. Sample signal pulses trigger a determination of whether the tagged group is the next-to-complete instruction group. When the sample pulse occurs at a time when the tagged group is the next-to-complete group, the instrumentation data is written as an output. Instrumentation data present during sample pulses that occur when the tagged group is not the next-to-complete group is optionally discarded. Sample pulses are generated at a rate equal to the desired sample rate times the number of groups in the global completion table to better ensure occurrence of a next-to-complete tagged group.
摘要翻译：一种用处理器收集仪器数据的系统和方法，其中流水线指令执行阶段以无序执行体系结构排列。全局完成表中的一个指令组被标记为标记组。存储用于与标记组相关联的处理阶段处理指令的仪表数据。采样信号脉冲触发确定标记的组是否是下一个完成指令组。当标记的组是下一个完成组时，当采样脉冲发生时，仪表数据被写为输出。当标记的组不是下一个到完整的组时发生的采样脉冲期间存在的仪器数据被任选地丢弃。以等于所需采样率的速率乘以采样脉冲乘以全局完成表中的组数，以更好地确保下一个到完整标记组的发生。

100. 发明授权

US07949968B2 Method and system for building binary decision diagrams optimally for nodes in a netlist graph using don't-caring 失效
标题翻译：使用不关心的方法和系统来最佳地构建网表中节点的二进制决策图
公开(公告)号：US07949968B2
公开(公告)日：2011-05-24
申请号：US11683495
申请日：2007-03-08
申请人： Christian Jacobi , Udo Krautz , Viresh Paruthi , Matthias Pflanz , Kai O. Weber
发明人： Christian Jacobi , Udo Krautz , Viresh Paruthi , Matthias Pflanz , Kai O. Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： An improved method, system and computer-readable medium for constructing binary decision diagrams for a netlist graph is disclosed. The method comprises traversing a netlist graph in a depth-first manner. At least one binary decision diagram is built for one input of a node of the netlist graph using a binary decision diagram for the other input of that node as a don't-care condition.
摘要翻译：公开了一种用于构建网表的二进制决策图的改进方法，系统和计算机可读介质。该方法包括以深度优先方式遍历网表。使用用于该节点的另一输入的二进制决策图作为不关心条件，为网表图形的节点的一个输入构建至少一个二进制决策图。

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