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91. 发明申请

US20100235576A1 Handling Castout Cache Lines In A Victim Cache 失效
标题翻译：在受害者缓存中处理Castout缓存行
公开(公告)号：US20100235576A1
公开(公告)日：2010-09-16
申请号：US12336048
申请日：2008-12-16
申请人： Guy L. Guthrie , Alvan W. Ng , Michael S. Siegel , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , Alvan W. Ng , Michael S. Siegel , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/127 , G06F12/0811 , G06F12/0862
摘要： A victim cache memory includes a cache array, a cache directory of contents of the cache array, and a cache controller that controls operation of the victim cache memory. The cache controller, responsive to receiving a castout command identifying a victim cache line castout from another cache memory, causes the victim cache line to be held in the cache array. If the other cache memory is a higher level cache in the cache hierarchy of the processor core, the cache controller marks the victim cache line in the cache directory so that it is less likely to be evicted by a replacement policy of the victim cache, and otherwise, marks the victim cache line in the cache directory so that it is more likely to be evicted by the replacement policy of the victim cache.
摘要翻译：受害者缓存存储器包括缓存阵列，高速缓存阵列的内容的高速缓存目录以及控制受害者缓存存储器的操作的高速缓存控制器。高速缓存控制器响应于从另一高速缓冲存储器接收识别受害者高速缓存线路突发的丢弃命令，使受害者高速缓存行保持在高速缓存阵列中。如果其他高速缓冲存储器是处理器核心的高速缓存层级中的较高级缓存，则高速缓存控制器将高速缓存目录中的受害者高速缓存行标记为不太可能被受害缓存的替换策略驱逐，否则，将缓存目录中的受害者缓存行标记为更有可能被受害者缓存的替换策略驱逐。

92. 发明申请

US20100153647A1 Cache-To-Cache Cast-In 失效
标题翻译：缓存到缓存注入
公开(公告)号：US20100153647A1
公开(公告)日：2010-06-17
申请号：US12335975
申请日：2008-12-16
申请人： Guy L. Guthrie , Alvan W. Ng , Michael S. Siegel , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , Alvan W. Ng , Michael S. Siegel , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0804 , G06F12/0831 , G06F12/0862
摘要： A data processing system includes a first processing unit and a second processing unit coupled by an interconnect fabric. The first processing unit has a first processor core and associated first upper and first lower level caches, and the second processing unit has a second processor core and associated second upper and lower level caches. In response to a data request, a victim cache line is selected for castout from the first lower level cache. The first processing unit issues on the interconnect fabric a lateral castout (LCO) command that identifies the victim cache line to be castout from the first lower level cache and indicates that a lower level cache is an intended destination. In response to a coherence response indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.
摘要翻译：数据处理系统包括由互连结构耦合的第一处理单元和第二处理单元。第一处理单元具有第一处理器核心和相关联的第一上部和第一下层高速缓存，并且第二处理单元具有第二处理器核心和相关联的第二上部和下部高速缓存。响应于数据请求，选择受害者高速缓存行用于从第一较低级别缓存进行舍弃。第一处理单元在互连结构上发出横向聚合（LCO）命令，该命令标识要从第一较低级缓存中抛出的受害缓存行，并且指示较低级缓存是预期目的地。响应于指示LCO命令的成功的一致性响应，从第一低级缓存中删除受害者高速缓存行并保存在第二较低级高速缓存中。

93. 发明授权

US07716428B2 Data processing system, cache system and method for reducing imprecise invalid coherency states 失效
标题翻译：数据处理系统，缓存系统和减少不精确无效一致性状态的方法
公开(公告)号：US07716428B2
公开(公告)日：2010-05-11
申请号：US11364774
申请日：2006-02-28
申请人： Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data. In response to snooping a data-invalid state update request, the first cache memory updates the coherency state field from the first data-invalid coherency state to a second data-invalid coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, and that a memory block associated with the address tag is likely cached within the first coherency domain.
摘要翻译：缓存相干数据处理系统至少包括第一和第二相干域。在数据处理系统的第一相关域内的第一高速缓冲存储器中，将与存储位置和地址标签相关联的一致性状态字段设置为指示地址标签有效的第一数据无效一致性状态，存储位置不包含有效数据。响应于窥探数据无效状态更新请求，第一缓存存储器将相关性状态字段从第一数据无效一致性状态更新为指示地址标签有效的第二数据无效一致性状态，存储位置不包含有效数据，并且与地址标签相关联的存储器块可能被缓存在第一个相干域内。

94. 发明授权

US07689771B2 Coherency management of castouts 有权
标题翻译： castouts的一致性管理
公开(公告)号：US07689771B2
公开(公告)日：2010-03-30
申请号：US11532981
申请日：2006-09-19
申请人： James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0804 , G06F12/0815
摘要： According to one embodiment, a method of coherency management in a data processing system includes holding a cache line in an upper level cache memory in an exclusive ownership coherency state and thereafter removing the cache line from the upper level cache memory and transmitting a castout request for the cache line from the upper level cache memory to a lower level cache memory. The castout request includes an indication of a shared ownership coherency state. In response to the castout request, the cache line is placed in the lower level cache memory in a coherency state determined in accordance with the castout request.
摘要翻译：根据一个实施例，一种数据处理系统中的一致性管理方法包括：将高速缓存行以独占所有权一致性状态保存在上级高速缓冲存储器中，之后从高级缓存存储器中移除高速缓存行，从高级缓存存储器到高级缓存的高速缓存行。丢弃请求包括共享所有权一致性状态的指示。响应于抛出请求，高速缓存行以根据转储请求确定的一致性状态被放置在较低级高速缓冲存储器中。

95. 发明申请

US20090198971A1 Heterogeneous Processing Elements 有权
标题翻译：异构处理元件
公开(公告)号：US20090198971A1
公开(公告)日：2009-08-06
申请号：US12024220
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Charles F. Marino , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Charles F. Marino , William J. Starke
IPC分类号： G06F9/30
CPC分类号： G06F13/12
摘要： A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt handling, and exception processing, for example. The heterogeneous processing element model puts special purpose processing elements on the same playing field as processors, from a programming perspective, operating system perspective, power perspective, as the processors. The operating system can get work to a security engine, for example, in the same way it does to a processor.
摘要翻译：提供异构处理元件模型，其中I / O设备看起来像处理器一样操作。为了像处理器一样处理I / O处理元件或其他专用处理元件，必须遵循一些规则并具有处理器的某些特性，例如地址转换，安全性，中断处理和异常处理，用于例。异构处理元素模型将特殊处理元素放在与处理器相同的竞争环境中，从编程角度，操作系统的角度，功率视角，作为处理器。操作系统可以使用安全引擎，例如，与处理器相同。

96. 发明授权

US07523268B2 Reducing number of rejected snoop requests by extending time to respond to snoop request 有权
标题翻译：通过延长响应窥探请求的时间来减少被拒绝的窥探请求数
公开(公告)号：US07523268B2
公开(公告)日：2009-04-21
申请号：US12114790
申请日：2008-05-04
申请人： Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon entering a bottom latch in the pipeline. The stall/reorder unit is not informed as to whether the dispatched snoop request is accepted by an arbitration mechanism for several clock cycles after the dispatch occurred. A copy of the dispatched snoop request is stored in a top latch in an overrun pipeline of latches in the first unit upon dispatching the snoop request. By maintaining information about the snoop request, the snoop request may be dispatched again to the selector in case the dispatched snoop request was rejected thereby increasing the chance that the snoop request will ultimately be accepted.
摘要翻译：用于减少拒绝的窥探请求数量的缓存，系统和方法。如果失速/重新排序单元未满，则在失速/重新排序单元中的锁存器管线中的第一可用锁存器中输入进入的窥探请求。输入的窥探请求在进入管道中的底部闩锁时被调度到选择器。失速/重新排序单元不知道发送后发送的几个时钟周期是否由仲裁机制接受发送的窥探请求。调度窥探请求的副本在调度窥探请求时被存储在第一单元中的锁存器的溢出管道中的顶部锁存器中。通过维护关于窥探请求的信息，可以在被发送的窥探请求被拒绝的情况下再次发送到选择器的窥探请求，从而增加窥探请求将最终被接受的机会。

97. 发明授权

US07475195B2 Data processing system, cache system and method for actively scrubbing a domain indication 失效
标题翻译：数据处理系统，缓存系统和方法，用于主动清理域指示
公开(公告)号：US07475195B2
公开(公告)日：2009-01-06
申请号：US11136651
申请日：2005-05-24
申请人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F12/0822
摘要： Scrubbing logic in a local coherency domain issues to at least one cache hierarchy in a remote coherency domain a domain reset request that forces invalidation of any cached copy of a target memory block then held in said remote coherency domain. A coherency response to said domain reset request is received. In response to said coherency response indicating that said target memory block is not cached in said remote coherency domain, a domain indication of said local coherency domain is updated to indicate that said target memory block is cached, if at all, only within said local coherency domain.
摘要翻译：本地一致性域中的擦除逻辑向远程一致性域中的至少一个高速缓存层次结构发出一个域重置请求，该请求强制所保存在所述远程一致性域中的目标存储器块的任何高速缓存副本的无效。接收到对所述域重置请求的一致性响应。响应于所述相关性响应指示所述目标存储器块未被高速缓存在所述远程一致性域中，所述本地一致性域的域指示被更新以指示所述目标存储器块被缓存，如果完全只在所述局部一致性内域。

98. 发明申请

US20080301531A1 FAULT TOLERANT ENCODING OF DIRECTORY STATES FOR STUCK BITS 有权
标题翻译：对于保险单的目录状态的容错编码
公开(公告)号：US20080301531A1
公开(公告)日：2008-12-04
申请号：US12189808
申请日：2008-08-12
申请人： Robert H. Bell, JR. , Guy L. Guthrie , William J. Starke
发明人： Robert H. Bell, JR. , Guy L. Guthrie , William J. Starke
IPC分类号： G11C29/04 , G06F11/08
CPC分类号： G11C29/832 , G06F11/1064
摘要： A method of handling a stuck bit in a directory of a cache memory, by defining multiple binary encodings to indicate a defective cache state, detecting an error in a tag stored in a member of the directory (wherein the tag at least includes an address field, a state field and an error-correction field), determining that the error is associated with a stuck bit of the directory member, and writing new state information to the directory member which is selected from one of the binary encodings based on a field location of the stuck bit within the directory member. The multiple binary encodings may include a first binary encoding when the stuck bit is in the address field, a second binary encoding when the stuck bit is in the state field, and a third binary encoding when the stuck bit is in the error-correction field. The new state information may also further be selected based on the value of the stuck bit, e.g., a state bit corresponding to the stuck bit is assigned a bit value from the new state information which matches the value of the stuck bit.
摘要翻译：一种通过定义多个二进制编码来指示缺陷高速缓存状态来处理高速缓冲存储器的目录中的卡住位的方法，检测存储在目录成员中的标签中的错误（其中标签至少包括地址字段，状态字段和纠错字段），确定错误与目录成员的卡住位相关联，并且基于字段位置将新状态信息写入从二进制编码之一中选择的目录成员的目录成员中的卡住位。多个二进制编码可以包括当卡住位在地址字段中时的第一二进制编码，当卡位位于状态字段时的第二二进制编码，以及当卡位位于错误校正字段中时的第三二进制编码。还可以基于卡住位的值进一步选择新的状态信息，例如，对应于该卡住位的状态位从与该卡位的值匹配的新状态信息中分配一位值。

99. 发明申请

US20080181244A1 DATA PROCESSING SYSTEM, METHOD AND INTERCONNECT FABRIC FOR IMPROVED COMMUNICATION IN A DATA PROCESSING SYSTEM 有权
标题翻译：数据处理系统，用于数据处理系统中改进通信的方法和互连织物
公开(公告)号：US20080181244A1
公开(公告)日：2008-07-31
申请号：US12060751
申请日：2008-04-01
申请人： LEO J. CLARK , James S. Fields , Guy L. Guthrie , William J. Starke
发明人： LEO J. CLARK , James S. Fields , Guy L. Guthrie , William J. Starke
IPC分类号： H04L12/56
CPC分类号： G06F15/16
摘要： A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts operations received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units.
摘要翻译：数据处理系统包括多个处理单元，每个处理单元各自具有与多个处理单元中的多个其他处理单元中的每一个相对的点对点通信链路，但是比所有多个处理单元少。多个处理单元中的每一个包括互连逻辑，耦合到该处理单元的每个点对点通信链路，其将从多个处理单元中的多个其中一个处理单元接收的操作广播到多个处理单元中的一个或多个处理单位。

100. 发明授权

US07237070B2 Cache memory, processing unit, data processing system and method for assuming a selected invalid coherency state based upon a request source 有权
标题翻译：高速缓冲存储器，处理单元，数据处理系统和方法，用于基于请求源假设所选择的无效一致性状态
公开(公告)号：US07237070B2
公开(公告)日：2007-06-26
申请号：US11109085
申请日：2005-04-19
申请人： Guy L. Guthrie , Aaron C. Sawdey , William J. Starke , Derek Edward Williams
发明人： Guy L. Guthrie , Aaron C. Sawdey , William J. Starke , Derek Edward Williams
IPC分类号： G06F13/00
CPC分类号： G06F12/0811 , G06F12/0813 , G06F12/0831
摘要： At a first cache memory affiliated with a first processor core, an exclusive memory access operation is received via an interconnect fabric coupling the first cache memory to second and third cache memories respectively affiliated with second and third processor cores. The exclusive memory access operation specifies a target address. In response to receipt of the exclusive memory access operation, the first cache memory detects presence or absence of a source indication indicating that the exclusive memory access operation originated from the second cache memory to which the first cache memory is coupled by a private communication network to which the third cache memory is not coupled. In response to detecting presence of the source indication, a coherency state field of the first cache memory that is associated with the target address is updated to a first data-invalid state. In response to detecting absence of the source indication, the coherency state field of the first cache memory is updated to a different second data-invalid state.
摘要翻译：在与第一处理器核心相关联的第一高速缓冲存储器处，通过将第一高速缓冲存储器耦合到分别隶属于第二和第三处理器核的第二和第三高速缓冲存储器的互连结构接收独占存储器存取操作。独占内存访问操作指定目标地址。响应于独占存储器访问操作的接收，第一高速缓存存储器检测是否存在指示来自第一高速缓存存储器的专用存储器访问操作的源指示由第一高速缓存存储器通过专用通信网络耦合到第三缓存存储器未被耦合。响应于检测到源指示的存在，与目标地址相关联的第一高速缓冲存储器的一致性状态字段被更新为第一数据无效状态。响应于检测到不存在源指示，将第一高速缓冲存储器的一致性状态字段更新为不同的第二数据无效状态。

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