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1. 发明授权

US08161493B2 Weighted-region cycle accounting for multi-threaded processor cores 失效
标题翻译：加权区域循环计算多线程处理器内核
公开(公告)号：US08161493B2
公开(公告)日：2012-04-17
申请号：US12173771
申请日：2008-07-15
申请人： Michael S. Floyd , Steven R. Kunkel , Aaron C. Sawdey , Philip L. Vitale
发明人： Michael S. Floyd , Steven R. Kunkel , Aaron C. Sawdey , Philip L. Vitale
IPC分类号： G06F9/45 , G06F9/46
CPC分类号： G06F9/3851 , G06F11/3409 , G06F11/3466 , G06F2201/88
摘要： An aspect of the present invention improves the accuracy of measuring processor utilization of multi-threaded cores by providing a calibration facility that derives utilization in the context of the overall dynamic operating state of the core by assigning weights to idle threads and assigning weights to run threads, depending on the status of the core. From previous chip designs it has been established in a Simultaneous Multi Thread (SMT) core that not all idle cycles in a hardware thread can be equally converted into useful work. Competition for core resources reduces the conversion efficiency of one thread's idle cycles when any other thread is running on the same core.
摘要翻译：本发明的一个方面通过提供一种校准设备来提高测量多线程核心处理器利用率的准确性，该校准设备通过向空闲线程分配权重并为运行线程分配权重而在核心的整体动态操作状态的上下文中获得利用，取决于核心的状态。从先前的芯片设计，已经建立在同步多线程（SMT）核心中，并非硬件线程中的所有空闲周期都可以平等地转换为有用的工作。核心资源的竞争降低了一个线程在同一个核心上运行的一个线程的空闲周期的转换效率。

2. 发明申请

US20100287561A1 DEVICE FOR AND METHOD OF WEIGHTED-REGION CYCLE ACCOUNTING FOR MULTI-THREADED PROCESSOR CORES 失效
标题翻译：用于多线加工器的加权区域循环会计的装置和方法
公开(公告)号：US20100287561A1
公开(公告)日：2010-11-11
申请号：US12173771
申请日：2008-07-15
申请人： Michael S. Floyd , Steven R. Kunkel , Aaron C. Sawdey , Philip L. Vitale
发明人： Michael S. Floyd , Steven R. Kunkel , Aaron C. Sawdey , Philip L. Vitale
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F11/3409 , G06F11/3466 , G06F2201/88
摘要： An aspect of the present invention improves the accuracy of measuring processor utilization of multi-threaded cores by providing a calibration facility that derives utilization in the context of the overall dynamic operating state of the core by assigning weights to idle threads and assigning weights to run threads, depending on the status of the core. From previous chip designs it has been established in a Simultaneous Multi Thread (SMT) core that not all idle cycles in a hardware thread can be equally converted into useful work. Competition for core resources reduces the conversion efficiency of one thread's idle cycles when any other thread is running on the same core.
摘要翻译：本发明的一个方面通过提供一种校准设备来提高测量多线程核心处理器利用率的准确性，该校准设备通过向空闲线程分配权重并为运行线程分配权重而在核心的整体动态操作状态的上下文中获得利用，取决于核心的状态。从先前的芯片设计，已经建立在同步多线程（SMT）核心中，并非硬件线程中的所有空闲周期都可以平等地转换为有用的工作。核心资源的竞争降低了一个线程在同一个核心上运行的一个线程的空闲周期的转换效率。

3. 发明授权

US07237070B2 Cache memory, processing unit, data processing system and method for assuming a selected invalid coherency state based upon a request source 有权
标题翻译：高速缓冲存储器，处理单元，数据处理系统和方法，用于基于请求源假设所选择的无效一致性状态
公开(公告)号：US07237070B2
公开(公告)日：2007-06-26
申请号：US11109085
申请日：2005-04-19
申请人： Guy L. Guthrie , Aaron C. Sawdey , William J. Starke , Derek Edward Williams
发明人： Guy L. Guthrie , Aaron C. Sawdey , William J. Starke , Derek Edward Williams
IPC分类号： G06F13/00
CPC分类号： G06F12/0811 , G06F12/0813 , G06F12/0831
摘要： At a first cache memory affiliated with a first processor core, an exclusive memory access operation is received via an interconnect fabric coupling the first cache memory to second and third cache memories respectively affiliated with second and third processor cores. The exclusive memory access operation specifies a target address. In response to receipt of the exclusive memory access operation, the first cache memory detects presence or absence of a source indication indicating that the exclusive memory access operation originated from the second cache memory to which the first cache memory is coupled by a private communication network to which the third cache memory is not coupled. In response to detecting presence of the source indication, a coherency state field of the first cache memory that is associated with the target address is updated to a first data-invalid state. In response to detecting absence of the source indication, the coherency state field of the first cache memory is updated to a different second data-invalid state.
摘要翻译：在与第一处理器核心相关联的第一高速缓冲存储器处，通过将第一高速缓冲存储器耦合到分别隶属于第二和第三处理器核的第二和第三高速缓冲存储器的互连结构接收独占存储器存取操作。独占内存访问操作指定目标地址。响应于独占存储器访问操作的接收，第一高速缓存存储器检测是否存在指示来自第一高速缓存存储器的专用存储器访问操作的源指示由第一高速缓存存储器通过专用通信网络耦合到第三缓存存储器未被耦合。响应于检测到源指示的存在，与目标地址相关联的第一高速缓冲存储器的一致性状态字段被更新为第一数据无效状态。响应于检测到不存在源指示，将第一高速缓冲存储器的一致性状态字段更新为不同的第二数据无效状态。

4. 发明授权

US08788757B2 Dynamic inclusive policy in a hybrid cache hierarchy using hit rate 失效
标题翻译：使用命中率的混合缓存层次结构中的动态包容性策略
公开(公告)号：US08788757B2
公开(公告)日：2014-07-22
申请号：US13315381
申请日：2011-12-09
申请人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F12/0888 , G06F12/0897 , G06F12/126
摘要： A mechanism is provided for dynamic cache allocation using a cache hit rate. A first cache hit rate is monitored in a first subset utilizing a first allocation policy of N sets of a lower level cache. A second cache hit rate is also monitored in a second subset utilizing a second allocation policy different from the first allocation policy of the N sets of the lower level cache. A periodic comparison of the first cache hit rate to the second cache hit rate is made to identify a third allocation policy for a third subset of the N-sets of the lower level cache. The third allocation policy for the third subset is then periodically adjusted to at least one of the first allocation policy or the second allocation policy based on the comparison of the first cache hit rate to the second cache hit rate.
摘要翻译：提供了一种用于使用高速缓存命中率进行动态高速缓存分配的机制。使用N组较低级高速缓存的第一分配策略，在第一子集中监视第一高速缓存命中率。利用与下一级高速缓存的N组的第一分配策略不同的第二分配策略，也在第二子集中监视第二高速缓存命中率。进行第一高速缓存命中率与第二高速缓存命中率的周期性比较，以识别下级高速缓存的N组的第三子集的第三分配策略。然后，基于第一高速缓存命中率与第二高速缓存命中率的比较，将第三子集的第三分配策略周期性地调整为第一分配策略或第二分配策略中的至少一个。

5. 发明申请

US20130151780A1 Weighted History Allocation Predictor Algorithm in a Hybrid Cache 有权
公开(公告)号：US20130151780A1
公开(公告)日：2013-06-13
申请号：US13611614
申请日：2012-09-12
申请人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/122 , G06F12/0897 , G06F12/121
摘要： A mechanism is provided for weighted history allocation prediction. For each member in a plurality of members in a lower level cache, an associated reference counter is initialized to an initial value based on an operation type that caused data to be allocated to a member location of the member. For each access to the member in the lower level cache, the associated reference counter is incremented. Responsive to a new allocation of data to the lower level cache and responsive to the new allocation of data requiring the victimization of another member in the lower level cache, a member of the lower level cache is identified that has a lowest reference count value in its associated reference counter. The member with the lowest reference count value in its associated reference counter is then evicted.

6. 发明申请

US20130151777A1 Dynamic Inclusive Policy in a Hybrid Cache Hierarchy Using Hit Rate 失效
标题翻译：使用命中率的混合缓存层次结构中的动态包容性策略
公开(公告)号：US20130151777A1
公开(公告)日：2013-06-13
申请号：US13315381
申请日：2011-12-09
申请人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0897 , G06F12/126
摘要： A mechanism is provided for dynamic cache allocation using a cache hit rate. A first cache hit rate is monitored in a first subset utilizing a first allocation policy of N sets of a lower level cache. A second cache hit rate is also monitored in a second subset utilizing a second allocation policy different from the first allocation policy of the N sets of the lower level cache. A periodic comparison of the first cache hit rate to the second cache hit rate is made to identify a third allocation policy for a third subset of the N-sets of the lower level cache. The third allocation policy for the third subset is then periodically adjusted to at least one of the first allocation policy or the second allocation policy based on the comparison of the first cache hit rate to the second cache hit rate.
摘要翻译：提供了一种用于使用高速缓存命中率进行动态高速缓存分配的机制。使用N组较低级高速缓存的第一分配策略，在第一子集中监视第一高速缓存命中率。利用与下一级高速缓存的N组的第一分配策略不同的第二分配策略，也在第二子集中监视第二高速缓存命中率。进行第一高速缓存命中率与第二高速缓存命中率的周期性比较，以识别下级高速缓存的N组的第三子集的第三分配策略。然后，基于第一高速缓存命中率与第二高速缓存命中率的比较，将第三子集的第三分配策略周期性地调整为第一分配策略或第二分配策略中的至少一个。

7. 发明授权

US08930625B2 Weighted history allocation predictor algorithm in a hybrid cache 有权
标题翻译：混合高速缓存中加权历史分配预测算法
公开(公告)号：US08930625B2
公开(公告)日：2015-01-06
申请号：US13611614
申请日：2012-09-12
申请人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/122 , G06F12/0897 , G06F12/121
摘要： A mechanism is provided for weighted history allocation prediction. For each member in a plurality of members in a lower level cache, an associated reference counter is initialized to an initial value based on an operation type that caused data to be allocated to a member location of the member. For each access to the member in the lower level cache, the associated reference counter is incremented. Responsive to a new allocation of data to the lower level cache and responsive to the new allocation of data requiring the victimization of another member in the lower level cache, a member of the lower level cache is identified that has a lowest reference count value in its associated reference counter. The member with the lowest reference count value in its associated reference counter is then evicted.
摘要翻译：提供了一种用于加权历史分配预测的机制。对于较低级缓存中的多个成员中的每个成员，相关联的引用计数器基于导致数据被分配给成员的成员位置的操作类型被初始化为初始值。对于对较低级缓存中的成员的每次访问，相关联的引用计数器递增。响应于对低级缓存的新数据分配并响应于需要在较低级别高速缓存中另一成员受害的数据的新分配，识别出在其级别缓存中具有最低参考计数值的成员相关参考计数器。然后将其相关参考计数器中具有最低参考计数值的成员逐出。

8. 发明授权

US08843707B2 Dynamic inclusive policy in a hybrid cache hierarchy using bandwidth 有权
标题翻译：使用带宽的混合缓存层次结构中的动态包容性策略
公开(公告)号：US08843707B2
公开(公告)日：2014-09-23
申请号：US13315395
申请日：2011-12-09
申请人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
IPC分类号： G06F13/00
CPC分类号： G06F12/0897 , G06F2212/502
摘要： A mechanism is provided for dynamic cache allocation using bandwidth. A bandwidth between a higher level cache and a lower level cache is monitored. Responsive to bandwidth usage between the higher level cache and the lower level cache being below a predetermined low bandwidth threshold, the higher level cache and the lower level cache are set to operate in accordance with a first allocation policy. Responsive to bandwidth usage between the higher level cache and the lower level cache being above a predetermined high bandwidth threshold, the higher level cache and the lower level cache are set to operate in accordance with a second allocation policy.
摘要翻译：提供了一种使用带宽进行动态高速缓存分配的机制。监视高级缓存和较低级别缓存之间的带宽。响应于较高级别高速缓存和较低级别高速缓存之间的带宽使用低于预定低带宽阈值，高级缓存和下级高速缓存被设置为根据第一分配策略进行操作。响应于高级缓存和低级高速缓存之间的带宽使用高于预定高带宽阈值，高级缓存和下级高速缓存被设置为根据第二分配策略进行操作。

9. 发明授权

US07536513B2 Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache state 有权
标题翻译：数据处理系统，缓存系统和方法，用于基于标记的高速缓存状态在不引用低级缓存的情况下在互连结构上发出请求
公开(公告)号：US07536513B2
公开(公告)日：2009-05-19
申请号：US11095734
申请日：2005-03-31
申请人： Guy L. Guthrie , Aaron C. Sawdey , William J. Starke , Jeffrey A. Stuecheli
发明人： Guy L. Guthrie , Aaron C. Sawdey , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F13/00 , G06F13/28 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/0815 , G06F12/0831
摘要： In response to a master receiving a memory access request indicating a target address, the master accesses a first cache directory of an upper level cache of a cache hierarchy. In response to the target address being associated in the first cache directory with an entry having a valid address tag and a first invalid coherency state, the master issues a request specifying the target address on an interconnect fabric without regard to a coherency state associated with the target address in a second cache directory of a lower level cache of the cache hierarchy. In response to the target address having a second invalid coherency state with respect to the first cache directory, the master issues a request specifying the target address on an interconnect fabric after determining a coherency state associated with the target address in the second cache directory of the lower level cache of the cache hierarchy.
摘要翻译：响应于主机接收到指示目标地址的存储器访问请求，主机访问高速缓存层级的高级缓存的第一高速缓存目录。响应于目标地址与具有有效地址标签的条目和第一无效一致性状态在第一高速缓存目录中相关联的目标地址，主机在不考虑与该互连结构相关联的一致性状态的情况下发布指定互连结构上的目标地址的请求目标地址在缓存层次结构的较低级缓存的第二高速缓存目录中。响应于相对于第一高速缓存目录具有第二无效一致性状态的目标地址，主机在确定与第二高速缓存目录中的目标地址相关联的一致性状态之后，在互连结构上发出指定目标地址的请求缓存层次结构的较低级缓存。

10. 发明授权

US08688915B2 Weighted history allocation predictor algorithm in a hybrid cache 有权
标题翻译：混合高速缓存中加权历史分配预测算法
公开(公告)号：US08688915B2
公开(公告)日：2014-04-01
申请号：US13315411
申请日：2011-12-09
申请人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
IPC分类号： G06F12/16
CPC分类号： G06F12/122 , G06F12/0897 , G06F12/121
摘要： A mechanism is provided for weighted history allocation prediction. For each member in a plurality of members in a lower level cache, an associated reference counter is initialized to an initial value based on an operation type that caused data to be allocated to a member location of the member. For each access to the member in the lower level cache, the associated reference counter is incremented. Responsive to a new allocation of data to the lower level cache and responsive to the new allocation of data requiring the victimization of another member in the lower level cache, a member of the lower level cache is identified that has a lowest reference count value in its associated reference counter. The member with the lowest reference count value in its associated reference counter is then evicted.
摘要翻译：提供了一种用于加权历史分配预测的机制。对于较低级缓存中的多个成员中的每个成员，相关联的引用计数器基于导致数据被分配给成员的成员位置的操作类型被初始化为初始值。对于对较低级缓存中的成员的每次访问，相关联的引用计数器递增。响应于对低级缓存的新数据分配并响应于需要在较低级别高速缓存中另一成员受害的数据的新分配，识别出在其级别缓存中具有最低参考计数值的成员相关参考计数器。然后将其相关参考计数器中具有最低参考计数值的成员逐出。

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