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    • 95. 发明申请
    • SERVICE CREATION SYSTEM AND IMPLEMENTING METHOD THEREOF
    • 服务创新系统及其实施方法
    • US20120136747A1
    • 2012-05-31
    • US13259804
    • 2010-05-14
    • Wei Wang
    • Wei Wang
    • G06Q30/06
    • H04L41/5041G06Q10/00G06Q50/01H04W4/60
    • The present invention discloses a service creation system and an implementing method thereof. The system comprises: a service creation module for managing and providing service information and service state; a serving access module for managing and providing the serving needed to consist the service; a service execution engine module for, when executing the service, acquiring corresponding service information and service state from the service creation module, acquiring a serving node related when executing a service logic according to the acquired corresponding service information, acquiring corresponding serving information from the serving access module, and invoking a corresponding serving. The present invention improves the service development flexibility.
    • 本发明公开了一种服务创建系统及其实现方法。 该系统包括:服务创建模块,用于管理和提供服务信息和服务状态; 用于管理和提供服务所需的服务的服务访问模块; 服务执行引擎模块,用于在执行所述服务时,从所述服务创建模块获取对应的服务信息和服务状态,根据获取的对应服务信息获取与执行服务逻辑相关的服务节点,从服务中获取相应的服务信息 访问模块,并调用相应的服务。 本发明提高了服务开发的灵活性。
    • 99. 发明授权
    • Data line structure in lead region
    • 铅区数据线结构
    • US08164194B2
    • 2012-04-24
    • US12265809
    • 2008-11-06
    • Wei QinWei Wang
    • Wei QinWei Wang
    • H01L23/48
    • G02F1/136227H01L2924/0002H01L2924/00
    • An embodiment of the invention provides a data line structure in a lead region of a thin film transistor liquid crystal display (TFT-LCD). The data line structure in the lead region comprises a substrate and a gate layer data line segment, a dielectric layer, a data line lead, and a passivation layer, which are formed sequentially in the lead region on the substrate. The gate layer data line segment extends corresponding to the data line lead; the data line lead is formed with a via hole therein; a portion of the gate insulating layer and a portion of the passivation layer in a position corresponding to the via hole are removed so as to form a connection hole together with the via hole; a connection line segment is formed in the connection hole, and the gate layer data line segment and the data line lead are connected by the connection line segment in the connection hole.
    • 本发明的实施例提供了薄膜晶体管液晶显示器(TFT-LCD)的引线区域中的数据线结构。 引线区域中的数据线结构包括在衬底上的引线区域中依次形成的衬底和栅极层数据线段,电介质层,数据线引线和钝化层。 栅极层数据线段对应于数据线引线延伸; 数据线引线在其中形成有通孔; 除去栅极绝缘层的一部分和与通孔相对应的位置的钝化层的一部分,以与通孔一起形成连接孔; 连接线段形成在连接孔中,栅极层数据线段和数据线引线通过连接孔中的连接线段连接。
    • 100. 发明申请
    • Semiconductor Device Die with Integrated MOSFET and Low Forward Voltage Diode-Connected Enhancement Mode JFET and Method
    • 具有集成MOSFET和低正向电压二极管连接增强模式JFET和方法的半导体器件芯片
    • US20120074896A1
    • 2012-03-29
    • US12893978
    • 2010-09-29
    • Sik LuiWei Wang
    • Sik LuiWei Wang
    • H02J7/00H01L21/8232H01L27/06
    • H01L27/0617H01L27/098
    • A semiconductor die with integrated MOSFET and diode-connected enhancement mode JFET is disclosed. The MOSFET-JFET die includes common semiconductor substrate region (CSSR) of type-1 conductivity. A MOSFET device and a diode-connected enhancement mode JFET (DCE-JFET) device are located upon CSSR. The DCE-JFET device has the CSSR as its DCE-JFET drain. At least two DCE-JFET gate regions of type-2 conductivity located upon the DCE-JFET drain and laterally separated from each other with a DCE-JFET gate spacing. At least a DCE-JFET source of type-1 conductivity located upon the CSSR and between the DCE-JFET gates. A top DCE-JFET electrode, located atop and in contact with the DCE-JFET gate regions and DCE-JFET source regions. When properly configured, the DCE-JFET simultaneously exhibits a forward voltage Vf substantially lower than that of a PN junction diode while the reverse leakage current can be made comparable to that of a PN junction diode.
    • 公开了具有集成MOSFET和二极管连接的增强型JFET的半导体管芯。 MOSFET-JFET管芯包括类型1导电性的公共半导体衬底区域(CSSR)。 MOSFET器件和二极管连接的增强型JFET(DCE-JFET)器件位于CSSR上。 DCE-JFET器件具有CSSR作为其DCE-JFET漏极。 至少两个DCE-JFET栅极区域,位于DCE-JFET漏极上,并以DCE-JFET栅极间隔彼此横向分离。 至少一个位于CSSR上和DCE-JFET门之间的类型1电导率的DCE-JFET源。 位于顶部并与DCE-JFET栅极区域和DCE-JFET源极区域接触的顶部DCE-JFET电极。 当正确配置时,DCE-JFET同时呈现基本上低于PN结二极管的正向电压Vf,而反向漏电流可以与PN结二极管的相反。