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91. 发明授权

US08050174B2 Self-healing chip-to-chip interface 失效
公开(公告)号：US08050174B2
公开(公告)日：2011-11-01
申请号：US12886404
申请日：2010-09-20
申请人： Wiren D. Becker , Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Robert J. Reese
发明人： Wiren D. Becker , Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Robert J. Reese
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

92. 发明授权

US07945881B2 Method of reducing crosstalk induced noise in circuitry designs 有权
标题翻译：减少电路设计中串扰引起的噪声的方法
公开(公告)号：US07945881B2
公开(公告)日：2011-05-17
申请号：US11961440
申请日：2007-12-20
申请人： Sungjun Chun , Anand Haridass , Jesus Montanez , Xiaomin Shen
发明人： Sungjun Chun , Anand Haridass , Jesus Montanez , Xiaomin Shen
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5077
摘要： A method of reducing crosstalk induced noise in a physical circuit wiring design constructs a spatial vector for each interconnect wire segment in the physical circuit wiring design. The method compares the spatial vectors of said physical circuit wiring design and identifies any of the spatial vectors that are parallel to each other and have opposite directions. The method may identify all drivers and receivers in the physical circuit wiring design, and trace each interconnect line, starting with its driver, to determine a routed length from the driver to each segment break point of the interconnect line. The method may construct the spatial vector by defining an origin in the physical circuit wiring design. The method determines a starting point and an ending point of the spatial vector with respect to the origin. The starting point of the spatial vector is the break point of the interconnect wire segment closer to the driver. The ending point of the spatial vector is the break point of the interconnect wire segment farther from the driver. The method may define a Cartesian coordinate system with respect to the origin. The Cartesian coordinate system may be orthogonal with the interconnect wire segments of the physical circuit wiring design. The method may define one or more geometry windows in the physical circuit wiring design and compare the spatial vectors in each geometry window.
摘要翻译：在物理电路布线设计中减少串扰引起的噪声的方法在物理电路布线设计中为每个互连线段构造空间矢量。该方法比较了所述物理电路布线设计的空间矢量，并且识别彼此平行且具有相反方向的任何空间矢量。该方法可以识别物理电路布线设计中的所有驱动器和接收器，并且从其驱动器开始追踪每个互连线，以确定从驱动器到互连线的每个段断点的路由长度。该方法可以通过在物理电路布线设计中定义原点来构造空间矢量。该方法确定相对于原点的空间矢量的起始点和终点。空间矢量的起始点是互连线段靠近驾驶员的断点。空间矢量的终点是互连线段远离驾驶员的断点。该方法可以相对于原点定义笛卡尔坐标系。笛卡尔坐标系可以与物理电路布线设计的互连线段正交。该方法可以在物理电路布线设计中定义一个或多个几何窗口并比较每个几何窗口中的空间矢量。

93. 发明申请

US20110083888A1 Noise Coupling Reduction and Impedance Discontinuity Control in High-Speed Ceramic Modules 有权
标题翻译：高速陶瓷模块的噪声耦合降低和阻抗不连续控制
公开(公告)号：US20110083888A1
公开(公告)日：2011-04-14
申请号：US12577259
申请日：2009-10-12
申请人： Jinwoo Choi , Sungjun Chun , Anand Haridass , Roger Weekly
发明人： Jinwoo Choi , Sungjun Chun , Anand Haridass , Roger Weekly
IPC分类号： H05K1/02 , H05K3/10 , G06F17/50
CPC分类号： G06F17/5068 , G06F17/5036 , H01L23/552 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0219 , H05K1/0224 , H05K3/4629 , H05K2201/09236 , H05K2201/09681 , H01L2924/00
摘要： An improved multi-layered ceramic package comprises: a plurality of signal layers, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; at least one reference mesh layer adjacent to one or more signal layers; and a plurality of via-connected coplanar-type shield (VCS) lines, with a first VCS line extending on a first side of a first signal line within the plurality of signal layers and a second VCS line extending on a second opposing side of the first signal line. Each of the plurality of VCS lines interconnect with and extend past one or more vias that are located along the directional path in which the VCS lines runs. The placement of the VCS lines relative to the signal lines reduces coupling noise and controls impedance discontinuity in the ceramic package.
摘要翻译：一种改进的多层陶瓷封装包括：多个信号层，每个具有一个或多个信号线; 多个通孔，每个通孔提供电压（Vdd）电源连接或地（Gnd）连接中的一个; 与一个或多个信号层相邻的至少一个参考网格层; 以及多个通孔连接的共面型屏蔽（VCS）线，其中在所述多个信号层中的第一信号线的第一侧上延伸的第一VCS线和在所述多个信号层的第二相对侧上延伸的第二VCS线第一条信号线。多个VCS线路中的每一条与VCS线路运行的定向路径相互连接并延伸经过一个或多个通孔。 VCS线相对于信号线的放置减少了耦合噪声并且控制了陶瓷封装中的阻抗不连续性。

94. 发明申请

US20110010482A1 Self-Healing Chip-to-Chip Interface 失效
标题翻译：自我修复芯片到芯片接口
公开(公告)号：US20110010482A1
公开(公告)日：2011-01-13
申请号：US12886404
申请日：2010-09-20
申请人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
发明人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
IPC分类号： G06F13/00
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译：一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。检测用于芯片的信号路径集合内的有缺陷的信号路径。信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径有缺陷的信号路径。

95. 发明授权

US07813266B2 Self-healing chip-to-chip interface 有权
标题翻译：自愈芯片到芯片的接口
公开(公告)号：US07813266B2
公开(公告)日：2010-10-12
申请号：US11948620
申请日：2007-11-30
申请人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
发明人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译：一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。检测用于芯片的信号路径集合内的有缺陷的信号路径。信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径有缺陷的信号路径。

96. 发明申请

US20100085872A1 Self-Healing Chip-to-Chip Interface 失效
标题翻译：自我修复芯片到芯片接口
公开(公告)号：US20100085872A1
公开(公告)日：2010-04-08
申请号：US12635121
申请日：2009-12-10
申请人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
发明人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
IPC分类号： H04L12/26
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译：一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。检测用于芯片的信号路径集合内的有缺陷的信号路径。信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径有缺陷的信号路径。

97. 发明申请

US20080143375A1 METHOD FOR REDUCING CROSS-TALK INDUCED SOURCE SYNCHRONOUS BUS CLOCK JITTER 失效
标题翻译：用于减少交叉输入源同步总线时钟抖动的方法
公开(公告)号：US20080143375A1
公开(公告)日：2008-06-19
申请号：US11611200
申请日：2006-12-15
申请人： Bao G. Truong , Daniel Mark Dreps , Anand Haridass , John C. Schiff , Joel D. Ziegelbein
发明人： Bao G. Truong , Daniel Mark Dreps , Anand Haridass , John C. Schiff , Joel D. Ziegelbein
IPC分类号： H03K19/00 , H03K19/003
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译：使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以第一个时钟信号的补码。从第一时钟信号产生频率为F / 2的第二时钟信号。第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。在一个实施例中，使用延迟线电路来移位第二时钟。在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。

98. 发明授权

US07302664B2 System and method for automatic insertion of on-chip decoupling capacitors 失效
标题翻译：自动插入片上去耦电容的系统和方法
公开(公告)号：US07302664B2
公开(公告)日：2007-11-27
申请号：US11054916
申请日：2005-02-10
申请人： Anand Haridass , Andreas Huber , Erich Klink , Jochen Supper
发明人： Anand Haridass , Andreas Huber , Erich Klink , Jochen Supper
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A system and method for automatic insertion of on-chip decoupling capacitors are provided. With the system and method, an integrated circuit design is partitioned into cells and the noise distribution per cell of an integrated circuit is determined. This noise distribution may be generated using any of a number of different known mechanisms and generally results in a noise-map being generated for the integrated circuit. Thereafter, a mapping function is applied to the noise map for each cell to determine a required capacitance for the cells of the integrated circuit. From this required capacitance per cell, the necessary decoupling capacitors may be identified as well as the location for insertion of these decoupling capacitors. In a similar manner, decoupling capacitors may be removed from cells of the integrated circuit based upon the determined required capacitance per cell.
摘要翻译：提供一种用于自动插入片上去耦电容器的系统和方法。利用该系统和方法，将集成电路设计划分为单元，确定集成电路的每个单元的噪声分布。该噪声分布可以使用多个不同的已知机构中的任何一个产生，并且通常导致为集成电路产生噪声映射。此后，将映射函数应用于每个单元的噪声图，以确定集成电路的单元所需的电容。根据每个电池所需的电容，可以识别必要的去耦电容以及插入这些去耦电容器的位置。以类似的方式，可以基于每个单元所确定的所需电容从集成电路的单元去除去耦电容器。

99. 发明申请

US20070187468A1 Low inductance via arrangement for multilayer ceramic substrates 失效
标题翻译：用于多层陶瓷衬底的低电感通孔布置
公开(公告)号：US20070187468A1
公开(公告)日：2007-08-16
申请号：US11355713
申请日：2006-02-16
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm O'Reilly , Roger Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm O'Reilly , Roger Weekly
IPC分类号： B23K5/20 , B23K20/10 , B23K1/06
CPC分类号： H05K1/162 , H01L23/49827 , H01L23/50 , H01L23/642 , H01L2924/0002 , H05K1/0306 , H05K3/4611 , H05K3/4629 , H05K2201/09609 , H05K2201/09627 , Y10T29/49117 , Y10T29/49155 , H01L2924/00
摘要： A low inductance via arrangement for multilayer ceramic (MLC) substrates is provided. With the MLC substrate and via arrangement of the illustrative embodiments, the via-field inductance for a given contact pad array is reduced. This reduction is achieved by the introduction of T-jogs and additional vias. These T-jogs and additional vias form additional current paths that cause additional parallel inductances that reduce the via-field inductance. In one illustrative embodiment, the additional T-jogs and vias are added to a center portion of a contact pad array. The T-jogs are comprised of two jogs in a wiring layer of the MLC, each jog being toward a via associated with an adjacent contact pad in the contact pad array. These additional T-jogs and vias form additional current loops parallel to the existing ones which thus, reduce the total inductance of the via-field.
摘要翻译：提供了一种用于多层陶瓷（MLC）衬底的低电感通孔布置。通过MLC衬底和示例性实施例的通孔布置，给定接触焊盘阵列的通孔电感减小。这种减少是通过引入T-jogs和附加通孔来实现的。这些T形点动和附加通孔形成额外的电流路径，从而产生额外的并联电感，从而减小通路电感。在一个说明性实施例中，附加的T形点动和通孔被添加到接触焊盘阵列的中心部分。 T-jogs由MLC的布线层中的两个点动组成，每个点动都朝向与接触垫阵列中的相邻接触焊盘相关联的通孔。这些额外的T形点动和通孔形成与现有循环平行的额外的电流回路，从而减小通孔的总电感。

100. 发明授权

US07233170B2 Programmable driver delay 有权
公开(公告)号：US07233170B2
公开(公告)日：2007-06-19
申请号：US11211955
申请日：2005-08-25
申请人： Wiren Dale Becker , Anand Haridass , Bao G. Truong
发明人： Wiren Dale Becker , Anand Haridass , Bao G. Truong
IPC分类号： H03K19/00
CPC分类号： H03K5/00 , H03K5/135 , H04L25/0276
摘要： Data busses are configured as N differential channels driven by a data signal and its complement through two off-chip drivers (OCDs). Each OCD is preceded by a programmable delay element and a two way MUX. The two data channels either transmit the data signals or a common clock signal as determined by a select signal from a skew controller. The differential signals are received in a differential receiver and a phase detector. The output of the phase detector in each differential channel is routed through an N×1 MUX. The N×1 MUX is controlled by the skew controller. The output of the N×1 MUX is fed back as a phase error feedback signal to the skew controller. Each differential data channel is sequentially selected and the programmable delays are adjusted until the phase error feedback signal from the selected phase detector reaches a predetermined minimum allowable value. Periodic adjustment may be implemented for calibration.

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