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91. 发明授权

US07772095B2 Integrated circuit having localized embedded SiGe and method of manufacturing 失效
标题翻译：具有局部嵌入式SiGe的集成电路及其制造方法
公开(公告)号：US07772095B2
公开(公告)日：2010-08-10
申请号：US12127887
申请日：2008-05-28
申请人： Thomas W Dyer
发明人： Thomas W Dyer
IPC分类号： H01L21/20
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： An integrated circuit (IC) with localized SiGe embedded in a substrate and a method of manufacturing the IC is provided. The method includes forming recesses in a substrate on each side of a gate structure and remote from a shallow trench isolation structure. The method further includes growing a stress material within the recesses such that the stress material is bounded on its side only by the substrate.
摘要翻译：本发明提供一种集成电路（IC），其集成电路（IC）具有嵌入基板中的局部SiGe和IC的制造方法。该方法包括在栅极结构的每一侧的基板上形成凹槽，并远离浅沟槽隔离结构。该方法还包括在凹部内生长应力材料，使得应力材料仅在其侧面仅由衬底限定。

92. 发明授权

US07667255B2 Deep trench inter-well isolation structure 有权
标题翻译：深沟槽间隔隔离结构
公开(公告)号：US07667255B2
公开(公告)日：2010-02-23
申请号：US11748532
申请日：2007-05-15
申请人： Thomas W. Dyer
发明人： Thomas W. Dyer
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/1087 , H01L21/76224 , H01L29/945
摘要： A deep trench is formed in a semiconductor substrate. The deep trench may comprise a pair of parallel substantially vertical sidewalls having a constant separation distance. A set of outer substantially vertical sidewalls may have a closed shape in a horizontal cross-section. At least one dielectric layer is formed in the deep trench. The deep trench is filled with at least one conductive trench fill material to form a conductive deep trench fill region. A shallow trench isolation structure is formed directly on the deep trench to encapsulate the conductive deep trench fill region therebeneath. The stack of the deep trench and the shallow trench isolation structure form a deep trench inter-well isolation structure that provides electrical isolation of devices on one side of the stack from devices on the other side.
摘要翻译：在半导体衬底中形成深沟槽。深沟槽可以包括具有恒定间隔距离的一对平行的大致垂直的侧壁。一组外部基本垂直的侧壁可以具有水平横截面中的封闭形状。在深沟槽中形成至少一个电介质层。深沟槽填充有至少一个导电沟槽填充材料以形成导电深沟槽填充区域。浅沟槽隔离结构直接形成在深沟槽上，以封装其下方的导电深沟槽填充区域。深沟槽和浅沟槽隔离结构的堆叠形成深沟槽隔间隔离结构，其提供了在堆叠的一侧上的装置与另一侧的装置的电隔离。

93. 发明授权

US07652336B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07652336B2
公开(公告)日：2010-01-26
申请号：US11834398
申请日：2007-08-06
申请人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
发明人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
IPC分类号： H01L29/78
CPC分类号： H01L29/6656 , H01L21/76232 , H01L21/823481 , H01L21/823878 , H01L29/165 , H01L29/41775 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片内形成至少一个隔离结构，并在半导体晶片上形成至少一个特征。移除所述至少一个隔离结构的顶部，并且在所述半导体晶片，所述至少一个特征以及所述至少一个隔离结构之上形成衬垫。在衬套上形成填充材料。填充材料和衬垫从半导体晶片的顶表面的至少一部分上方被去除。

94. 发明申请

US20090321847A1 HIGH PERFORMANCE CMOS DEVICES COMPRISING GAPPED DUAL STRESSORS WITH DIELECTRIC GAP FILLERS, AND METHODS OF FABRICATING THE SAME 有权
标题翻译：包含带有电介质隙隙填料的双层压缩机的高性能CMOS器件及其制造方法
公开(公告)号：US20090321847A1
公开(公告)日：2009-12-31
申请号：US12556261
申请日：2009-09-09
申请人： Bruce B. Doris , Thomas W. Dyer , David R. Medeiros , Anna W. Topol
发明人： Bruce B. Doris , Thomas W. Dyer , David R. Medeiros , Anna W. Topol
IPC分类号： H01L27/092 , H01L21/31 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L21/823871 , H01L29/7843
摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A tensilely stressed dielectric layer overlays the n-FET, and a compressively stressed dielectric layer overlays the p-FET. A gap is located between the tensilely and compressively stressed dielectric layers and is filled with a dielectric filler material. In one specific embodiment of the present invention, both the tensilely and compressively stressed dielectric layers are covered by a layer of the dielectric filler material, which is essentially free of stress. In an alternatively embodiment of the present invention, the dielectric filler material is only present in the gap between the tensilely and compressively stressed dielectric layers.
摘要翻译：本发明涉及具有间隙填充物的具有间隙双重应力的互补金属氧化物半导体（CMOS）器件。具体地，本发明的每个CMOS器件包括至少一个n沟道场效应晶体管（n-FET）和至少一个p沟道场效应晶体管（p-FET）。拉伸应力介电层覆盖n-FET，并且压应力介电层覆盖p-FET。间隙位于拉伸和压应力介电层之间，并填充有介电填料。在本发明的一个具体实施方案中，拉伸和压缩应力介电层都被基本上没有应力的介电填料材料层覆盖。在本发明的替代实施例中，电介质填充材料仅存在于拉伸和压缩应力介电层之间的间隙中。

95. 发明申请

US20090283829A1 FINFET WITH A V-SHAPED CHANNEL 审中-公开
标题翻译： FINFET与V形通道
公开(公告)号：US20090283829A1
公开(公告)日：2009-11-19
申请号：US12119515
申请日：2008-05-13
申请人： Thomas W. Dyer , Haining S. Yang
发明人： Thomas W. Dyer , Haining S. Yang
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66818
摘要： A fin-type field effect transistor (finFET) structure comprises a substrate having a planar upper surface, an elongated fin on the planar upper surface of the substrate (wherein the length and the height of the fin are greater that the width of the fin) and an elongated gate conductor on the planar upper surface of the substrate. The length and the height of the gate conductor are greater than the width of the gate conductor. The fin comprises a center section comprising a semiconducting channel region and end sections distal to the channel region. The end sections of the fin comprise conductive source and drain regions. The gate conductor covers the channel region of the fin. The sidewalls of the channel region comprise a different crystal orientation than the sidewalls of the source and drain regions.
摘要翻译：鳍式场效应晶体管（finFET）结构包括具有平坦上表面的基板，在基板的平面上表面上的细长翅片（其中鳍的长度和高度大于翅片的宽度）以及在基板的平面上表面上的细长栅极导体。栅极导体的长度和高度大于栅极导体的宽度。翅片包括中心部分，其包括半导体沟道区域和远离沟道区域的端部区段。翅片的端部部分包括导电源极和漏极区域。栅极导体覆盖鳍片的沟道区域。沟道区的侧壁包括与源区和漏区的侧壁不同的晶体取向。

96. 发明申请

US20090256173A1 COMPLEMENTARY FIELD EFFECT TRANSISTORS HAVING EMBEDDED SILICON SOURCE AND DRAIN REGIONS 有权
标题翻译：具有嵌入式硅源和漏区的补充场效应晶体管
公开(公告)号：US20090256173A1
公开(公告)日：2009-10-15
申请号：US12103301
申请日：2008-04-15
申请人： Xiangdong Chen , Thomas W. Dyer , Haining S. Yang
发明人： Xiangdong Chen , Thomas W. Dyer , Haining S. Yang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/8258 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of a substrate. The first semiconductor region can be grown laterally adjacent to a second semiconductor region which has a lattice constant smaller than that of silicon. Layers consisting essentially of silicon can be grown epitaxially onto exposed major surfaces of the first and second semiconductor regions after which gates can be formed which overlie the epitaxially grown silicon layers. Portions of the first and second semiconductor regions adjacent to the gates can be removed to form recesses. Regions consisting essentially of silicon can be grown within the recesses to form embedded silicon regions. Source and drain regions then can be formed in the embedded silicon regions. The difference between the lattice constant of silicon and that of the underlying first and second regions results in tensile stressed silicon over the first semiconductor region and compressive stressed silicon over the second semiconductor region.
摘要翻译：提供了制造互补应力半导体器件的方法，例如具有拉伸应力通道的NFET和具有压应力通道的PFET。在这种方法中，可以在衬底的下面的半导体区域外延生长具有大于硅的晶格常数的第一半导体区域。第一半导体区域可以与具有比硅的晶格常数小的晶格常数的第二半导体区域横向生长。基本上由硅组成的层可以外延生长到第一和第二半导体区域的暴露的主表面上，之后可以形成覆盖外延生长的硅层的栅极。可以去除与栅极相邻的第一和第二半导体区域的部分以形成凹部。基本上由硅组成的区域可以在凹槽内生长以形成嵌入的硅区域。然后可以在嵌入的硅区域中形成源区和漏区。硅的晶格常数和下面的第一和第二区域的晶格常数之间的差异导致第一半导体区域上的拉伸应力硅和第二半导体区域上的压应力硅。

97. 发明申请

US20090250738A1 SIMULTANEOUS BURIED STRAP AND BURIED CONTACT VIA FORMATION FOR SOI DEEP TRENCH CAPACITOR 有权
标题翻译：用于SOI深层电容器的同时生成的带状和带状接触
公开(公告)号：US20090250738A1
公开(公告)日：2009-10-08
申请号：US12098019
申请日：2008-04-04
申请人： Thomas W. Dyer
发明人： Thomas W. Dyer
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10867 , H01L29/66181
摘要： A node dielectric, an inner electrode, and a buried strap cavity are formed in the deep trench in an SOI substrate. A buried layer contact cavity is formed by lithographic methods. The buried strap cavity and the buried layer contact cavity are filled simultaneously by deposition of a conductive material, which is subsequently planarized to form a buried strap in the deep trench and a buried contact via outside the deep trench. The simultaneous formation of the buried strap and the buried contact via enables formation of a deep trench capacitor in the SOI substrate in an economic and efficient manner.
摘要翻译：在SOI衬底的深沟槽中形成节点电介质，内电极和掩埋带腔。通过光刻方法形成掩埋层接触腔。掩埋带腔和埋层接触腔通过沉积导电材料同时填充，导电材料随后被平坦化以在深沟槽中形成掩埋带，并且在深沟槽外部形成埋入接触。埋设带和埋入接触通孔的同时形成能够以经济和有效的方式在SOI衬底中形成深沟槽电容器。

98. 发明授权

US07598572B2 Silicided polysilicon spacer for enhanced contact area 失效
标题翻译：用于增强接触面积的硅化多晶硅间隔物
公开(公告)号：US07598572B2
公开(公告)日：2009-10-06
申请号：US11552673
申请日：2006-10-25
申请人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
发明人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
IPC分类号： H01L29/40
CPC分类号： H01L29/4983 , H01L21/28123 , H01L21/28518 , H01L21/76897 , H01L21/823418 , H01L21/823481 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact area is enhanced by the silicided polysilicon spacer.
摘要翻译：一种通过形成的硅化多晶硅间隔物具有增加的源/漏接触面积的集成电路器件。形成多晶硅侧壁间隔物，其高度小于所述栅极导体高度的百分之七十，并且在深源极和漏极区域上具有连续的表面硅化物层。接触面积由硅化多晶硅间隔物增强。

99. 发明申请

US20090230508A1 SOI PROTECTION FOR BURIED PLATE IMPLANT AND DT BOTTLE ETCH 失效
标题翻译：刨花板植入物和DT瓶盖的SOI保护
公开(公告)号：US20090230508A1
公开(公告)日：2009-09-17
申请号：US12048291
申请日：2008-03-14
申请人： Thomas W. Dyer , Herbert L. Ho , Ravi M. Todi
发明人： Thomas W. Dyer , Herbert L. Ho , Ravi M. Todi
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L29/945 , H01L21/3086 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： An SOI layer has an initial trench extending therethrough, prior to deep trench etch. An oxidation step, such as thermal oxidation is performed to form a band of oxide on an inner periphery of the SOI layer to protect it during a subsequent RIE step for forming a deep trench. The initial trench may stop on BOX underlying the SOI. The band of oxide may also protect the SOI during buried plate implant or gas phase doping.
摘要翻译：在深沟槽蚀刻之前，SOI层具有穿过其延伸的初始沟槽。执行氧化步骤，例如热氧化，以在SOI层的内周上形成氧化带，以在随后的用于形成深沟槽的RIE步骤中保护它。初始沟槽可能停在SOI上的BOX上。在掩埋板植入或气相掺杂期间，氧化物带也可以保护SOI。

100. 发明申请

US20090101979A1 Methods of Forming Field Effect Transistors Having Stress-Inducing Sidewall Insulating Spacers Thereon and Devices Formed Thereby 有权
标题翻译：形成具有应力诱导侧壁绝缘垫片的场效应晶体管的方法和由此形成的器件
公开(公告)号：US20090101979A1
公开(公告)日：2009-04-23
申请号：US11874118
申请日：2007-10-17
申请人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
发明人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.
摘要翻译：形成集成电路器件的方法包括形成具有栅电极的场效应晶体管，栅电极的侧壁上的牺牲隔离物和硅化源/漏区。当形成源极/漏极区域的高掺杂部分时，牺牲间隔物用作注入掩模。然后从栅电极的侧壁去除牺牲隔离物。然后，在栅电极的侧壁上形成应力诱导电绝缘层，其被配置为在场效应晶体管的沟道区域中引起净拉伸应力（用于NMOS晶体管）或压应力（用于PMOS晶体管）。

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