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1. 发明授权

US5790110A System and method for generating video in a computer system 失效
公开(公告)号：US5790110A
公开(公告)日：1998-08-04
申请号：US783777
申请日：1997-01-15
申请人： David C. Baker , Daniel P. Mulligan , Eric J. Schell
发明人： David C. Baker , Daniel P. Mulligan , Eric J. Schell
IPC分类号： H04N11/20 , G09G5/00 , G09G5/06 , G09G5/39 , G09G5/393 , G09G5/395 , H04N7/01 , H04N9/64 , H04N11/14 , H04N11/16 , G09G5/02
CPC分类号： H04N9/641 , G09G5/39 , G09G2310/04 , G09G2340/02 , G09G2340/125 , G09G5/06 , G09G5/393 , H04N11/14 , H04N11/16
摘要： A system and method for generating composite video signals in a computer. Digital pixel data may be processed by software to form component video pixel data, which may include luminance and chrominance components. A chrominance look-up table is provided in a display memory and is used for modulation of the chrominance components. The modulated components are then combined to form digital composite video pixel data which may be stored in a frame buffer in the display memory. Video control information is precalculated and stored in the display memory in advance. The digital composite video pixel data and video control information are then recovered from the display memory to produce a formatted stream of video data. The architecture of this system greatly reduces hardware complexity and bandwidth requirements. In addition, the process may be controlled by a media stream controller which is also adapted for audio and graphics processing. This allows the display memory and various other components to be shared by multiple media subsystems.

2. 发明授权

US5768275A Controller for ATM segmentation and reassembly 失效
标题翻译：控制器用于ATM分段和重组
公开(公告)号：US5768275A
公开(公告)日：1998-06-16
申请号：US633955
申请日：1996-04-15
申请人： Bradford C. Lincoln , Douglas M. Brady , David R. Meyer , Warner B. Andrews, Jr.
发明人： Bradford C. Lincoln , Douglas M. Brady , David R. Meyer , Warner B. Andrews, Jr.
IPC分类号： H04Q3/00 , H04L12/56 , H04Q11/04
CPC分类号： H04Q11/0478 , H04L12/5601 , H04L2012/561 , H04L2012/5616 , H04L2012/5649 , H04L2012/5651 , H04L2012/5652 , H04L2012/5679
摘要： A header and a payload in a cell are separated for transfer between a cell interface and a host memory. The header is transferred to a control memory. For transfer to the host memory, the control memory initially provides a host-memory region address and the region length. The payload is recorded in such region. The control memory also provides a second host-memory region address, and length, when the payload length exceeds the payload length in the first address region. For transfer from the host memory to the cell interface, the control memory provides a host memory region address and the header combines the header and the payload and passes the combination to the cell interface. Cells from different sources (i.e. terminals) are scheduled at table positions dependent upon their individual transfer rates. The cells at the scheduled positions are normally transferred in time slots corresponding to such positions. When more than one (1) cell is scheduled at the same position, one (1) cell is transferred on a preset priority basis to the corresponding time slot. The other cells are delayed for transfer subsequently in idle time slots (i.e. no cell normally scheduled) in the same or other priorities. The cell delays for each source are accumulated to a maximum preset value. When the cell delays accumulated for a source exceed the normal time spacing between cells from that source, the source transfers a cell in an idle time slot prior to the normally scheduled time slot to compensate for such delay.
摘要翻译：单元格中的标题和有效负载被分离以在单元接口和主机存储器之间传送。标题被传送到控制存储器。为了传输到主机存储器，控制存储器最初提供主机 - 存储器区域地址和区域长度。有效载荷记录在这样的区域。当有效载荷长度超过第一地址区域中的有效载荷长度时，控制存储器还提供第二主机 - 存储器区域地址和长度。为了从主机存储器传送到单元接口，控制存储器提供主机存储器区域地址，并且报头组合报头和有效载荷，并将组合传递到单元接口。来自不同来源（即终端）的小区根据其个人传送速率被安排在表位置。预定位置处的单元通常在对应于这些位置的时隙中传送。当多于一个（1）小区被调度在相同位置时，一（1）个小区以预设的优先级被传送到相应的时隙。在相同或其他优先级中，其他小区被延迟以在空闲时隙（即，没有小区正常安排）中传送。每个源的单元延迟被累积到最大预设值。当来自源的单元延迟超过来自该源的单元之间的正常时间间隔时，源在正常调度的时隙之前的空闲时隙中传送单元以补偿这种延迟。

3. 发明授权

US5731744A Voltage controlled oscillator 失效
标题翻译：压控振荡器
公开(公告)号：US5731744A
公开(公告)日：1998-03-24
申请号：US654054
申请日：1996-05-28
申请人： Jan C. Diffenderfer
发明人： Jan C. Diffenderfer
IPC分类号： H03B5/32 , H03B5/36 , H03L5/00 , H03J5/14
CPC分类号： H03B5/32 , H03B5/366 , H03L5/00
摘要： An apparatus and a method are provided to obtain oscillations from a crystal at a particular frequency by introducing real and imaginary components of voltage to the crystal. The imaginary component of voltage is different from the real component of voltage by a particular phase angle such as 90.degree.. The voltage introduced to the crystal is processed to produce a first current having characteristics corresponding to such voltage and to produce a second current having characteristics related to the imaginary component of such voltage. The first and second currents are combined to produce a first current corresponding to the real component of the voltage introduced to the crystal. This current is shifted through a phase angle of 90.degree. to produce a second current corresponding to the imaginary component of the voltage introduced to the crystal. The first current is converted to a first voltage which is regulated to provide a particular gain. This regulated voltage corresponds to the real component of the voltage introduced to the crystal. The second current is converted to a second voltage which can be adjusted to adjust the frequency of the oscillations from the oscillator. The second voltage corresponds to the imaginary component of the voltage introduced to the crystal. The first and second voltages are combined to produce the voltage for introduction to the crystal.
摘要翻译：提供了一种装置和方法，以通过将晶体的电压的实部和虚部分量从特定频率的晶体获得振荡。电压的虚分量与90°的特定相位角的实际电压分量不同。处理引入晶体的电压以产生具有对应于这种电压的特性的第一电流，并产生具有与该电压的虚分量相关的特性的第二电流。第一和第二电流被组合以产生对应于引入晶体的电压的实分量的第一电流。该电流通过90°的相位角移动，产生对应于引入晶体的电压的虚分量的第二电流。第一电流被转换成第一电压，其被调节以提供特定的增益。该调节电压对应于引入晶体的电压的实际分量。第二电流被转换成可调节的第二电压以调节振荡器的振荡频率。第二电压对应于引入晶体的电压的虚分量。第一和第二电压被组合以产生用于引入晶体的电压。

4. 发明授权

US5627396A Micromachined relay and method of forming the relay 失效
标题翻译：微加工继电器和形成继电器的方法
公开(公告)号：US5627396A
公开(公告)日：1997-05-06
申请号：US443456
申请日：1995-05-18
申请人： Christopher D. James , Henry S. Katzenstein
发明人： Christopher D. James , Henry S. Katzenstein
IPC分类号： H01L29/84 , H01H1/20 , H01H59/00 , H01L29/82
CPC分类号： H01H59/0009 , H01H1/20 , H01H2001/0084 , H01H2059/0018 , Y10T307/878
摘要： A bridging member extending across a cavity in a semiconductor substrate (e.g. signal crystal silicon) has successive layers--a masking layer, an electrically conductive layer (e.g. polysilicon) and an insulating layer (e.g. SiO.sub.2). A first electrical contact (e.g. gold coated with ruthenium) extends on the insulating layer in a direction perpendicular to the extension of the bridging member across the cavity. A pair of bumps (e.g. gold) are on the insulating layer each between the contact and one of the cavity ends. Initially the bridging member and then the contact and the bumps are formed on the substrate and then the cavity is etched in the substrate through holes in the bridging member. A pair of second electrical contacts (e.g. gold coated with ruthenium) are on the surface of an insulating substrate (e.g. pyrex glass) adjacent the semiconductor substrate. The two substrates are bonded after the contacts are cleaned. The first contact is normally separated from the second contacts because the bumps engage the insulating substrate surface. When a voltage is applied between an electrically conductive layer on the insulating substrate surface and the polysilicon layer, the bridging member is deflected so that the first contact engages the second contacts. Electrical leads extend on the surface of the insulating substrate from the second contacts to bonding pads disposed adjacent a second cavity in the semiconductor substrate. The resultant relays on a wafer may be separated by sawing the semiconductor and insulating substrates at the position of the second cavity in each relay to expose the pads for electrical connections.
摘要翻译：延伸穿过半导体衬底（例如信号晶体硅）中的空腔的桥接构件具有连续的层 - 掩模层，导电层（例如多晶硅）和绝缘层（例如SiO 2）。第一电接触件（例如镀有钌的金）在垂直于桥接构件的延伸方向的绝缘层上延伸穿过空腔。一对凸起（例如金）在绝缘层上分别位于接触件和一个空腔端部之间。最初，桥接构件，然后在衬底上形成接触和凸块，然后通过桥接构件中的孔在衬底中蚀刻空腔。一对第二电触点（例如镀有钌的金）位于与半导体衬底相邻的绝缘衬底（例如耐热玻璃）的表面上。触点清洁后，两个基板接合。第一触点通常与第二触点分离，因为凸块与绝缘基板表面接合。当在绝缘衬底表面上的导电层和多晶硅层之间施加电压时，桥接构件被偏转，使得第一触点接合第二触点。电引线在绝缘基板的表面上从第二触点延伸到邻近半导体衬底中的第二腔的接合焊盘。可以通过在每个继电器中的第二腔的位置处锯切半导体和绝缘基板来分离晶片上的所得继电器，以露出用于电连接的焊盘。

5. 发明授权

US5620933A Micromachined relay and method of forming the relay 失效
标题翻译：微加工继电器和形成继电器的方法
公开(公告)号：US5620933A
公开(公告)日：1997-04-15
申请号：US445139
申请日：1995-05-19
申请人： Christopher D. James , Henry S. Katzenstein
发明人： Christopher D. James , Henry S. Katzenstein
IPC分类号： H01L29/84 , H01H1/20 , H01H59/00 , H01L21/461 , H01L21/465
CPC分类号： H01H59/0009 , H01H1/20 , H01H2001/0084 , H01H2059/0018 , Y10T307/878
摘要： A bridging member extending across a cavity in a semiconductor substrate (e.g. single crystal silicon) has successive layers--a masking layer, an electrically conductive layer (e.g. polysilicon) and an insulating layer (e.g. SiO.sub.2). A first electrical contact (e.g. gold coated with ruthenium) extends on the insulating layer in a direction perpendicular to the extension of the bridging member across the cavity. A pair of bumps (e.g. gold) are on the insulating layer each between the contact and one of the cavity ends. Initially the bridging member and then the contact and the bumps are formed on the substrate and then the cavity is etched in the substrate through holes in the bridging member. A pair of second electrical contacts (e.g. gold coated with ruthenium) are on the surface of an insulating substrate (e.g. pyrex glass) adjacent the semiconductor substrate. The two substrates are bonded after the contacts are cleaned. The first contact is normally separated from the second contacts because the bumps engage the insulating substrate surface. When a voltage is applied between an electrically conductive layer on the insulating substrate surface and the polysilicon layer, the bridging member is deflected so that the first contact engages the second contacts. Electrical leads extend on the surface of the insulating substrate from the second contacts to bonding pads disposed adjacent a second cavity in the semiconductor substrate. The resultant relays on a wafer may be separated by sawing the semiconductor and insulating substrates at the position of the second cavity in each relay to expose the pads for electrical connections.
摘要翻译：延伸穿过半导体衬底（例如单晶硅）中的空腔的桥接构件具有连续的层 - 掩模层，导电层（例如多晶硅）和绝缘层（例如SiO 2）。第一电接触件（例如镀有钌的金）在垂直于桥接构件的延伸方向的绝缘层上延伸穿过空腔。一对凸起（例如金）在绝缘层上分别位于接触件和一个空腔端部之间。最初，桥接构件，然后在衬底上形成接触和凸块，然后通过桥接构件中的孔在衬底中蚀刻空腔。一对第二电触点（例如镀有钌的金）位于与半导体衬底相邻的绝缘衬底（例如耐热玻璃）的表面上。触点清洁后，两个基板接合。第一触点通常与第二触点分离，因为凸块与绝缘基板表面接合。当在绝缘衬底表面上的导电层和多晶硅层之间施加电压时，桥接构件被偏转，使得第一触点接合第二触点。电引线在绝缘基板的表面上从第二触点延伸到邻近半导体衬底中的第二腔的接合焊盘。可以通过在每个继电器中的第二腔的位置处锯切半导体和绝缘基板来分离晶片上的所得继电器，以露出用于电连接的焊盘。

6. 发明授权

US5500892A Echo canceller 失效
标题翻译：回音消除器
公开(公告)号：US5500892A
公开(公告)日：1996-03-19
申请号：US195267
申请日：1994-02-14
申请人： Daniel L. Essig
发明人： Daniel L. Essig
IPC分类号： H03H21/00 , H04B3/23 , H04M11/00
CPC分类号： H04B3/237
摘要： Analog signals representing individual digital values (+3, +1, -1, -3) of data pass through a telephone line to a receiver. These signals may first be provided in a pseudo random sequence. A linear echo canceller and a first adder at the receiver simultaneously eliminate, to some extent, echo signals resulting from second analog signals transmitted through the telephone line by the receiver. A non-linear echo canceller and a second adder further significantly reduce the echo signals and specifically reduce non-linear components in the echo signals. Adjustable signal delays achieve optimal performance of the linear and non-linear echo cancellers. In one inventive embodiment, each echo canceller includes a memory which stores, for each terminal in such echo canceller, data representing (a) the pseudo random sequence and (b) coefficients for adjusting the signals in such sequence. Such data for each terminal in such echo canceller is recorded in the memory for introduction to the next terminal in the memory. For each terminal in such echo canceller, the signals representing the data for the coefficient and the output from the associated adder are processed to determine an adjusted value of such coefficient for storage in the memory and for use in the next cycle of processing. The adjusted coefficient value and the data stored in the memory for such terminal are processed to produce signals for introduction to the associated adder. The signals from the second adder are processed to restore the data transmitted through the telephone line to the receiver.
摘要翻译：表示数据的各个数字值（+3，+1，-1，-3）的模拟信号通过电话线通过接收机。这些信号可以首先以伪随机序列提供。在接收器处，线性回波消除器和第一加法器同时消除由接收器通过电话线传输的第二模拟信号产生的回波信号。非线性回波消除器和第二加法器进一步显着地减少回波信号并且具体地减小回波信号中的非线性分量。可调节的信号延迟实现了线性和非线性回波消除器的最佳性能。在一个发明实施例中，每个回声消除器包括一个存储器，存储对于这种回波消除器中的每个终端，表示（a）伪随机序列的数据和（b）用于以这样的顺序调整信号的系数。这种回波消除器中的每个终端的这样的数据被记录在存储器中以被引入到存储器中的下一个终端。对于这种回波消除器中的每个终端，处理表示系数的数据和来自相关联的加法器的输出的信号，以确定用于在存储器中存储并用于下一个处理周期的这种系数的调整值。处理调整后的系数值和存储在该终端的存储器中的数据，以产生用于引入相关加法器的信号。来自第二加法器的信号被处理以将通过电话线传输的数据恢复到接收器。

7. 发明授权

US5325001A Negative feedback sense pre-amplifier 失效
标题翻译：负反馈感测前置放大器
公开(公告)号：US5325001A
公开(公告)日：1994-06-28
申请号：US909074
申请日：1992-07-02
申请人： Michael J. Brunolli
发明人： Michael J. Brunolli
IPC分类号： G11C11/419 , G11C7/06 , H03F3/45 , G01R19/00 , G11C7/00
CPC分类号： G11C7/062
摘要： A static RAM cell having first and second differentially connected lines reads binary information stored in the cell by providing a current through the cell and the first line to read a binary "1" or through the cell and the second line to read a binary "0". First and second transistors in a pre-amplifier respectively connected in the first and second lines provide outputs respectively representing a binary "1" and a binary "0". The first and second transistors pass control currents respectively through third and fourth transistors to produce bias currents in one of the first and second transistors when reading currents are not passing through that transistor and the cell. The control of the third and fourth transistors increases the frequency at which information is read from the cell and is amplified. In this improvement, the bias current in the line providing an output at each instant is reduced by respectively providing a negative feedback from the outputs (e.g. the drains) of the first and second transistors to control the inputs (e.g. the gates) of the third and fourth transistors. This reduces power losses while increasing the frequency at which binary information is read from the cell. The frequency may be further increased by including an impedance in the control circuitry to the third and fourth transistors to delay the response of the third and fourth transistors. Pairs of pre-amplifiers for different bit and word lines may be connected in parallel to provide further increases in the frequency response and further power losses.
摘要翻译：具有第一和第二差分连接线的静态RAM单元通过提供通过单元的电流和第一行读取二进制“1”或通过单元和第二行读取二进制“0”来读取存储在单元中的二进制信息 “。分别连接在第一和第二行中的前置放大器中的第一和第二晶体管提供分别表示二进制“1”和二进制“0”的输出。当读取电流不通过该晶体管和单元时，第一和第二晶体管分别通过第三和第四晶体管传递控制电流，以产生第一和第二晶体管之一中的偏置电流。第三和第四晶体管的控制增加了从单元读取信息并被放大的频率。在这种改进中，通过分别从第一和第二晶体管的输出（例如，漏极）分别提供负反馈来控制在每一时刻提供输出的线路中的偏置电流，以控制第三和第二晶体管的输入（例如，门）和第四晶体管。这降低了功率损耗，同时增加了从单元读取二进制信息的频率。通过将控制电路中的阻抗包括在第三和第四晶体管中来延迟第三和第四晶体管的响应，可以进一步增加频率。可以并行连接用于不同位和字线的一对预放大器，以提供频率响应和进一步功率损耗的进一步增加。

8. 发明授权

US5301305A Apparatus for amplifying signals in ping-pong arrangement to reduce the frequency of amplification 失效
标题翻译：用于以乒乓排列放大信号以减小放大频率的装置
公开(公告)号：US5301305A
公开(公告)日：1994-04-05
申请号：US616988
申请日：1990-11-20
申请人： Michael J. Brunolli
发明人： Michael J. Brunolli
IPC分类号： G11C11/41 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/16 , G11C11/417 , G11C7/06
CPC分类号： G11C7/00 , G11C7/10 , G11C7/1075 , G11C7/22 , G11C8/16
摘要： Input signals provide binary coded information at a first frequency. A ping-pong arrangement has two (2) substantially identical circuitries. The circuitries operate respectively in synchronism with first and second clock signals each having a frequency half that of the first frequency and each having a phase opposite to the phase of the other. When the first clock signal has a first polarity, the first circuitry produces first voltages representing these signals. In the second polarity of the first clock signal, the first circuitry produces first output signals representing the first voltages. The first circuitry continues producing the first voltages in the clock cycle after the initial production of such voltages. Similarly, the second circuitry produces second voltages representing the input signals in the first polarity of the second clock signal. In the second polarity of the second clock signal, the second circuitry produces second output signals representing the second voltages. The second circuitry continues producing the second voltages in the clock cycle after the initial production of such voltages. The first and second output signals may respectively constitute first pairs. In the first polarity of the first clock signal, the first circuitry equalizes the output signals in the first pair to provide for the subsequent production of updated output signals in the first circuitry in the second polarity of the first clock signal. Similarly, in the first polarity of the second clock signal, the second circuitry equalizes the output signals in the second pair.
摘要翻译：输入信号以第一频率提供二进制编码信息。乒乓配置有两（2）个基本相同的电路。电路分别与第一和第二时钟信号同步地操作，第一和第二时钟信号各自具有第一频率的频率的一半，并且每个具有与另一个的相位相反的相位。当第一时钟信号具有第一极性时，第一电路产生表示这些信号的第一电压。在第一时钟信号的第二极性中，第一电路产生表示第一电压的第一输出信号。在初始产生这样的电压之后，第一电路在时钟周期内继续产生第一电压。类似地，第二电路产生表示第二时钟信号的第一极性的输入信号的第二电压。在第二时钟信号的第二极性中，第二电路产生表示第二电压的第二输出信号。在初始产生这样的电压之后，第二电路在时钟周期内继续产生第二电压。第一和第二输出信号可以分别构成第一对。在第一时钟信号的第一极性中，第一电路对第一对中的输出信号进行均衡，以便在第一时钟信号的第二极性中在第一电路中随后产生更新的输出信号。类似地，在第二时钟信号的第一极性中，第二电路对第二对中的输出信号进行均衡。

9. 发明授权

US4926176A Self-timing analog-to-digital converting system 失效
标题翻译：自定时模数转换系统
公开(公告)号：US4926176A
公开(公告)日：1990-05-15
申请号：US236505
申请日：1988-08-25
申请人： Lanny L. Lewyn , Perry W. Lou
发明人： Lanny L. Lewyn , Perry W. Lou
IPC分类号： H03M1/36 , H03K3/356 , H03K5/08 , H03M1/12 , H03M1/34
CPC分类号： H03K3/356104 , H03M1/125 , H03M1/365
摘要： A substantially constant current is divided between two lines in accordance with the relative values of an input voltage and a reference voltage respectively introduced to such lines. The currents through the first and second lines respectively charge first and second capacitances. The charges in the first and second capacitances respectively control the magnitudes of the currents flowing through first and second control members to charge the first and second capacitances. The control members are interconnected so that any difference between the flow of current through the control members and the associated capacitances between magnified. When the charge in an individual one of the capacitances reaches a particular value, a signal on an output terminal associated with the other capacitance changes from the first magnitude to a second magnitude. During this time, the signal associated with the first capacitance remains at substantially the first magnitude. A plurality of stages, including the comparators discussed above, compare the input voltage with progressive values of the reference voltage. Such stages are connected to successive pairs of comparators to indicate, on the basis of the relative magnitudes of the voltages on the output terminals of such comparators, whether the reference voltage is greater than the input voltage for both comparators in such pairs. A output signal is provided by the plurality only when one pair of comparators provides an output indicating that the input voltage is between the reference voltages connected to that pair of comparators.

10. 发明授权

US4904922A Apparatus for converting between digital and analog values 失效
标题翻译：用于在数字和模拟值之间转换的装置
公开(公告)号：US4904922A
公开(公告)日：1990-02-27
申请号：US225055
申请日：1988-07-26
申请人： Joseph H. Colles
发明人： Joseph H. Colles
IPC分类号： H03M1/68 , H03M1/74
CPC分类号： H03M1/685 , H03M1/747
摘要： Output members in a matrix relationship having x and y inputs respectively receive signals in first and second pluralities cumulatively representing a digital value. These signals are decoded and are respectively introduced to the x and y inputs to activate a particular output member common to a selected x row and a selected y column. The output members in the preceding rows and preceding the activated output member in the selected row are also activated. Three-transistor (all of the same type) current sources provide constant currents to the activated output members. In each current source, a first transistor provides the constant current, a second transistor in each current source constitutes a switch operative in response to binary input signals, and a third transistor receives the constant current dependent upon the binary input to the second transistor. A circuit providing first and second reference voltages and including an operational amplifier produces a resultant voltage representing the difference between the reference voltages. The resultant voltage controls the current flowing through fourth and fifth transistors, preferably in series, thereby regulating the value of the first reference voltage. The amplifier output also regulates the current in the first transistor of each current cell, and the voltage from the fifth transistor biases the third transistor in each current cell toward a conductive state. The three transistors in each current source and the fourth and fifth transistors may be C-MOS transistors of the p type.
摘要翻译：具有x和y输入的矩阵关系的输出成员分别以第一和第二多个累积地表示数字值的信号接收信号。这些信号被解码并分别被引入x和y输入以激活所选x行和所选择的y列共有的特定输出成员。前一行中的输出成员和所选行中激活的输出成员之前的激活。三晶体管（所有相同类型）电流源为激活的输出元件提供恒定电流。在每个电流源中，第一晶体管提供恒定电流，每个电流源中的第二晶体管构成响应于二进制输入信号而工作的开关，并且第三晶体管根据二阶输入到第二晶体管接收恒定电流。提供第一和第二参考电压并且包括运算放大器的电路产生表示参考电压之间的差的合成电压。所得到的电压控制流过第四和第五晶体管的电流，优选地串联，从而调节第一参考电压的值。放大器输出还调节每个电流单元的第一晶体管中的电流，并且来自第五晶体管的电压将每个当前单元中的第三晶体管偏置为导通状态。每个电流源中的三个晶体管和第四和第五晶体管可以是p型的C-MOS晶体管。

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