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1. 发明申请

US20100046270A1 RESISTANCE VARIABLE MEMORY APPARATUS 有权
标题翻译：电阻可变存储器
公开(公告)号：US20100046270A1
公开(公告)日：2010-02-25
申请号：US12514025
申请日：2007-11-16
申请人： Yoshikazu Katoh , Kazuhiko Shimakawa , Zhiqiang Wei
发明人： Yoshikazu Katoh , Kazuhiko Shimakawa , Zhiqiang Wei
IPC分类号： G11C17/00 , G11C11/00
CPC分类号： G11C13/003 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/32 , G11C2213/76 , G11C2213/79
摘要： A resistance variable memory apparatus (100) of the present invention is a resistance variable memory apparatus (100) using a resistance variable element (22) transitioning between plural resistance states in response to electric pulses of the same polarity, in which a series resistance setting unit (10) is configured to set a resistance value of the series current path and a parallel resistance setting unit (30) is configured to set a resistance value of a parallel current path such that the resistance values become resistance values at which a node potential is not larger than a second voltage level in a state where an electric pulse application device (50) is outputting a first electric pulse after the resistance variable element (22) has switched to the high-resistance state, and the node potential is not larger than a first voltage level in the state where the electric pulse application device (50) is outputting a second electric pulse after the resistance variable element (22) has switched to the low-resistance state.
摘要翻译：本发明的电阻可变存储装置（100）是电阻可变存储装置（100），其使用电阻可变元件（22），其响应于相同极性的电脉冲在多个电阻状态之间转变，其中串联电阻设定单元（10）被配置为设置串联电流路径的电阻值，并联电阻设定单元（30）被配置为设置并联电流路径的电阻值，使得电阻值成为节点电位在电阻可变元件（22）切换到高电阻状态之后电脉冲施加装置（50）输出第一电脉冲的状态下不大于第二电压电平，并且节点电位不大在电脉冲施加装置（50）在电阻可变元件（22）之后输出第二电脉冲的状态下的第一电压电平ha s切换到低电阻状态。

2. 发明授权

US07920402B2 Resistance variable memory apparatus 有权
标题翻译：电阻变量存储装置
公开(公告)号：US07920402B2
公开(公告)日：2011-04-05
申请号：US12514025
申请日：2007-11-16
申请人： Yoshikazu Katoh , Kazuhiko Shimakawa , Zhiqiang Wei
发明人： Yoshikazu Katoh , Kazuhiko Shimakawa , Zhiqiang Wei
IPC分类号： G11C17/00 , G11C11/00
CPC分类号： G11C13/003 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/32 , G11C2213/76 , G11C2213/79
摘要： A resistance variable memory apparatus (100) of the present invention is a resistance variable memory apparatus (100) using a resistance variable element (22) transitioning between plural resistance states in response to electric pulses of the same polarity, in which a series resistance setting unit (10) is configured to set a resistance value of the series current path and a parallel resistance setting unit (30) is configured to set a resistance value of a parallel current path such that the resistance values become resistance values at which a node potential is not larger than a second voltage level in a state where an electric pulse application device (50) is outputting a first electric pulse after the resistance variable element (22) has switched to the high-resistance state, and the node potential is not larger than a first voltage level in the state where the electric pulse application device (50) is outputting a second electric pulse after the resistance variable element (22) has switched to the low-resistance state.
摘要翻译：本发明的电阻可变存储装置（100）是电阻可变存储装置（100），其使用电阻可变元件（22），其响应于相同极性的电脉冲在多个电阻状态之间转变，其中串联电阻设定单元（10）被配置为设置串联电流路径的电阻值，并联电阻设定单元（30）被配置为设置并联电流路径的电阻值，使得电阻值成为节点电位在电阻可变元件（22）切换到高电阻状态之后电脉冲施加装置（50）输出第一电脉冲的状态下不大于第二电压电平，并且节点电位不大在电脉冲施加装置（50）在电阻可变元件（22）之后输出第二电脉冲的状态下的第一电压电平ha s切换到低电阻状态。

3. 发明申请

US20100110766A1 NONVOLATILE MEMORY APPARATUS AND METHOD FOR WRITING DATA IN NONVOLATILE MEMORY APPARATUS 有权
标题翻译：非易失性存储器装置和非易失性存储器装置中的数据写入方法
公开(公告)号：US20100110766A1
公开(公告)日：2010-05-06
申请号：US12524313
申请日：2008-02-22
申请人： Zhiqiang Wei , Kazuhiko Shimakawa , Takeshi Takagi , Yoshikazu Katoh
发明人： Zhiqiang Wei , Kazuhiko Shimakawa , Takeshi Takagi , Yoshikazu Katoh
IPC分类号： G11C11/00 , G11C7/10 , G11C7/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/34 , G11C2213/72 , H01L27/1021
摘要： A nonvolatile memory apparatus comprises a memory array (102) including plural first electrode wires (WL) formed to extend in parallel with each other within a first plane; plural second electrode wires (BL) formed to extend in parallel with each other within a second plane parallel to the first plane and to three-dimensionally cross the plural first electrode wires; and nonvolatile memory elements (11) which are respectively provided at three-dimensional cross points between the first electrode wires and the second electrode wires, the elements each having a resistance variable layer whose resistance value changes reversibly in response to a current pulse supplied between an associated first electrode wire and an associated second electrode wire; and a first selecting device (13) for selecting the first electrode wires, and further comprises voltage restricting means (15) provided within or outside the memory array, the voltage restricting means being connected to the first electrode wires, for restricting a voltage applied to the first electrode wires to a predetermined upper limit value or less; wherein plural nonvolatile memory elements of the nonvolatile memory elements are connected to one first electrode wire connecting the first selecting device to the voltage restricting means.
摘要翻译：非易失性存储装置包括存储器阵列（102），其包括形成为在第一平面内彼此平行延伸的多个第一电极线（WL）多个第二电极线（BL），其形成为在与第一平面平行的第二平面内彼此平行延伸并且三维地交叉所述多个第一电极线; 和非易失性存储元件（11），其分别设置在第一电极线和第二电极线之间的三维交叉点处，每个元件具有电阻变化层，其电阻值响应于在相关联的第一电极线和相关联的第二电极线; 以及用于选择所述第一电极线的第一选择装置（13），并且还包括设置在所述存储器阵列内或外的电压限制装置（15），所述电压限制装置连接到所述第一电极线，用于限制施加到所述第一电极线达到预定的上限值以下; 其中所述非易失性存储元件的多个非易失性存储元件连接到将所述第一选择装置连接到所述电压限制装置的一个第一电极线。

4. 发明授权

US07916516B2 Nonvolatile memory apparatus and method for writing data in nonvolatile memory apparatus 有权
标题翻译：非易失性存储装置和用于在非易失性存储装置中写入数据的方法
公开(公告)号：US07916516B2
公开(公告)日：2011-03-29
申请号：US12524313
申请日：2008-02-22
申请人： Zhiqiang Wei , Kazuhiko Shimakawa , Takeshi Takagi , Yoshikazu Katoh
发明人： Zhiqiang Wei , Kazuhiko Shimakawa , Takeshi Takagi , Yoshikazu Katoh
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/34 , G11C2213/72 , H01L27/1021
摘要： A nonvolatile memory apparatus comprises a memory array (102) including plural first electrode wires (WL) formed to extend in parallel with each other within a first plane; plural second electrode wires (BL) formed to extend in parallel with each other within a second plane parallel to the first plane and to three-dimensionally cross the plural first electrode wires; and nonvolatile memory elements (11) which are respectively provided at three-dimensional cross points between the first electrode wires and the second electrode wires, the elements each having a resistance variable layer whose resistance value changes reversibly in response to a current pulse supplied between an associated first electrode wire and an associated second electrode wire; and a first selecting device (13) for selecting the first electrode wires, and further comprises voltage restricting means (15) provided within or outside the memory array, the voltage restricting means being connected to the first electrode wires, for restricting a voltage applied to the first electrode wires to a predetermined upper limit value or less; wherein plural nonvolatile memory elements of the nonvolatile memory elements are connected to one first electrode wire connecting the first selecting device to the voltage restricting means.
摘要翻译：非易失性存储装置包括存储器阵列（102），其包括形成为在第一平面内彼此平行延伸的多个第一电极线（WL）多个第二电极线（BL），其形成为在与第一平面平行的第二平面内彼此平行延伸并且三维地交叉所述多个第一电极线; 和非易失性存储元件（11），其分别设置在第一电极线和第二电极线之间的三维交叉点处，每个元件具有电阻变化层，其电阻值响应于在相关联的第一电极线和相关联的第二电极线; 以及用于选择所述第一电极线的第一选择装置（13），并且还包括设置在所述存储器阵列内或外的电压限制装置（15），所述电压限制装置连接到所述第一电极线，用于限制施加到所述第一电极线达到预定的上限值以下; 其中所述非易失性存储元件的多个非易失性存储元件连接到将所述第一选择装置连接到所述电压限制装置的一个第一电极线。

5. 发明申请

US20130077384A1 CROSS POINT VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND METHOD OF READING THEREBY 有权
标题翻译：交叉点可变电阻非易失性存储器件及其读取方法
公开(公告)号：US20130077384A1
公开(公告)日：2013-03-28
申请号：US13636169
申请日：2012-04-27
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C11/21
CPC分类号： G11C11/21 , G11C8/08 , G11C13/00 , G11C13/0007 , G11C13/0023 , G11C13/0028 , G11C13/004 , G11C2213/15 , G11C2213/71
摘要： A cross point variable resistance nonvolatile memory device including: a cross point memory cell array having memory cells each of which is placed at a different one of cross points of bit lines and word lines; a word line decoder circuit that selects at least one of the memory cells from the memory cell array; a read circuit that reads data from the selected memory cell; an unselected word line current source that supplies a first constant current; and a control circuit that controls the reading of the data from the selected memory cell, wherein the control circuit controls the word line decoder circuit, the read circuit, and the unselected word line current source so that when the read circuit reads data, the first constant current is supplied to an unselected word line.
摘要翻译：一种交叉点可变电阻非易失性存储器件，包括：具有存储单元的交叉点存储单元阵列，每个存储单元位于位线和字线的交叉点的不同位置; 字线解码器电路，从存储单元阵列中选择至少一个存储单元; 从所选择的存储单元读取数据的读取电路; 提供第一恒定电流的未选字线电流源; 以及控制电路，其控制来自所选择的存储单元的数据的读取，其中所述控制电路控制所述字线解码器电路，所述读取电路和所述未选字线电流源，使得当所述读取电路读取数据时，所述第一恒定电流被提供给未选择的字线。

6. 发明授权

US08867259B2 Method of programming variable resistance nonvolatile memory element 有权
标题翻译：编程可变电阻非易失性存储元件的方法
公开(公告)号：US08867259B2
公开(公告)日：2014-10-21
申请号：US13704649
申请日：2012-08-09
申请人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh , Shunsaku Muraoka
发明人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh , Shunsaku Muraoka
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C2013/0054 , G11C2013/0073 , G11C2013/0083 , G11C2013/0092 , G11C2213/56 , G11C2213/79
摘要： A method of programming a variable resistance nonvolatile memory element that removes a defect in a resistance change, ensures an operation widow, and stably sustains a resistance change operation, the method including: applying, when the detect in the resistance change occurs in the variable resistance nonvolatile memory element, a recovery voltage pulse at least once to the variable resistance nonvolatile memory element, the recovery voltage pulse including: a first recovery voltage pulse that has an amplitude greater than amplitudes of a normal high resistance writing voltage pulse and a low resistance writing voltage pulse; and a second recovery voltage pulse that is the low resistance writing voltage pulse following the first recovery voltage pulse.
摘要翻译：一种编程消除电阻变化缺陷的可变电阻非易失性存储元件的方法，确保操作遗ow，并稳定地维持电阻变化操作，该方法包括：当在可变电阻中发生电阻变化的检测时，非易失性存储元件，至少一次到可变电阻非易失性存储元件的恢复电压脉冲，恢复电压脉冲包括：第一恢复电压脉冲，其具有大于正常高电阻写入电压脉冲和低电阻写入的幅度的幅度电压脉冲; 以及第二恢复电压脉冲，其是跟随第一恢复电压脉冲的低电阻写入电压脉冲。

7. 发明授权

US08094482B2 Nonvolatile memory apparatus and nonvolatile data storage medium 有权
标题翻译：非易失性存储装置和非易失性数据存储介质
公开(公告)号：US08094482B2
公开(公告)日：2012-01-10
申请号：US12529466
申请日：2008-10-28
申请人： Zhiqiang Wei , Takeshi Takagi , Ken Kawai , Kazuhiko Shimakawa
发明人： Zhiqiang Wei , Takeshi Takagi , Ken Kawai , Kazuhiko Shimakawa
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0073 , G11C2013/009 , G11C2211/5646 , G11C2213/31 , G11C2213/32 , G11C2213/34 , G11C2213/79
摘要： A nonvolatile memory apparatus and a nonvolatile data storage medium of the present invention, including nonvolatile memory elements each of which changes its resistance in response to electric pulses applied, comprises a first write circuit for performing first write in which a first electric pulse is applied to the nonvolatile memory element to switch a resistance value of the nonvolatile memory element from a first resistance value to a second resistance value and a second electric pulse which is opposite in polarity to the first electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from the second resistance value to the first resistance value.
摘要翻译：本发明的非易失性存储装置和非易失性数据存储介质，包括各自根据施加的电脉冲改变其电阻的非易失性存储元件，包括用于执行第一写入的第一写入电路，其中施加第一电脉冲到将非易失性存储元件的电阻值从第一电阻值切换到与第一电脉冲极性相反的第二电阻值和第二电脉冲的非易失性存储元件施加到非易失性存储元件，以将电阻非易失性存储元件的值从第二电阻值到第一电阻值。

8. 发明授权

US08982603B2 Cross point variable resistance nonvolatile memory device and method of reading thereby 有权
标题翻译：交叉点可变电阻非易失性存储器件及其读取方法
公开(公告)号：US08982603B2
公开(公告)日：2015-03-17
申请号：US13636169
申请日：2012-04-27
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C11/00 , G11C11/21 , G11C13/00
CPC分类号： G11C11/21 , G11C8/08 , G11C13/00 , G11C13/0007 , G11C13/0023 , G11C13/0028 , G11C13/004 , G11C2213/15 , G11C2213/71
摘要： A cross point variable resistance nonvolatile memory device including: a cross point memory cell array having memory cells each of which is placed at a different one of cross points of bit lines and word lines; a word line decoder circuit that selects at least one of the memory cells from the memory cell array; a read circuit that reads data from the selected memory cell; an unselected word line current source that supplies a first constant current; and a control circuit that controls the reading of the data from the selected memory cell, wherein the control circuit controls the word line decoder circuit, the read circuit, and the unselected word line current source so that when the read circuit reads data, the first constant current is supplied to an unselected word line.
摘要翻译：一种交叉点可变电阻非易失性存储器件，包括：具有存储单元的交叉点存储单元阵列，每个存储单元位于位线和字线的交叉点的不同位置; 字线解码器电路，从存储单元阵列中选择至少一个存储单元; 从所选择的存储单元读取数据的读取电路; 提供第一恒定电流的未选字线电流源; 以及控制电路，其控制来自所选择的存储单元的数据的读取，其中所述控制电路控制所述字线解码器电路，所述读取电路和所述未选字线电流源，使得当所述读取电路读取数据时，所述第一恒定电流被提供给未选择的字线。

9. 发明授权

US08942050B2 Method of inspecting variable resistance nonvolatile memory device and variable resistance nonvolatile memory device 有权
标题翻译：检查可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法
公开(公告)号：US08942050B2
公开(公告)日：2015-01-27
申请号：US13637428
申请日：2011-09-07
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
IPC分类号： G11C7/06 , G11C13/00 , G11C29/50
CPC分类号： G11C13/0007 , G11C13/00 , G11C13/003 , G11C29/50008 , G11C2213/15
摘要： A method of inspecting a variable resistance nonvolatile memory device detecting a faulty memory cell of a memory cell array employing a current steering element, and a variable resistance nonvolatile memory device are provided. The method of inspecting a variable resistance nonvolatile memory device having a memory cell array, a memory cell selection circuit, and a read circuit includes: determining that a current steering element has a short-circuit fault when a variable resistance element is in a low resistance state and a current higher than or equal to a predetermined current passes through the current steering element, when the resistance state of the memory cell is read using a second voltage; and determining whether the variable resistance element is in the low or high resistance state, when the resistance state of the memory cell is read using a first voltage.
摘要翻译：提供了检测使用电流导向元件的存储单元阵列的故障存储单元的可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法。检查具有存储单元阵列的可变电阻非易失性存储器件，存储单元选择电路和读取电路的方法包括：当可变电阻元件处于低电阻时，确定当前的导向元件具有短路故障当使用第二电压读取存储单元的电阻状态时，高于或等于预定电流的电流通过电流导向元件; 以及当使用第一电压读取存储单元的电阻状态时，确定可变电阻元件是处于低电阻还是高电阻状态。

10. 发明申请

US20140078811A1 VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT WRITING METHOD AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：可变电阻非易失性存储器元件写入方法和可变电阻非易失性存储器件
公开(公告)号：US20140078811A1
公开(公告)日：2014-03-20
申请号：US13990209
申请日：2012-11-21
申请人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh , Yuichiro Ikeda
发明人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh , Yuichiro Ikeda
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/00 , G11C13/004 , G11C13/0064 , G11C2013/0073 , G11C2013/0092
摘要： Provided is a method of writing to a variable resistance nonvolatile memory element which is capable of both improving retention characteristics and enlarging a window of operation. In the method of writing, to write “1” data (LR), first a weak HR writing process is performed in which a weak HR writing voltage pulse set for changing the variable resistance nonvolatile memory element to an intermediate resistance state is applied and, subsequently, a LR writing process is performed in which a LR writing voltage pulse set for changing the variable resistance nonvolatile memory element from the intermediate resistance state to a LR state is applied.
摘要翻译：提供一种写入能够改善保持特性和扩大操作窗口的可变电阻非易失性存储元件的方法。在写入方法中，为了写入“1”数据（LR），首先执行将用于将可变电阻非易失性存储元件变更为中间电阻状态而设定的弱的HR写入电压脉冲的弱的HR写入处理，随后，执行LR写入处理，其中设置用于将可变电阻非易失性存储元件从中间电阻状态改变为LR状态的LR写入电压脉冲。

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