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1. 发明授权

US07593268B2 Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage 有权
标题翻译：使用反向偏置电压擦除现场可编程门阵列的可编程互连单元的方法
公开(公告)号：US07593268B2
公开(公告)日：2009-09-22
申请号：US11567625
申请日：2006-12-06
申请人： Volker Hecht , John McCollum , Robert M. Salter, III
发明人： Volker Hecht , John McCollum , Robert M. Salter, III
IPC分类号： G11C11/34
CPC分类号： G11C16/14 , H03K19/17748 , H03K19/1776
摘要： A method for erasing a non-volatile memory cell interconnect switch in an FPGA comprised providing an FPGA having a core containing a plurality of non-volatile-memory-cell interconnect switches, each switch formed in a switch well region and coupled to a source/drain of an n-channel transistor formed in a grounded well region separate from the switch well region. A non-volatile memory cell interconnect switch is selected for erasing. The switch well region is disconnected from ground. A VCC potential is applied to the switch well region and to the drain of the n-channel transistor to which it is coupled and an erase potential is applied to the gate of the selected non-volatile memory cell interconnect switch.
摘要翻译：一种用于擦除FPGA中的非易失性存储单元互连开关的方法，包括提供具有包含多个非易失性存储单元互连开关的核的FPGA，每个开关形成在开关阱区中并耦合到源/ 形成在与开关阱区域分离的接地阱区域中的n沟道晶体管的漏极。选择非易失性存储单元互连开关进行擦除。开关井区域与地面断开。将VCC电位施加到开关阱区域和与其耦合的n沟道晶体管的漏极，并且将擦除电位施加到所选择的非易失性存储器单元互连开关的栅极。

2. 发明授权

US6072720A Nonvolatile reprogrammable interconnect cell with programmable buried bitline 有权
标题翻译：具有可编程掩埋位线的非易失性可编程互连单元
公开(公告)号：US6072720A
公开(公告)日：2000-06-06
申请号：US205876
申请日：1998-12-04
申请人： Jack Zezhong Peng , Robert M. Salter, III , Volker Hecht , Kyung Joon Han , Robert U. Broze , Victor Levchenko
发明人： Jack Zezhong Peng , Robert M. Salter, III , Volker Hecht , Kyung Joon Han , Robert U. Broze , Victor Levchenko
IPC分类号： G11C16/04 , H01L21/82 , H01L21/822 , H01L21/8234 , H01L21/8247 , H01L27/04 , H01L27/088 , H01L27/115 , H01L27/118 , H01L29/788 , H01L29/792 , H03K19/177
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/11524
摘要： Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected through a buried bitline in juxtaposition with the switch transistor and the sense transistor over which are the floating gate and the control gate. The sense transistor can be fabricated simultaneously with fabrication of the switch transistor whereby the two transistors are identical in dopant concentrations.
摘要翻译：公开了一种使用FN隧道进行编程和擦除的FPGA单元和阵列结构。每个单元包括开关浮置栅极场效应晶体管和感测浮置栅极场效应晶体管，其中浮动栅极是共同的，并且控制栅极是共同的。单元的编程通过与开关晶体管和感测晶体管并置的埋入位线来实现，开关晶体管和浮动栅极和控制栅极在其上。感测晶体管可以与开关晶体管的制造同时制造，由此两个晶体管的掺杂剂浓度相同。

3. 发明授权

US6137728A Nonvolatile reprogrammable interconnect cell with programmable buried source/drain in sense transistor 有权
标题翻译：非易失性可重新编程的互连单元，具有可编程的埋入式源/漏极，在感应晶体管中
公开(公告)号：US6137728A
公开(公告)日：2000-10-24
申请号：US205678
申请日：1998-12-04
申请人： Jack Zezhong Peng , Volker Hecht , Robert M. Salter, III , Kyung Joon Han , Robert U. Broze
发明人： Jack Zezhong Peng , Volker Hecht , Robert M. Salter, III , Kyung Joon Han , Robert U. Broze
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/82 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088 , H01L27/115 , H01L27/118 , H01L29/788 , H01L29/792 , H03K19/177
CPC分类号： H01L27/11803 , G11C16/0441 , H01L27/115
摘要： Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected by voltage biasing the common control gate line and the source/drains of the sense transistor. The source/drains of the sense field effect transistor are formed from buried doped layers (e.g. N+ in a P-doped substrate) which are formed prior to formation of the polysilicon floating gate and control gate. Lateral diffusion of dopant from the buried source/drains into the channel beneath the floating gate facilitates electron tunneling during erase and program operations, and the graded junctions of the buried source/drains lower band-to-band tunneling leakage.
摘要翻译：公开了一种使用FN隧道进行编程和擦除的FPGA单元和阵列结构。每个单元包括开关浮置栅极场效应晶体管和感测浮置栅极场效应晶体管，其中浮动栅极是共同的，并且控制栅极是共同的。通过对公共控制栅极线和感测晶体管的源极/漏极的电压偏置来实现单元的编程。感测场效应晶体管的源极/漏极由在形成多晶硅浮置栅极和控制栅极之前形成的掩埋掺杂层（例如P掺杂衬底中的N +）形成。掺杂剂从掩埋源/漏极到浮置栅极下方的沟道的横向扩散有助于在擦除和编程操作期间的电子隧穿，并且埋入源/分级结的接合点降低带对带隧穿泄漏。

4. 发明授权

US07919977B2 Circuits and methods for testing FPGA routing switches 有权
标题翻译： FPGA路由交换机的电路和方法
公开(公告)号：US07919977B2
公开(公告)日：2011-04-05
申请号：US12860004
申请日：2010-08-20
申请人： Jonathan W. Greene , John McCollum , Volker Hecht
发明人： Jonathan W. Greene , John McCollum , Volker Hecht
IPC分类号： H03K19/00 , H01L25/00
CPC分类号： H03K19/17764 , G01R31/318519 , H03K19/17736
摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.
摘要翻译： FPGA架构包括具有非易失性开关的多路复用器，其具有耦合到字线W的控制栅极，与行相关联的每个字线，所述开关通过具有可控接地连接NGND的缓冲器连接到布线轨道，至少一些开关是连接开关可耦合到多个位线B中的一个，每个位线与列相关联。

5. 发明授权

US07804321B2 Circuits and methods for testing FPGA routing switches 有权
标题翻译： FPGA路由交换机的电路和方法
公开(公告)号：US07804321B2
公开(公告)日：2010-09-28
申请号：US12205656
申请日：2008-09-05
申请人： Jonathan W. Greene , John McCollum , Volker Hecht
发明人： Jonathan W. Greene , John McCollum , Volker Hecht
IPC分类号： H03K19/00 , H01L25/00
CPC分类号： H03K19/17764 , G01R31/318519 , H03K19/17736
摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.
摘要翻译： FPGA架构包括具有非易失性开关的多路复用器，其具有耦合到字线W的控制栅极，与行相关联的每个字线，所述开关通过具有可控接地连接NGND的缓冲器连接到布线轨道，至少一些开关是连接开关可耦合到多个位线B中的一个，每个位线与列相关联。

6. 发明申请

US20070091683A1 METHOD FOR ERASING PROGRAMMABLE INTERCONNECT CELLS FOR FIELD PROGRAMMABLE GATE ARRAYS USING REVERSE BIAS VOLTAGE 有权
标题翻译：使用反向偏置电压对现场可编程门阵列擦除可编程互连电池的方法
公开(公告)号：US20070091683A1
公开(公告)日：2007-04-26
申请号：US11567625
申请日：2006-12-06
申请人： Volker Hecht , John McCollum
发明人： Volker Hecht , John McCollum
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , H03K19/17748 , H03K19/1776
摘要： A method for erasing a non-volatile memory cell interconnect switch in an FPGA comprised providing an FPGA having a core containing a plurality of non-volatile-memory-cell interconnect switches, each switch formed in a switch well region and coupled to a source/drain of an n-channel transistor formed in a grounded well region separate from the switch well region. A non-volatile memory cell interconnect switch is selected for erasing. The switch well region is disconnected from ground. A VCC potential is applied to the switch well region and to the drain of the n-channel transistor to which it is coupled and an erase potential is applied to the gate of the selected non-volatile memory cell interconnect switch.
摘要翻译：一种用于擦除FPGA中的非易失性存储单元互连开关的方法，包括提供具有包含多个非易失性存储单元互连开关的核的FPGA，每个开关形成在开关阱区中并耦合到源/ 形成在与开关阱区域分离的接地阱区域中的n沟道晶体管的漏极。选择非易失性存储单元互连开关进行擦除。开关井区域与地面断开。 CC 电位被施加到开关阱区域和与其耦合的n沟道晶体管的漏极，并且擦除电位被施加到所选择的非易失性存储器单元互连的栅极开关。

7. 发明申请

US20100315118A1 CIRCUITS AND METHODS FOR TESTING FPGA ROUTING SWITCHES 有权
标题翻译：用于测试FPGA路由开关的电路和方法
公开(公告)号：US20100315118A1
公开(公告)日：2010-12-16
申请号：US12860004
申请日：2010-08-20
申请人： Jonathan W. Greene , John McCollum , Volker Hecht
发明人： Jonathan W. Greene , John McCollum , Volker Hecht
IPC分类号： H03K19/00
CPC分类号： H03K19/17764 , G01R31/318519 , H03K19/17736
摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.
摘要翻译： FPGA架构包括具有非易失性开关的多路复用器，其具有耦合到字线W的控制栅极，与行相关联的每个字线，所述开关通过具有可控接地连接NGND的缓冲器连接到布线轨道，至少一些开关是连接开关可耦合到多个位线B中的一个，每个位线与列相关联。

8. 发明授权

US07161841B1 Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage 有权
标题翻译：使用反向偏置电压擦除现场可编程门阵列的可编程互连单元的方法
公开(公告)号：US07161841B1
公开(公告)日：2007-01-09
申请号：US11171489
申请日：2005-06-29
申请人： Volker Hecht , John McCollum
发明人： Volker Hecht , John McCollum
IPC分类号： G11C11/34
CPC分类号： G11C16/14 , H03K19/17748 , H03K19/1776
摘要： A method for erasing a non-volatile memory cell interconnect switch in an FPGA comprises providing an FPGA having a core containing a plurality of non-volatile-memory-cell interconnect switches, each switch formed in a switch well region and coupled to a source/drain of an n-channel transistor formed in a grounded well region separate from the switch well region. A non-volatile memory cell interconnect switch is selected for erasing. The switch well region is disconnected from ground. A VCC potential is applied to the switch well region and to the drain of the n-channel transistor to which it is coupled and an erase potential is applied to the gate of the selected non-volatile memory cell interconnect switch.
摘要翻译：用于擦除FPGA中的非易失性存储单元互连开关的方法包括提供具有包含多个非易失性存储单元互连开关的核的FPGA，每个开关形成在开关阱区域中并且耦合到源极/ 形成在与开关阱区域分离的接地阱区域中的n沟道晶体管的漏极。选择非易失性存储单元互连开关进行擦除。开关井区域与地面断开。将VCC电位施加到开关阱区域和与其耦合的n沟道晶体管的漏极，并且将擦除电位施加到所选择的非易失性存储器单元互连开关的栅极。

9. 发明申请

US20100060311A1 CIRCUITS AND METHODS FOR TESTING FPGA ROUTING SWITCHES 有权
公开(公告)号：US20100060311A1
公开(公告)日：2010-03-11
申请号：US12205656
申请日：2008-09-05
申请人： Jonathan W. Greene , John McCollum , Volker Hecht
发明人： Jonathan W. Greene , John McCollum , Volker Hecht
IPC分类号： H03K19/00 , H03K19/177
CPC分类号： H03K19/17764 , G01R31/318519 , H03K19/17736
摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.

10. 发明授权

US08244791B1 Fast carry lookahead circuits 有权
标题翻译：快速携带查找电路
公开(公告)号：US08244791B1
公开(公告)日：2012-08-14
申请号：US12022721
申请日：2008-01-30
申请人： Volker Hecht , Marcel Derevlean , Jonathan Greene
发明人： Volker Hecht , Marcel Derevlean , Jonathan Greene
IPC分类号： G06F7/50
CPC分类号： G06F7/508
摘要： A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.
摘要翻译：快速前瞻进位加法器包括耦合到加法器逻辑的加法器逻辑和先行进位逻辑逻辑。进位路径逻辑具有主进位路径，进位入口路径和进位出口路径，进位路径与进位出口路径分离。

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