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1. 发明授权

US5925135A Clock rate compensation for a low frequency slave device 失效
标题翻译：低频从设备的时钟速率补偿
公开(公告)号：US5925135A
公开(公告)日：1999-07-20
申请号：US721234
申请日：1996-09-26
申请人： Tuong Trieu , James P. Kardach
发明人： Tuong Trieu , James P. Kardach
IPC分类号： G06F1/08 , G06F1/12 , G06F1/04
CPC分类号： G06F1/12 , G06F1/08
摘要： A slave device having clock rate compensation circuitry for low frequency operation. The slave device is coupled to a bus having a first operating frequency yet uses a slave clock signal having a frequency less than the first operating frequency. The slave device includes a bus clock driver circuit coupled to a bus clock interface for a bus clock signal. A slave controller state machine is clocked by the slave clock signal and accordingly operates at less than the first operating frequency. The clock rate compensation circuitry receives the bus clock signal, a data signal, and the slave clock signal, and synchronizes bus events for the state machine. The clock rate compensation circuitry also asynchronously begins a bus clock signal stretching period.
摘要翻译：具有用于低频操作的时钟速率补偿电路的从设备。从设备耦合到具有第一工作频率的总线，而使用具有小于第一工作频率的频率的从时钟信号。从设备包括总线时钟驱动器电路，其耦合到用于总线时钟信号的总线时钟接口。从控制器状态机由从时钟信号计时，因此在小于第一工作频率的情况下工作。时钟速率补偿电路接收总线时钟信号，数据信号和从时钟信号，并同步状态机的总线事件。时钟速率补偿电路还异步地开始总线时钟信号延伸周期。

2. 发明授权

US5898859A Address shadow feature and methods of using the same 失效
标题翻译：地址阴影功能和使用方法
公开(公告)号：US5898859A
公开(公告)日：1999-04-27
申请号：US724369
申请日：1996-10-01
申请人： James P. Kardach , Tuong Trieu
发明人： James P. Kardach , Tuong Trieu
IPC分类号： G06F15/16
CPC分类号： G06F13/24
摘要： An address shadow feature and methods of using the same. A slave controller of the present invention includes an address register coupled to receive a device address from a secondary bus interface. A match circuit is coupled to the address register and compares the device address to a shadow address, generating a match signal upon detection of a match between the shadow address and the device address. An interrupt generation circuit generates an interrupt signal in response to the match signal.
摘要翻译：地址阴影特征及使用方法。本发明的从属控制器包括地址寄存器，其耦合以从次级总线接口接收设备地址。匹配电路耦合到地址寄存器，并将器件地址与阴影地址进行比较，在检测到阴影地址和器件地址之间的匹配时产生匹配信号。中断产生电路响应于匹配信号产生中断信号。

3. 发明授权

US07612780B2 Optimized memory addressing 有权
标题翻译：优化的内存寻址
公开(公告)号：US07612780B2
公开(公告)日：2009-11-03
申请号：US11784342
申请日：2007-04-06
申请人： David E Freker , Aditya Sreenivas , Zohar Bogin , Anoop Mukker , Tuong Trieu
发明人： David E Freker , Aditya Sreenivas , Zohar Bogin , Anoop Mukker , Tuong Trieu
IPC分类号： G09G5/399 , G06F13/00 , G09G5/39
CPC分类号： G06F13/1684
摘要： Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.
摘要翻译：本发明的实施例涉及使用双通道存储器件的第一通道访问第一对相邻数据块; 并且使用所述存储器件的第二通道同时访问第二对相邻数据块，所述第二对与所述第一对间隔开预定间隔。

4. 发明授权

US06243781B1 Avoiding deadlock by storing non-posted transactions in an auxiliary buffer when performing posted and non-posted bus transactions from an outbound pipe 失效
标题翻译：在从出站管道执行发布和未发布的总线事务时，通过将非发布的事务存储在辅助缓冲区中来避免死锁
公开(公告)号：US06243781B1
公开(公告)日：2001-06-05
申请号：US09205051
申请日：1998-12-03
申请人： Wishwesh Gandhi , Tuong Trieu , Ashish Gadagkar , Zohar Bogin , David D. Lent
发明人： Wishwesh Gandhi , Tuong Trieu , Ashish Gadagkar , Zohar Bogin , David D. Lent
IPC分类号： G06F1314
CPC分类号： G06F13/4036
摘要： In a bus resource having an outbound pipe for processing both non-posted and posted transactions in a FIFO manner, a rejected non-posted transaction at the head of the outbound pipe is moved aside and into an auxiliary buffer to avoid a potential blockage of the outbound pipe. The auxiliary buffer is for holding transaction information and return data of the rejected non-posted transaction. The rejected transaction is eventually completed from the auxiliary buffer as determined by an arbiter.
摘要翻译：在具有用于以FIFO方式处理非发布和发布的交易的出站管道的总线资源中，在出站管道的头部处的被拒绝的非贴现事务被移动到辅助缓冲器中，以避免潜在的阻塞出站管道辅助缓冲区用于保存交易信息并返回被拒绝的非贴现交易的数据。被拒绝的事务最终由仲裁器确定的辅助缓冲区完成。

5. 发明授权

US07180520B2 Queue partitioning mechanism 有权
标题翻译：队列分区机制
公开(公告)号：US07180520B2
公开(公告)日：2007-02-20
申请号：US10795939
申请日：2004-03-08
申请人： Sarath Kotamreddy , Tuong Trieu
发明人： Sarath Kotamreddy , Tuong Trieu
IPC分类号： G06F13/14 , G06F13/18
CPC分类号： G06F13/1689
摘要： According to one embodiment a chipset is disclosed. The chipset includes a graphics accelerator, a memory controller and a queue mechanism. The queue mechanism includes a first functional unit block (FUB) coupled to the graphics accelerator, and a second FUB coupled to the memory controller.
摘要翻译：根据一个实施例，公开了一种芯片组。该芯片组包括图形加速器，存储器控制器和队列机制。队列机构包括耦合到图形加速器的第一功能单元块（FUB）和耦合到存储器控制器的第二FUB。

6. 发明申请

US20050091481A1 Deterministic shut down of memory devices in response to a system warm reset 有权
标题翻译：响应于系统热复位，确定性地关闭存储器件
公开(公告)号：US20050091481A1
公开(公告)日：2005-04-28
申请号：US10693226
申请日：2003-10-24
申请人： Zohar Bogin , Surya Kareenahalli , Anoop Mukker , David Sastry , Tuong Trieu
发明人： Zohar Bogin , Surya Kareenahalli , Anoop Mukker , David Sastry , Tuong Trieu
IPC分类号： G06F1/24 , G06F15/177
CPC分类号： G06F1/24
摘要： A method to deterministically shut down memory devices in response to a system warm reset has been disclosed. One embodiment of the method includes causing a first type of reset in a number of memory devices in a system in response to a second type of reset in the system being initiated if the memory devices are not initialized and enabling a deterministic shutdown mode in a memory controller, which is coupled to the memory devices, after the memory devices have been initialized. Other embodiments are described and claimed.
摘要翻译：已经公开了响应于系统热复位来确定地关闭存储器件的方法。该方法的一个实施例包括在系统中响应于系统中的第二类型的复位而引起系统中的多个存储器件中的第一类型的复位，如果存储器件未被初始化并且使能存储器中的确定性关断模式控制器，其在存储器件初始化之后耦合到存储器件。描述和要求保护其他实施例。

7. 发明授权

US06237055B1 Avoiding livelock when performing a long stream of transactions 失效
标题翻译：执行长时间的事务时避免活动锁定
公开(公告)号：US06237055B1
公开(公告)日：2001-05-22
申请号：US09205024
申请日：1998-12-03
申请人： Tuong Trieu , David D. Lent , Zohar Bogin , Ashish Gadagkar
发明人： Tuong Trieu , David D. Lent , Zohar Bogin , Ashish Gadagkar
IPC分类号： G06F13362
CPC分类号： G06F13/364
摘要： An arbiter comprising logic circuitry configured to delay granting bus ownership to an agent X in response to receiving a first signal which indicates that a device coupled to the bus is not available to service transactions directed at the device over the bus. For instance, the device may be a bridge and the grant is delayed if an inbound pipe of the bridge is full. The arbiter may provide a borrowed grant to an outbound pipe of the device for performing a transaction on the bus while waiting for an inbound pipe of the device to become available.
摘要翻译：一种仲裁器，包括逻辑电路，其被配置为响应于接收到指示耦合到总线的设备不能用于通过总线对设备进行服务的事务的第一信号来延迟向代理X授予总线所有权。例如，如果桥的入站管道已满，则设备可能是桥接器，并且延迟许可。仲裁器可以向设备的出站管道提供借用的授权，用于在等待设备的入站管道变得可用时在总线上进行交易。

8. 发明授权

US07797492B2 Method and apparatus for dedicating cache entries to certain streams for performance optimization 失效
标题翻译：将缓存条目专用于某些流以进行性能优化的方法和装置
公开(公告)号：US07797492B2
公开(公告)日：2010-09-14
申请号：US10783621
申请日：2004-02-20
申请人： Anoop Mukker , Zohar Bogin , Tuong Trieu , Aditya Navale
发明人： Anoop Mukker , Zohar Bogin , Tuong Trieu , Aditya Navale
IPC分类号： G06F13/16
CPC分类号： G06F12/121 , G06F12/0862 , G06F12/128
摘要： A method and apparatus for dedicating cache entries to certain streams for performance optimization are disclosed. The method according to the present techniques comprises partitioning a cache array into one or more special-purpose entries and one or more general-purpose entries, wherein special-purpose entries are only allocated for one or more streams having a particular stream ID.
摘要翻译：公开了用于将高速缓存条目专用于某些流以用于性能优化的方法和装置。根据本技术的方法包括将高速缓存阵列划分成一个或多个特殊用途条目和一个或多个通用条目，其中仅为具有特定流ID的一个或多个流分配专用条目。

9. 发明授权

US07230627B2 Optimized memory addressing 有权
标题翻译：优化的内存寻址
公开(公告)号：US07230627B2
公开(公告)日：2007-06-12
申请号：US10796686
申请日：2004-03-08
申请人： David E. Freker , Aditya Sreenivas , Zohar Bogin , Anoop Mukker , Tuong Trieu
发明人： David E. Freker , Aditya Sreenivas , Zohar Bogin , Anoop Mukker , Tuong Trieu
IPC分类号： G09G5/399 , G09G5/39 , G06F13/00
CPC分类号： G06F13/1684
摘要： Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.
摘要翻译：本发明的实施例涉及使用双通道存储器件的第一通道访问第一对相邻数据块; 并且使用所述存储器件的第二通道同时访问第二对相邻数据块，所述第二对与所述第一对间隔开预定间隔。

10. 发明申请

US20070188508A1 Optimized memory addressing 有权
公开(公告)号：US20070188508A1
公开(公告)日：2007-08-16
申请号：US11784342
申请日：2007-04-06
申请人： David Freker , Aditya Sreenivas , Zohar Bogin , Anoop Mukker , Tuong Trieu
发明人： David Freker , Aditya Sreenivas , Zohar Bogin , Anoop Mukker , Tuong Trieu
IPC分类号： G09G5/399
CPC分类号： G06F13/1684
摘要： Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

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