专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5898859A Address shadow feature and methods of using the same 失效
标题翻译：地址阴影功能和使用方法
公开(公告)号：US5898859A
公开(公告)日：1999-04-27
申请号：US724369
申请日：1996-10-01
申请人： James P. Kardach , Tuong Trieu
发明人： James P. Kardach , Tuong Trieu
IPC分类号： G06F15/16
CPC分类号： G06F13/24
摘要： An address shadow feature and methods of using the same. A slave controller of the present invention includes an address register coupled to receive a device address from a secondary bus interface. A match circuit is coupled to the address register and compares the device address to a shadow address, generating a match signal upon detection of a match between the shadow address and the device address. An interrupt generation circuit generates an interrupt signal in response to the match signal.
摘要翻译：地址阴影特征及使用方法。本发明的从属控制器包括地址寄存器，其耦合以从次级总线接口接收设备地址。匹配电路耦合到地址寄存器，并将器件地址与阴影地址进行比较，在检测到阴影地址和器件地址之间的匹配时产生匹配信号。中断产生电路响应于匹配信号产生中断信号。

2. 发明授权

US5925135A Clock rate compensation for a low frequency slave device 失效
标题翻译：低频从设备的时钟速率补偿
公开(公告)号：US5925135A
公开(公告)日：1999-07-20
申请号：US721234
申请日：1996-09-26
申请人： Tuong Trieu , James P. Kardach
发明人： Tuong Trieu , James P. Kardach
IPC分类号： G06F1/08 , G06F1/12 , G06F1/04
CPC分类号： G06F1/12 , G06F1/08
摘要： A slave device having clock rate compensation circuitry for low frequency operation. The slave device is coupled to a bus having a first operating frequency yet uses a slave clock signal having a frequency less than the first operating frequency. The slave device includes a bus clock driver circuit coupled to a bus clock interface for a bus clock signal. A slave controller state machine is clocked by the slave clock signal and accordingly operates at less than the first operating frequency. The clock rate compensation circuitry receives the bus clock signal, a data signal, and the slave clock signal, and synchronizes bus events for the state machine. The clock rate compensation circuitry also asynchronously begins a bus clock signal stretching period.
摘要翻译：具有用于低频操作的时钟速率补偿电路的从设备。从设备耦合到具有第一工作频率的总线，而使用具有小于第一工作频率的频率的从时钟信号。从设备包括总线时钟驱动器电路，其耦合到用于总线时钟信号的总线时钟接口。从控制器状态机由从时钟信号计时，因此在小于第一工作频率的情况下工作。时钟速率补偿电路接收总线时钟信号，数据信号和从时钟信号，并同步状态机的总线事件。时钟速率补偿电路还异步地开始总线时钟信号延伸周期。

3. 发明授权

US08522063B2 Non main CPU/OS based operational environment 有权
公开(公告)号：US08522063B2
公开(公告)日：2013-08-27
申请号：US13454993
申请日：2012-04-24
申请人： James P. Kardach , Brian V. Belmont , Muthu K. Kumar , Riley W. Jackson , Gunner Danneels , Richard A. Forand , Vivek Gupta , Jeffrey L. Huckins , Kristoffer D. Flemming , Uma M. Gadamsetty
发明人： James P. Kardach , Brian V. Belmont , Muthu K. Kumar , Riley W. Jackson , Gunner Danneels , Richard A. Forand , Vivek Gupta , Jeffrey L. Huckins , Kristoffer D. Flemming , Uma M. Gadamsetty
IPC分类号： G06F1/00 , H04B1/38
CPC分类号： G06F1/3296 , G06F1/266 , G06F1/3203 , G06F1/3293 , G06F13/102 , G06F13/4072 , G10L19/04 , H04R1/1091 , H04R2201/109 , Y02D10/122 , Y02D10/151 , Y02D50/20
摘要： A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.

4. 发明申请

US20120210036A1 NON MAIN CPU/OS BASED OPERATIONAL ENVIRONMENT 有权
标题翻译：非主CPU /操作系统的操作环境
公开(公告)号：US20120210036A1
公开(公告)日：2012-08-16
申请号：US13454993
申请日：2012-04-24
申请人： James P. Kardach , Brian V. Belmont , Muthu K. Kumar , Riley W. Jackson , Gunner Danneels , Richard A. Forand , Vivek Gupta , Jeffrey L. Huckins , Kristoffer D. Flemming , Uma M. Gadamsetty
发明人： James P. Kardach , Brian V. Belmont , Muthu K. Kumar , Riley W. Jackson , Gunner Danneels , Richard A. Forand , Vivek Gupta , Jeffrey L. Huckins , Kristoffer D. Flemming , Uma M. Gadamsetty
IPC分类号： G06F13/14
CPC分类号： G06F1/3296 , G06F1/266 , G06F1/3203 , G06F1/3293 , G06F13/102 , G06F13/4072 , G10L19/04 , H04R1/1091 , H04R2201/109 , Y02D10/122 , Y02D10/151 , Y02D50/20
摘要： A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
摘要翻译：描述了一种计算系统，其包括在所述计算系统在基于非主CPU / OS的非操作状态下操作时保持活动的主系统总线。计算系统还包括在计算系统处于基于非主CPU / OS的非操作状态之内的情况下操作功能任务的控制器。计算系统还包括耦合到主系统总线的I / O单元，其在计算系统在基于非主CPU / OS的非主操作状态下运行时保持活动。

5. 发明授权

US07631199B2 Various methods and apparatuses for power states in a controller 失效
标题翻译：用于控制器中功率状态的各种方法和装置
公开(公告)号：US07631199B2
公开(公告)日：2009-12-08
申请号：US11173784
申请日：2005-06-30
申请人： James P. Kardach , Barnes Cooper , Seh Kwa , Animesh Mishra , Paul Diefenbaugh
发明人： James P. Kardach , Barnes Cooper , Seh Kwa , Animesh Mishra , Paul Diefenbaugh
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/325
摘要： Various methods, apparatuses, and systems are described in which a chipset controller has circuitry to control communications with a peripheral device in a computing device. The chipset controller has logic configured 1) to detect a plug-in event when the peripheral device connects to the chipset controller and 2) to transition the chipset controller from a low power consumption state to a higher power consumption state based on the logic detecting the plug-in event.
摘要翻译：描述了各种方法，装置和系统，其中芯片组控制器具有控制与计算设备中的外围设备的通信的电路。芯片组控制器具有逻辑配置1）当外围设备连接到芯片组控制器时检测插件事件，以及2）基于逻辑检测来将芯片组控制器从低功耗状态转换到更高功耗状态插件事件。

6. 发明申请

US20090019185A1 Non Main CPU/OS Based Operational Environment 有权
标题翻译：非主CPU / OS操作环境
公开(公告)号：US20090019185A1
公开(公告)日：2009-01-15
申请号：US12235473
申请日：2008-09-22
申请人： James P. Kardach , Brian V. Belmont , Muthu K. Kumar , Riley W. Jackson , Gunner Danneels , Richard A. Forand , Vivek Gupta , Jeffrey L. Huckins , Kristoffer D. Flemming , Uma M. Gadamsetty
发明人： James P. Kardach , Brian V. Belmont , Muthu K. Kumar , Riley W. Jackson , Gunner Danneels , Richard A. Forand , Vivek Gupta , Jeffrey L. Huckins , Kristoffer D. Flemming , Uma M. Gadamsetty
IPC分类号： G06F3/00
CPC分类号： G06F1/3296 , G06F1/266 , G06F1/3203 , G06F1/3293 , G06F13/102 , G06F13/4072 , G10L19/04 , H04R1/1091 , H04R2201/109 , Y02D10/122 , Y02D10/151 , Y02D50/20
摘要： A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
摘要翻译：描述了一种计算系统，其包括在所述计算系统在基于非主CPU / OS的非操作状态下操作时保持活动的主系统总线。计算系统还包括在计算系统处于基于非主CPU / OS的非操作状态之内的情况下操作功能任务的控制器。计算系统还包括耦合到主系统总线的I / O单元，其在计算系统在基于非主CPU / OS的非主操作状态下运行时保持活动。

7. 发明授权

US07454639B2 Various apparatuses and methods for reduced power states in system memory 有权
标题翻译：用于在系统存储器中降低功率状态的各种装置和方法
公开(公告)号：US07454639B2
公开(公告)日：2008-11-18
申请号：US11174060
申请日：2005-06-30
申请人： Sandeep Jain , James P. Kardach
发明人： Sandeep Jain , James P. Kardach
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3275 , G06F1/3225 , Y02D10/14
摘要： A method, apparatus, and system are described in which a memory controller may have two or more registers to create and track zones of memory in a volatile memory device. The memory controller controls a power consumption state of a first zone of memory in the volatile memory device and a second zone of memory within the first volatile memory device on an individual basis; and one or more memory arrays contained within the first volatile memory device.
摘要翻译：描述了一种方法，装置和系统，其中存储器控制器可以具有两个或更多个寄存器来创建和跟踪易失性存储器设备中的存储器区域。存储器控制器在单独的基础上控制易失性存储器设备中的第一存储器区域和第一易失性存储器设备内的第二存储器区域的功耗状态; 以及包含在第一易失性存储器件内的一个或多个存储器阵列。

8. 发明授权

US07430673B2 Power management system for computing platform 有权
标题翻译：计算平台电源管理系统
公开(公告)号：US07430673B2
公开(公告)日：2008-09-30
申请号：US11173220
申请日：2005-06-30
申请人： James P. Kardach , Barnes Cooper , Paul Diefenbaugh , Seh Kwa , Animesh Mishra
发明人： James P. Kardach , Barnes Cooper , Paul Diefenbaugh , Seh Kwa , Animesh Mishra
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/325 , Y02D10/126 , Y02D50/20
摘要： A power management system for a computing platform is described. In one embodiment, the power management system provides additional device states which the device controllers of the platform assume when the device controllers are operational but idle. These additional device states are states in which the device controller commits to certain types of inactivity. In another embodiment, the power management system provides additional platform modes which guarantee processor inactivity and/or deference of particular platform events while the mode is in effect.
摘要翻译：描述了一种用于计算平台的电源管理系统。在一个实施例中，电源管理系统提供当设备控制器可操作但空闲时，平台的设备控制器假设的附加设备状态。这些附加设备状态是设备控制器执行某些类型的不活动状态。在另一个实施例中，电源管理系统提供额外的平台模式，其在模式有效时保证处理器不活动和/或尊重特定平台事件。

9. 发明授权

US06801755B2 Method and apparatus for providing a radio module for a computer system 有权
标题翻译：用于为计算机系统提供无线电模块的方法和装置
公开(公告)号：US06801755B2
公开(公告)日：2004-10-05
申请号：US09821346
申请日：2001-03-29
申请人： James P. Kardach , Jeffrey L. Schiffer
发明人： James P. Kardach , Jeffrey L. Schiffer
IPC分类号： H04B700
CPC分类号： G06F1/1616
摘要： A radio module that meets FCC Limited Modular Approval including a wireless transceiver and a low-level baseband controller. Only a portion of the baseband associated with a wireless communication protocol is contained within the controller. The remainder of the baseband may be contained within a host computer system to which the module may be coupled such that, for one embodiment, the module may be selectively operated in accordance with one of multiple wireless communication protocols.
摘要翻译：符合FCC限制模块化认证的无线电模块，包括无线收发器和低级基带控制器。与无线通信协议相关联的基带的仅一部分包含在控制器内。基带的其余部分可以包含在可以耦合模块的主计算机系统中，使得对于一个实施例，可以根据多个无线通信协议之一选择性地操作该模块。

10. 发明授权

US06567414B2 Method and apparatus for exiting a deadlock condition 有权
标题翻译：退出死锁状态的方法和装置
公开(公告)号：US06567414B2
公开(公告)日：2003-05-20
申请号：US09183051
申请日：1998-10-30
申请人： Feng Deng , James P. Kardach
发明人： Feng Deng , James P. Kardach
IPC分类号： H04L1228
CPC分类号： G06F13/4036
摘要： A bridge for communicating between a first and a second bus includes a first interface unit, a second interface unit and a buffer unit. The first interface unit is adapted to be coupled to the first bus. The second interface unit is adapted to be coupled to the second bus. The buffer unit is coupled to the first and second interface units. The buffer unit is adapted to receive a posted transaction from one of the first and second interface units. The buffer unit includes a posting buffer and a discard timer. The posting buffer is adapted to store the posted transaction. The discard timer is adapted to generate a discard timer expired signal after a predetermined time interval that the posted transaction has resided in the posting buffer. A method for exiting from a potential deadlock situation includes posting a transaction, tracking the length of time the transaction has been posted, and discarding the transaction after a predetermined time interval that the transaction has been posted.
摘要翻译：用于在第一和第二总线之间通信的桥接器包括第一接口单元，第二接口单元和缓冲单元。第一接口单元适于耦合到第一总线。第二接口单元适于耦合到第二总线。缓冲单元耦合到第一和第二接口单元。缓冲器单元适于从第一和第二接口单元之一接收已发布的事务。缓冲单元包括发布缓冲器和丢弃定时器。发布缓冲区适用于存储已发布的事务。丢弃定时器适于在发布的事务已经驻留在发布缓冲器中的预定时间间隔之后生成丢弃定时器过期信号。从潜在的死锁情况退出的方法包括发布交易，跟踪交易已经发布的时间长度，以及在交易已经过帐的预定时间间隔之后丢弃交易。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式