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1. 发明授权

US4920401A Bipolar transistors 失效
标题翻译：双极晶体管
公开(公告)号：US4920401A
公开(公告)日：1990-04-24
申请号：US710950
申请日：1985-03-14
申请人： Tetsushi Sakai , Yoshizi Kobayasi , Hironori Yamauchi , Yoshinobu Arita
发明人： Tetsushi Sakai , Yoshizi Kobayasi , Hironori Yamauchi , Yoshinobu Arita
IPC分类号： H01L29/43 , H01L21/033 , H01L21/28 , H01L21/311 , H01L21/3115 , H01L21/3215 , H01L21/331 , H01L21/768 , H01L29/73 , H01L29/732
CPC分类号： H01L29/66272 , H01L21/033 , H01L21/31111 , H01L21/31155 , H01L21/32155 , H01L29/7322
摘要： In a bipolar transistor, around the border line of the surface of a base region formed on a semiconductor substrate is formed a base electrode having a constant width of less than one micron and made of polycrystalline silicon. An island shaped emitter region is formed in the base region and an emitter electrode is formed on the surface of the emitter region. The emitter electrode is electrically isolated from the base electrode by an insulating film extending between the periphery of the emitter region and the base electrode.

2. 发明授权

US4531282A Bipolar transistors having vertically arrayed collector-base-emitter with novel polycrystalline base electrode surrounding island emitter and method of making same 失效
标题翻译：双极晶体管具有垂直排列的集电极 - 基极 - 发射极和围绕岛发射体的新型多晶基极及其制造方法
公开(公告)号：US4531282A
公开(公告)日：1985-07-30
申请号：US571453
申请日：1984-01-17
申请人： Tetsushi Sakai , Yoshizi Kobayasi , Hironori Yamauchi , Yoshinobu Arita
发明人： Tetsushi Sakai , Yoshizi Kobayasi , Hironori Yamauchi , Yoshinobu Arita
IPC分类号： H01L29/43 , H01L21/033 , H01L21/28 , H01L21/311 , H01L21/3115 , H01L21/3215 , H01L21/331 , H01L21/768 , H01L29/73 , H01L29/732 , H01L21/225
CPC分类号： H01L29/66272 , H01L21/033 , H01L21/31111 , H01L21/31155 , H01L21/32155 , H01L29/7322
摘要： In a bipolar transistor, around the border line of the surface of a base region formed on a semiconductor substrate is formed a base electrode having a constant width of less than one micron and made of polycrystalline silicon. An island shaped emitter region is formed in the base region and an emitter electrode is formed on the surface of the emitter region. The emitter electrode is electrically isolated from the base electrode by an insulating film extending between the periphery of the emitter region and the base electrode.
摘要翻译：在双极晶体管中，形成在半导体衬底上形成的基极区域的表面的边界线周围，形成具有小于1微米的恒定宽度并由多晶硅制成的基极。在基极区域形成岛状发射极区域，在发射极区域的表面上形成发射电极。发射电极通过在发射极区域的周边和基极之间延伸的绝缘膜与基极电隔离。

3. 发明授权

US4379001A Method of making semiconductor devices 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US4379001A
公开(公告)日：1983-04-05
申请号：US58417
申请日：1979-07-18
申请人： Tetsushi Sakai , Yoshiji Kobayasi , Yousuke Yamamoto , Hironori Yamauchi
发明人： Tetsushi Sakai , Yoshiji Kobayasi , Yousuke Yamamoto , Hironori Yamauchi
IPC分类号： H01L21/033 , H01L21/3213 , H01L21/3215 , H01L21/331 , H01L21/263 , H01L21/20 , H01L21/22
CPC分类号： H01L29/66272 , H01L21/033 , H01L21/32134 , H01L21/32155
摘要： In a semiconductor device such as a bipolar transistor and a field effect transistor of the type having a substrate, a doped polycrystalline silicon region selectively formed on the substrate and an insulating film overlying the polycrystalline silicon region, the region is shaped as mesa having side surfaces with a negative coefficient of gradient between the substrate and the top of the mesa.
摘要翻译：在诸如双极晶体管的半导体器件和具有衬底的场效应晶体管中，选择性地形成在衬底上的掺杂多晶硅区域和覆盖多晶硅区域的绝缘膜，该区域被成形为具有侧面的台面在底物和台面顶部之间具有负的系数梯度。

4. 发明授权

US5989981A Method of manufacturing SOI substrate 失效
标题翻译：制造SOI衬底的方法
公开(公告)号：US5989981A
公开(公告)日：1999-11-23
申请号：US886876
申请日：1997-07-02
申请人： Sadao Nakashima , Terukazu Ohno , Toshiaki Tsuchiya , Tetsushi Sakai , Shinji Nakamura , Takemi Ueki , Yuichi Kado , Tadao Takeda
发明人： Sadao Nakashima , Terukazu Ohno , Toshiaki Tsuchiya , Tetsushi Sakai , Shinji Nakamura , Takemi Ueki , Yuichi Kado , Tadao Takeda
IPC分类号： H01L21/265 , H01L21/322
CPC分类号： H01L21/3226 , H01L21/26533
摘要： A method of manufacturing an SOI substrate uses an SOI substrate having a first single-crystal silicon layer, an insulating layer formed on the first single-crystal silicon layer, and a second single-crystal silicon layer formed on the insulating layer. The surface of the second single-crystal silicon layer is thermally oxidized. The second single-crystal silicon layer is controlled to have a predetermined thickness by removing the thermally oxidized surface. This step controlling the second single-crystal silicon layer to have a predetermined thickness includes the step of eliminating, by annealing, a stacking fault formed by the thermal oxidation.
摘要翻译：制造SOI衬底的方法使用具有第一单晶硅层，形成在第一单晶硅层上的绝缘层和形成在绝缘层上的第二单晶硅层的SOI衬底。第二单晶硅层的表面被热氧化。通过去除热氧化表面，将第二单晶硅层控制为具有预定的厚度。控制第二单晶硅层具有预定厚度的步骤包括通过退火消除由热氧化形成的堆垛层错的步骤。

5. 发明申请

US20070018246A1 Semiconductor device and semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US20070018246A1
公开(公告)日：2007-01-25
申请号：US11447926
申请日：2006-06-07
申请人： Juri Kato , Hideaki Oka , Kei Kanemoto , Toshiki Hara , Tetsushi Sakai
发明人： Juri Kato , Hideaki Oka , Kei Kanemoto , Toshiki Hara , Tetsushi Sakai
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/78648
摘要： A semiconductor device includes a back gate electrode composed of a first single-crystal semiconductor layer formed on a first insulating layer, a second insulating layer formed on the first single-crystal semiconductor layer, a second single-crystal semiconductor layer formed on the second insulating layer and having a film thickness smaller than a film thickness of the first single-crystal semiconductor layer, a gate electrode formed on the second single-crystal semiconductor layer, and source and drain layers that are formed on the second single-crystal semiconductor layer and arranged on respective sides of the gate electrode.
摘要翻译：半导体器件包括由形成在第一绝缘层上的第一单晶半导体层，形成在第一单晶半导体层上的第二绝缘层构成的背栅电极，形成在第二绝缘层上的第二单晶半导体层并且具有比第一单晶半导体层的膜厚小的膜厚度，形成在第二单晶半导体层上的栅极电极以及形成在第二单晶半导体层上的源极和漏极层，以及布置在栅电极的相应侧上。

6. 发明授权

US06229165B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06229165B1
公开(公告)日：2001-05-08
申请号：US09143510
申请日：1998-08-28
申请人： Tetsushi Sakai , Nobuaki Ieda , Masayuki Ino , Shigeru Nakajima , Yukio Akazawa , Tsuneo Mano , Hiroshi Inokawa
发明人： Tetsushi Sakai , Nobuaki Ieda , Masayuki Ino , Shigeru Nakajima , Yukio Akazawa , Tsuneo Mano , Hiroshi Inokawa
IPC分类号： H01L31062
CPC分类号： H01L27/1443 , H01L27/14812 , H01L31/101
摘要： This invention provides a semiconductor device including a silicon layer, an insulating layer formed on the silicon layer, a first semiconductor device formed on the insulating film to convert light into an electric signal, and a second semiconductor device formed on the insulating film, wherein a silicon region is formed in the silicon layer to shield the second semiconductor device from light, and a through hole extending through the silicon layer except for the silicon region to input light to the first semiconductor device is formed in that portion of the silicon layer corresponding to the lower portions of the first and second semiconductor devices.
摘要翻译：本发明提供一种半导体器件，包括硅层，形成在硅层上的绝缘层，形成在绝缘膜上以将光转换为电信号的第一半导体器件，以及形成在绝缘膜上的第二半导体器件，其中，在硅层中形成硅区域以遮蔽第二半导体器件，并且在对应于第一半导体器件的硅层的部分中形成有通过除了硅区域之外的硅层延伸到第一半导体器件的光的通孔，第一和第二半导体器件的下部。

7. 发明授权

US4780427A Bipolar transistor and method of manufacturing the same 失效
标题翻译：双极晶体管及其制造方法
公开(公告)号：US4780427A
公开(公告)日：1988-10-25
申请号：US104544
申请日：1987-09-29
申请人： Tetsushi Sakai , Yoshiji Kobayashi
发明人： Tetsushi Sakai , Yoshiji Kobayashi
IPC分类号： H01L29/73 , H01L21/033 , H01L21/225 , H01L21/331 , H01L23/532 , H01L29/417 , H01L29/732 , H01L29/70
CPC分类号： H01L29/66272 , H01L21/033 , H01L21/2257 , H01L23/53271 , H01L29/41708 , H01L2924/0002
摘要： A bipolar transistor includes collector, base and emitter regions. The collector region consists of a first semiconductor region of a first conductivity type and formed in contact with a surface of a semiconductor layer. The base region consists of a second semiconductor region of a second conductivity type formed within the collector region to be in contact with the surface of the semiconductor layer. The emitter region consists of a third semiconductor region of the first conductivity type formed within the base region to be in contact with the surface of the semiconductor layer. The transistor also includes collector, base, and emitter electrodes. The collector and base electrodes are connected to the collector and base regions at opposite edges of a single opening formed in a field insulating film covering the surface of the semiconductor layer. The collector and base electrodes consist of a conductor. The emitter electrode is connected to the emitter region and consists of a conductor. The transistor further includes first and second insulating interlayers. The first insulating interlayer is formed between the collector and emitter electrodes. The second insulating interlayer is formed between the emitter and base electrodes. A distance between the collector and emitter electrodes on the surface of the semiconductor layer is substantially the same as that between the emitter and base electrodes.
摘要翻译：双极晶体管包括集电极，基极和发射极区域。集电极区域由第一导电类型的第一半导体区域和半导体层的表面形成。基极区域由形成在集电区域内的第二导电类型的第二半导体区域构成，以与半导体层的表面接触。发射极区由第一导电类型的第三半导体区域形成在基极区内，以与半导体层的表面接触。晶体管还包括集电极，基极和发射极。集电体和基极电极在覆盖半导体层的表面的场绝缘膜中形成的单个开口的相对边缘处连接到集电极和基极区域。集电极和基极由导体组成。发射极电极连接到发射极区域，由导体组成。晶体管还包括第一和第二绝缘夹层。在集电极和发射极之间形成第一绝缘中间层。第二绝缘中间层形成在发射极和基极之间。半导体层表面上的集电极和发射极之间的距离基本上与发射极和基极之间的距离相同。

8. 发明授权

US4128845A Semiconductor integrated circuit devices having inverted frustum-shape contact layers 失效
标题翻译：具有倒立的截头锥形接触层的半导体集成电路器件
公开(公告)号：US4128845A
公开(公告)日：1978-12-05
申请号：US706596
申请日：1976-07-19
申请人： Tetsushi Sakai
发明人： Tetsushi Sakai
IPC分类号： H01L21/3205 , H01L21/225 , H01L21/28 , H01L21/285 , H01L21/306 , H01L21/314 , H01L21/331 , H01L23/532 , H01L29/417 , H01L29/43 , H01L29/73 , H01L29/70 , H01L23/48
CPC分类号： H01L23/53271 , H01L21/2257 , H01L21/28525 , H01L29/417 , H01L2924/0002
摘要： Inverted frustum shaped polycrystalline semiconductor layers are formed on the emitter and collector regions provided on one surface of a semiconductor substrate, and conductor layers are applied on the upper surfaces of the polycrystalline semiconductor surfaces to form emitter and collector electrodes thus providing a bipolar transistor for the integrated circuit device.
摘要翻译：在设置在半导体衬底的一个表面上的发射极和集电极区域上形成倒圆锥形多晶半导体层，并且在多晶半导体表面的上表面上施加导体层以形成发射极和集电极，从而为集成电路器件。

9. 发明申请

US20070126034A1 Semiconductor substrate, semiconductor device and process for producing semiconductor substrate 审中-公开
标题翻译：半导体衬底，半导体器件和用于制造半导体衬底的工艺
公开(公告)号：US20070126034A1
公开(公告)日：2007-06-07
申请号：US10574835
申请日：2004-10-04
申请人： Tetsushi Sakai , Shunichiro Ohmi , Takashi Yamazaki
发明人： Tetsushi Sakai , Shunichiro Ohmi , Takashi Yamazaki
IPC分类号： H01L29/76
CPC分类号： H01L29/78648 , H01L21/76283 , H01L21/823412 , H01L21/84 , H01L27/1203 , H01L29/78603 , H01L29/78606
摘要： An opening 35 is formed on an assembly having a silicon germanium layer 32, a silicon layer 33, and a silicon oxide layer 34 sequentially formed on a silicon basis material 31. An additional silicon oxide layer 36 is formed so as to cover the silicon oxide layer 34 and an inner surface of the opening 35. Then, the silicon germanium layer 32 is removed by etching, and a thermal oxidation treatment and an annealing treatment are sequentially performed on the silicon basis material 31 and the silicon layer 33 to form thermal oxidation layers 37 and 38. Then, a flat film 39 is formed for flat treatment to manufacture a semiconductor substrate 10 having an island part 12 made of silicon buried in an component 13 made of silicon oxide. This allows for easily forming a high-insulation integration CMOSLSI based on inter-element isolation, and sufficiently reducing the SOI layer and the BOX layer in thickness, thereby preventing the short channel effect as well as forming the SOI layer and the BOX layer in multi-layers.
摘要翻译：在硅基材31上依次形成有硅锗层32，硅层33和氧化硅层34的组件上形成开口35。形成另外的氧化硅层36以覆盖氧化硅层34和开口35的内表面。然后，通过蚀刻去除硅锗层32，并且在硅基材料31和硅层33上依次进行热氧化处理和退火处理，以形成热氧化层37和38。然后，形成平坦的膜39，用于平坦处理，以制造半导体衬底10，该半导体衬底10具有埋入由氧化硅制成的部件13中的由硅制成的岛部分12。这允许容易地形成基于元件间隔离的高绝缘集成CMOSLSI，并且使SOI层和BOX层的厚度充分降低，从而防止短沟道效应以及多层SOI层和BOX层的形成地板

10. 发明申请

US20070075317A1 Semiconductor device and semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US20070075317A1
公开(公告)日：2007-04-05
申请号：US11489572
申请日：2006-07-20
申请人： Juri Kato , Hideaki Oka , Kei Kanemoto , Toshiki Hara , Tetsushi Sakai
发明人： Juri Kato , Hideaki Oka , Kei Kanemoto , Toshiki Hara , Tetsushi Sakai
IPC分类号： H01L29/04
CPC分类号： H01L27/1203 , H01L21/84
摘要： A semiconductor device includes a back gate electrode composed of a first single-crystal semiconductor layer formed on a first insulating layer; a second insulating layer formed on the first single-crystal semiconductor layer and having a film thickness smaller than a film thickness of the first insulating layer; a second single-crystal semiconductor layer formed on the second insulating layer; a gate electrode formed on the second single-crystal semiconductor layer; and source and drain layers that are formed on the second single-crystal semiconductor layer and arranged on respective sides of the gate electrode.
摘要翻译：半导体器件包括由形成在第一绝缘层上的第一单晶半导体层构成的背栅电极; 形成在所述第一单晶半导体层上并具有比所述第一绝缘层的膜厚小的膜厚度的第二绝缘层; 形成在所述第二绝缘层上的第二单晶半导体层; 形成在第二单晶半导体层上的栅电极; 以及形成在第二单晶半导体层上并且布置在栅电极的相应侧上的源极和漏极层。

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