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1. 发明申请

US20070018246A1 Semiconductor device and semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US20070018246A1
公开(公告)日：2007-01-25
申请号：US11447926
申请日：2006-06-07
申请人： Juri Kato , Hideaki Oka , Kei Kanemoto , Toshiki Hara , Tetsushi Sakai
发明人： Juri Kato , Hideaki Oka , Kei Kanemoto , Toshiki Hara , Tetsushi Sakai
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/78648
摘要： A semiconductor device includes a back gate electrode composed of a first single-crystal semiconductor layer formed on a first insulating layer, a second insulating layer formed on the first single-crystal semiconductor layer, a second single-crystal semiconductor layer formed on the second insulating layer and having a film thickness smaller than a film thickness of the first single-crystal semiconductor layer, a gate electrode formed on the second single-crystal semiconductor layer, and source and drain layers that are formed on the second single-crystal semiconductor layer and arranged on respective sides of the gate electrode.
摘要翻译：半导体器件包括由形成在第一绝缘层上的第一单晶半导体层，形成在第一单晶半导体层上的第二绝缘层构成的背栅电极，形成在第二绝缘层上的第二单晶半导体层并且具有比第一单晶半导体层的膜厚小的膜厚度，形成在第二单晶半导体层上的栅极电极以及形成在第二单晶半导体层上的源极和漏极层，以及布置在栅电极的相应侧上。

2. 发明申请

US20070075317A1 Semiconductor device and semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US20070075317A1
公开(公告)日：2007-04-05
申请号：US11489572
申请日：2006-07-20
申请人： Juri Kato , Hideaki Oka , Kei Kanemoto , Toshiki Hara , Tetsushi Sakai
发明人： Juri Kato , Hideaki Oka , Kei Kanemoto , Toshiki Hara , Tetsushi Sakai
IPC分类号： H01L29/04
CPC分类号： H01L27/1203 , H01L21/84
摘要： A semiconductor device includes a back gate electrode composed of a first single-crystal semiconductor layer formed on a first insulating layer; a second insulating layer formed on the first single-crystal semiconductor layer and having a film thickness smaller than a film thickness of the first insulating layer; a second single-crystal semiconductor layer formed on the second insulating layer; a gate electrode formed on the second single-crystal semiconductor layer; and source and drain layers that are formed on the second single-crystal semiconductor layer and arranged on respective sides of the gate electrode.
摘要翻译：半导体器件包括由形成在第一绝缘层上的第一单晶半导体层构成的背栅电极; 形成在所述第一单晶半导体层上并具有比所述第一绝缘层的膜厚小的膜厚度的第二绝缘层; 形成在所述第二绝缘层上的第二单晶半导体层; 形成在第二单晶半导体层上的栅电极; 以及形成在第二单晶半导体层上并且布置在栅电极的相应侧上的源极和漏极层。

3. 发明申请

US20060060921A1 Semiconductor substrate, semiconductor device, method of manufacturing semiconductor substrate, and method of manufacturing semiconductor device 失效
标题翻译：半导体衬底，半导体器件，半导体衬底的制造方法以及半导体器件的制造方法
公开(公告)号：US20060060921A1
公开(公告)日：2006-03-23
申请号：US11212400
申请日：2005-08-26
申请人： Teruo Takizawa , Kei Kanemoto , Juri Kato , Toshiki Hara
发明人： Teruo Takizawa , Kei Kanemoto , Juri Kato , Toshiki Hara
IPC分类号： H01L27/12
CPC分类号： H01L29/66772 , H01L29/78654
摘要： A semiconductor substrate includes a first semiconductor layer that is formed on a semiconductor base substrate, a second semiconductor layer that is formed on the first semiconductor layer and that has an etching selection ratio smaller than that of the first semiconductor layer, a cavity portion that is formed below the second semiconductor layer by removing a portion of the first semiconductor layer, a thermal oxidation film that is formed on the surface of the second semiconductor layer in the cavity portion, and a buried insulating film that is buried in the cavity portion.
摘要翻译：半导体衬底包括形成在半导体基底衬底上的第一半导体层，形成在第一半导体层上并具有小于第一半导体层的蚀刻选择比的蚀刻选择比的第二半导体层，通过去除第一半导体层的一部分而形成在第二半导体层的下方，形成在空腔部分中的第二半导体层的表面上的热氧化膜和埋在空腔部分中的埋入绝缘膜。

4. 发明授权

US07271447B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07271447B2
公开(公告)日：2007-09-18
申请号：US11212400
申请日：2005-08-26
申请人： Teruo Takizawa , Kei Kanemoto , Juri Kato , Toshiki Hara
发明人： Teruo Takizawa , Kei Kanemoto , Juri Kato , Toshiki Hara
IPC分类号： H01L27/01
CPC分类号： H01L29/66772 , H01L29/78654
摘要： A semiconductor substrate includes a first semiconductor layer that is formed on a semiconductor base substrate, a second semiconductor layer that is formed on the first semiconductor layer and that has an etching selection ratio smaller than that of the first semiconductor layer, a cavity portion that is formed below the second semiconductor layer by removing a portion of the first semiconductor layer, a thermal oxidation film that is formed on the surface of the second semiconductor layer in the cavity portion, and a buried insulating film that is buried in the cavity portion.
摘要翻译：半导体衬底包括形成在半导体基底衬底上的第一半导体层，形成在第一半导体层上并具有小于第一半导体层的蚀刻选择比的蚀刻选择比的第二半导体层，通过去除第一半导体层的一部分而形成在第二半导体层的下方，形成在空腔部分中的第二半导体层的表面上的热氧化膜和埋在空腔部分中的埋入绝缘膜。

5. 发明授权

US07465641B2 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07465641B2
公开(公告)日：2008-12-16
申请号：US11393211
申请日：2006-03-29
申请人： Toshiki Hara , Kei Kanemoto
发明人： Toshiki Hara , Kei Kanemoto
IPC分类号： H01L21/76
CPC分类号： H01L21/84 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L23/544 , H01L27/1203 , H01L29/78684 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Manufacturing a semiconductor device by removing the insulation film in an alignment mark-forming region, depositing a first semiconductor layer, removing the insulation film on the semiconductor substrate after the second semiconductor layer is formed, forming a first exposing region for exposing the semiconductor substrate through the second semiconductor layer and the first semiconductor layer with reference to the second semiconductor layer in the alignment mark-forming region as a first alignment mark for positioning, while forming, on the semiconductor substrate, a second alignment mark, forming a second exposing region for exposing the first semiconductor layer by using the second alignment mark as a reference for positioning, forming a cavity and forming a buried insulation layer in the cavity, and forming a first grate electrode by using the second alignment mark as a reference for positioning.
摘要翻译：通过去除对准标记形成区域中的绝缘膜来制造半导体器件，沉积第一半导体层，在形成第二半导体层之后去除半导体衬底上的绝缘膜，形成用于使半导体衬底通过的第一暴露区域第二半导体层和第一半导体层相对于对准标记形成区域中的第二半导体层，作为第一对准标记，用于在半导体衬底上形成第二对准标记，同时在半导体衬底上形成用于定位的第二对准标记，形成用于通过使用第二对准标记作为用于定位，形成空腔并在空腔中形成掩埋绝缘层的参考来暴露第一半导体层，并且通过使用第二对准标记作为定位的参考来形成第一栅格电极。

6. 发明申请

US20060223271A1 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US20060223271A1
公开(公告)日：2006-10-05
申请号：US11393211
申请日：2006-03-29
申请人： Toshiki Hara , Kei Kanemoto
发明人： Toshiki Hara , Kei Kanemoto
IPC分类号： H01L21/336 , H01L21/8222 , H01L21/331 , H01L21/00
CPC分类号： H01L21/84 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L23/544 , H01L27/1203 , H01L29/78684 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Manufacturing a semiconductor device by removing the insulation film in an alignment mark-forming region, depositing a first semiconductor layer, removing the insulation film on the semiconductor substrate after the second semiconductor layer is formed, forming a first exposing region for exposing the semiconductor substrate through the second semiconductor layer and the first semiconductor layer with reference to the second semiconductor layer in the alignment mark-forming region as a first alignment mark for positioning, while forming, on the semiconductor substrate, a second alignment mark, forming a second exposing region for exposing the first semiconductor layer by using the second alignment mark as a reference for positioning, forming a cavity and forming a buried insulation layer in the cavity, and forming a first grate electrode by using the second alignment mark as a reference for positioning.
摘要翻译：通过去除对准标记形成区域中的绝缘膜来制造半导体器件，沉积第一半导体层，在形成第二半导体层之后去除半导体衬底上的绝缘膜，形成用于使半导体衬底通过的第一暴露区域所述第二半导体层和所述第一半导体层相对于所述对准标记形成区域中的所述第二半导体层，作为用于定位的第一对准标记，同时在所述半导体衬底上形成第二对准标记，形成用于通过使用第二对准标记作为用于定位，形成空腔并在空腔中形成掩埋绝缘层的参考来暴露第一半导体层，并且通过使用第二对准标记作为定位的参考来形成第一栅格电极。

7. 发明授权

US07592208B2 Method for manufacturing semiconductor substrate and method for manufacturing semiconductor apparatus and photomask 失效
标题翻译：半导体基板的制造方法及半导体装置及光掩模的制造方法
公开(公告)号：US07592208B2
公开(公告)日：2009-09-22
申请号：US11465366
申请日：2006-08-17
申请人： Toshiki Hara
发明人： Toshiki Hara
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L29/66772 , H01L29/78615 , H01L29/78654
摘要： A method for manufacturing a semiconductor substrate, includes: forming a first semiconductor layer on a semiconductor base material; forming a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having an etching selectivity larger than that of the first semiconductor layer; forming, at the second semiconductor layer and the first semiconductor layer in the vicinity of an element region, at least three or more hole portions for exposing the semiconductor base material; forming, on the semiconductor base material, a supporting body for supporting the second semiconductor layer on the semiconductor base material so that the hole portions are filled and the second semiconductor layer is covered; etching the supporting body at regions other than predetermined regions including the hole portions and the element region to form an aperture plane in the supporting body, the aperture plane exposes a part of an end section of the first semiconductor layer; etching the first semiconductor layer via the aperture plane to form a hollow section between the second semiconductor layer of the element region and the semiconductor base material; and forming an insulation film in the hollow section. The hole portions are formed so that at least two or more the hole portions are formed in one direction of the element region and at least one or more the hole(s) is/are formed in the other direction crossing the one direction of the element region.
摘要翻译：一种制造半导体衬底的方法，包括：在半导体基底材料上形成第一半导体层; 在所述第一半导体层上形成第二半导体层，所述第二半导体层的蚀刻选择性大于所述第一半导体层的蚀刻选择性; 在元件区域附近的第二半导体层和第一半导体层处形成用于使半导体基材露出的至少三个以上的孔部; 在所述半导体基材上形成用于将所述第二半导体层支撑在所述半导体基材上的支撑体，使得所述孔部被填充并且覆盖所述第二半导体层; 在除了包括孔部分和元件区域的预定区域之外的区域处蚀刻支撑体以在支撑体中形成孔平面，孔径平面暴露第一半导体层的端部的一部分; 通过孔平面蚀刻第一半导体层，以在元件区域的第二半导体层和半导体基底材料之间形成中空部分; 并在中空部分形成绝缘膜。孔部形成为使得在元件区域的一个方向上形成有至少两个以上的孔部，并且在与元件的一个方向交叉的另一方向上形成有至少一个以上的孔地区。

8. 发明授权

US07534687B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07534687B2
公开(公告)日：2009-05-19
申请号：US11486555
申请日：2006-07-13
申请人： Toshiki Hara
发明人： Toshiki Hara
IPC分类号： H01L21/84
CPC分类号： H01L29/1083 , H01L29/06 , H01L29/7834
摘要： A semiconductor device, comprises: a transistor having structured to include a gate electrode formed on a semiconductor layer on a semiconductor substrate via a gate insulating film, and a source layer and a drain layer formed on the semiconductor layer sandwiching the gate electrode; a hollow portion existing between the source layer and the semiconductor substrate, and between the drain layer and the semiconductor substrate, respectively; and the hollow portion in absence between the semiconductor layer under the gate electrode and the semiconductor substrate.
摘要翻译：一种半导体器件，包括：晶体管，其被构造为包括通过栅极绝缘膜形成在半导体衬底上的半导体层上的栅电极，以及形成在夹持栅电极的半导体层上的源极层和漏极层; 存在于源极层和半导体衬底之间以及漏极层和半导体衬底之间的中空部分; 以及在栅电极下半导体层与半导体基板之间不存在的中空部分。

9. 发明授权

US08567919B2 Piezoelectric element, piezoelectric actuator, liquid ejecting head, and liquid ejecting apparatus 有权
标题翻译：压电元件，压电致动器，液体喷射头和液体喷射装置
公开(公告)号：US08567919B2
公开(公告)日：2013-10-29
申请号：US12880295
申请日：2010-09-13
申请人： Koichi Morozumi , Toshiki Hara , Jiro Kato , Satoshi Denda
发明人： Koichi Morozumi , Toshiki Hara , Jiro Kato , Satoshi Denda
IPC分类号： B41J2/045 , H01L41/18 , H01L41/187 , C04B35/495 , C04B35/00
CPC分类号： B41J2/14233 , H01L41/1876
摘要： A piezoelectric element includes a first conductive layer, a second conductive layer facing the first conductive layer, and a piezoelectric layer between the first and second conductive layers, composed of a compound oxide containing at least lead, zirconium, titanium, and oxygen. The piezoelectric layer includes a first crystal layer on the first conductive layer side of the piezoelectric layer and a second crystal layer continued from the first crystal layer, nearer to the second conductive layer side than the first crystal layer. In the piezoelectric layer, the lead concentration in the first conductive layer side of the first crystal layer is lower than that in the second conductive layer side of the second crystal layer. In the piezoelectric layer, the oxygen concentration in the first conductive layer side of the first crystal layer is higher than that in the second conductive layer side of the second crystal layer.
摘要翻译：压电元件包括第一导电层，与第一导电层相对的第二导电层，以及由至少含有铅，锆，钛和氧的复合氧化物构成的第一和第二导电层之间的压电层。压电层包括在压电层的第一导电层侧上的第一晶体层和从第一晶体层延续的第二晶体层，比第一晶体层更靠近第二导电层侧。在压电层中，第一晶体层的第一导电层侧的引线浓度低于第二晶体层的第二导电层侧的引线浓度。在压电层中，第一结晶层的第一导电层侧的氧浓度高于第二结晶层的第二导电层侧的氧浓度。

10. 发明申请

US20070296000A1 Method for manufacturing a semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：US20070296000A1
公开(公告)日：2007-12-27
申请号：US11818688
申请日：2007-06-15
申请人： Toshiki Hara
发明人： Toshiki Hara
IPC分类号： H01L27/10 , H01L29/74
CPC分类号： H01L29/66772 , H01L29/0649
摘要： A method for manufacturing a semiconductor device, includes: partially forming an epitaxial growth stopper film on a single crystal semiconductor substrate; sequentially depositing a first semiconductor layer and a second semiconductor layer on the semiconductor substrate by an epitaxial growth process; forming a first groove penetrating through the second semiconductor layer and the first semiconductor layer on the semiconductor substrate, at a region inside from an outer peripheral portion of the epitaxial growth stopper film, by partially etching the second semiconductor layer and the first semiconductor layer; forming a support body film on an entire surface of the semiconductor substrate, so as to fill the first groove and cover the second semiconductor layer; forming a support body in a shape covering the second semiconductor layer from the first groove to an element region extending over the outer peripheral portion of the epitaxial growth stopper film, by partially etching the support body film; forming a second groove exposing a side surface of the first semiconductor layer, by sequentially etching the second semiconductor layer and the first semiconductor layer exposing from under the support body; forming a hollow portion between the semiconductor substrate and the second semiconductor layer, by selectively etching the first semiconductor layer interposing the second groove therebetween, under an etching condition that the first semiconductor layer is easier to etch than the second semiconductor layer; and forming an insulating layer in the hollow portion.
摘要翻译：一种制造半导体器件的方法，包括：在单晶半导体衬底上部分地形成外延生长阻挡膜; 通过外延生长工艺在半导体衬底上依次沉积第一半导体层和第二半导体层; 通过部分地蚀刻所述第二半导体层和所述第一半导体层，在所述外延生长阻挡膜的外周部的内侧形成穿过所述第二半导体层和所述半导体基板上的所述第一半导体层的第一沟槽; 在所述半导体衬底的整个表面上形成支撑体膜，以填充所述第一沟槽并覆盖所述第二半导体层; 通过部分地蚀刻所述支撑体膜，从覆盖所述第二半导体层的形状形成覆盖所述第二半导体层的形状的支撑体，所述支撑体从所述第一槽到所述外延生长阻挡膜的外周部延伸的元件区域; 通过依次蚀刻第二半导体层和从支撑体下方露出的第一半导体层，形成露出第一半导体层的侧表面的第二沟槽; 在所述第一半导体层比所述第二半导体层更容易蚀刻的蚀刻条件下，通过选择性地蚀刻插入所述第二沟槽的第一半导体层，在所述半导体衬底和所述第二半导体层之间形成中空部分; 以及在所述中空部分中形成绝缘层。

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