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1. 发明授权

US5847995A Nonvolatile semiconductor memory device having a plurality of blocks provided on a plurality of electrically isolated wells 失效
标题翻译：具有设置在多个电隔离的井上的多个块的非易失性半导体存储器件
公开(公告)号：US5847995A
公开(公告)日：1998-12-08
申请号：US852354
申请日：1997-05-07
申请人： Shinichi Kobayashi , Shinji Kawai , Tadashi Omae , Makoto Oi , Akinori Matsuo , Masashi Wada , Kenji Kozakai
发明人： Shinichi Kobayashi , Shinji Kawai , Tadashi Omae , Makoto Oi , Akinori Matsuo , Masashi Wada , Kenji Kozakai
IPC分类号： G11C17/00 , G11C16/06 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/78
摘要： The inventive DINOR flash memory includes a plurality of blocks, a spare block and a spare word line block, which are formed on a plurality of electrically isolated P-type wells. When a word line-to-well short-circuit takes place in a certain block and another block is selected, the block causing the word line-to-well short-circuit is brought into a non-selected state. Thus, no leakage takes place in the block causing the word line-to-well short-circuit, to exert no bad influence on the selected block.
摘要翻译：本发明的DINOR闪速存储器包括形成在多个电隔离P型阱上的多个块，备用块和备用字线块。当在某个块中发生字线对阱短路并且选择另一个块时，导致字线对阱短路的块被带入非选择状态。因此，在导致字线到阱短路的块中不发生泄漏，对所选择的块不会产生不良影响。

2. 发明授权

US5852583A Semiconductor memory device that can realize high speed data read out 失效
标题翻译：可实现高速数据读出的半导体存储器件
公开(公告)号：US5852583A
公开(公告)日：1998-12-22
申请号：US848391
申请日：1997-05-08
申请人： Yasuhiko Taito , Shinji Kawai , Shinichi Kobayashi , Akinori Matsuo , Masashi Wada
发明人： Yasuhiko Taito , Shinji Kawai , Shinichi Kobayashi , Akinori Matsuo , Masashi Wada
IPC分类号： G11C17/00 , G11C8/08 , G11C16/06 , G11C8/00
CPC分类号： G11C8/08
摘要： Following latching of a word line select signal by a latch circuit, a transfer gate is turned off. When a word line is selected, the voltage applied to the latch circuit is shifted to a desired level to apply a desired voltage to the word line from a word line driver. As a result, a predecode signal is applied to a small size buffering circuit to be transmitted to the word line driver at a potential level between Vcc-GND. Therefore, the parasitic capacitance accompanying a predecode signal is reduced.
摘要翻译：在通过锁存电路锁存字线选择信号之后，转移门被关闭。当选择字线时，施加到锁存电路的电压被移动到期望的电平，以从字线驱动器向字线施加期望的电压。结果，将预解码信号施加到小尺寸缓冲电路，以在Vcc-GND之间的电位电平发送到字线驱动器。因此，伴随预解码信号的寄生电容减少。

3. 发明授权

US06512398B1 Semiconductor integrated circuit device having reference voltage generating section 失效
标题翻译：具有参考电压产生部分的半导体集成电路器件
公开(公告)号：US06512398B1
公开(公告)日：2003-01-28
申请号：US09572443
申请日：2000-05-17
申请人： Hirofumi Sonoyama , Yoshiki Kawajiri , Masashi Wada , Jun Eto , Shinji Kawai
发明人： Hirofumi Sonoyama , Yoshiki Kawajiri , Masashi Wada , Jun Eto , Shinji Kawai
IPC分类号： G01R1900
CPC分类号： G11C5/143 , G01R19/16552 , G05F3/242 , G11C16/30
摘要： The reliability of a semiconductor integrated circuit device is remarkably improved by minimizing the fluctuations of the detection level of the supply voltage due to the manufacturing process and/or other factors. In the semiconductor integrated circuit device according to the invention, a differential amplifier circuit SA amplifies the differential voltage representing the difference between the reference voltage VREF generated by a reference voltage generating section 16 and the detection voltage obtained by dividing a supply voltage VCC by means of resistors 27 and 28 and outputs it as a detection signal K. The reference voltage generating section 16 generates reference voltage VREF from the base-emitter voltage of a bipolar transistor that is minimally affected by temperature and the manufacturing process so that the fluctuations of the detection level of the supply voltage VCC can be minimized.
摘要翻译：通过最小化由于制造过程和/或其他因素导致的电源电压的检测水平的波动，可以显着提高半导体集成电路器件的可靠性。在根据本发明的半导体集成电路器件中，差分放大器电路SA放大表示由参考电压产生部分16产生的参考电压VREF与由电源电压VCC分压所获得的检测电压之间的差异的差分电压，电阻器27和28并将其输出作为检测信号K.参考电压产生部分16从由温度和制造过程影响最小的双极晶体管的基极 - 发射极电压产生参考电压VREF，使得检测的波动电源电压VCC的电平可以最小化。

4. 发明授权

US5828604A Non-volatile semiconductor memory device having large margin of readout operation for variation in external power supply voltage 失效
标题翻译：具有用于外部电源电压变化的大量读出余量的非易失性半导体存储器件
公开(公告)号：US5828604A
公开(公告)日：1998-10-27
申请号：US781247
申请日：1997-01-10
申请人： Shinji Kawai , Shinichi Kobayashi , Yasuhiko Taito
发明人： Shinji Kawai , Shinichi Kobayashi , Yasuhiko Taito
IPC分类号： G11C17/00 , G11C16/06 , G11C16/30 , G11C16/34 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/30 , G11C16/3454
摘要： In a confirmation operation of write data after writing data into a memory cell transistor (a verify operation), a verify potential generation circuit supplies a verify potential VPVRFY to the control gate of a memory transistor. Verify potential VPVRFY is determined depending upon the resistance ratio of variable resistors and a value of a constant current supplied from a constant current source circuit. According to reduction of a power supply potential, potential VPVRFY is decreased. The conductance of a memory cell transistor is adjusted according to variation in a detection sensitivity of a sense amplifier according to variation in the power supply potential, whereby the cell threshold value after a write operation takes a constant value.
摘要翻译：在将数据写入存储单元晶体管（验证操作）之后的写入数据的确认操作中，验证电位产生电路将验证电位VPVRFY提供给存储晶体管的控制栅极。验证电位VPVRFY取决于可变电阻器的电阻比和从恒流源电路提供的恒定电流值。根据电源电位的降低，电位VPVRFY减小。根据电源电位的变化，根据读出放大器的检测灵敏度的变化来调整存储单元晶体管的电导，由此写操作之后的单元阈值为常数。

5. 发明授权

US06243292B1 Nonvolatile semiconductor memory device capable of reducing memory array area 有权
标题翻译：能够减少存储器阵列区域的非易失性半导体存储器件
公开(公告)号：US06243292B1
公开(公告)日：2001-06-05
申请号：US09613691
申请日：2000-07-10
申请人： Shinichi Kobayashi , Yoshikazu Miyawaki , Shinji Kawai , Tomoshi Futatsuya
发明人： Shinichi Kobayashi , Yoshikazu Miyawaki , Shinji Kawai , Tomoshi Futatsuya
IPC分类号： G11C700
CPC分类号： H01L27/115 , G11C16/26 , G11C16/30 , G11C16/3436
摘要： A memory cell array is divided into a plurality of memory cell blocks each collectively subjected to an erasing operation as a unit. A P well regions for memory cell transistors and an N well region for electrically separating the P well regions are provided. Select transistors are formed in the same P well region as the memory cell transistor connected to the corresponding sub bit line of P well regions.
摘要翻译：存储单元阵列被分成以共同作为单位进行擦除操作的多个存储单元块。提供存储单元晶体管的P阱区和用于电分离P阱区的N阱区。选择晶体管形成在与连接到P阱区域的对应子位线的存储单元晶体管相同的P阱区域中。

6. 发明授权

US06458944B1 Human BMP-4 promoter and method for exploring bone-related substance by using the same 失效
标题翻译：人类BMP-4启动子和通过使用相同物质探索骨相关物质的方法
公开(公告)号：US06458944B1
公开(公告)日：2002-10-01
申请号：US09674460
申请日：2000-11-30
申请人： Shinji Kawai , Takeyuki Sugiura
发明人： Shinji Kawai , Takeyuki Sugiura
IPC分类号： C07H2104
CPC分类号： C07K14/51
摘要： The present invention provides a method for exploring low molecular weight compounds which regulate positively or negatively the expression of human BMP-4 with reference to a reporter activity by using 5′ upstream region gene containing the human BMP-4 promoter and an animal cell introduced with a recombinant expression vector that has been connected to an appropriate reporter gene. The low molecular weight compounds and their derivatives obtained by the present method have morphogenetic activity and inhibiting activity for bone and cartilage through the expression of human BMP-4 and are useful as preventive or therapeutic agents for cartilage and bone diseases.
摘要翻译：本发明提供一种探索通过使用含有人BMP-4启动子的5'上游区域基因和引入了人BMP-4启动子的动物细胞参照报告基因活性来调节人BMP-4表达的低分子量化合物的方法已经连接到适当报道基因的重组表达载体。通过本发明方法获得的低分子化合物及其衍生物通过人BMP-4的表达具有形态发生活性和对骨和软骨的抑制活性，并且可用作软骨和骨疾病的预防或治疗剂。

7. 发明授权

US5249155A Semiconductor device incorporating internal voltage down converting circuit 失效
标题翻译：包含内部电压降低转换电路的半导体器件
公开(公告)号：US5249155A
公开(公告)日：1993-09-28
申请号：US819208
申请日：1992-01-10
申请人： Kazutami Arimoto , Hideto Hidaka , Mikio Asakura , Masanori Hayashikoshi , Masaki Tsukude , Shinji Kawai , Tsukasa Ooishi
发明人： Kazutami Arimoto , Hideto Hidaka , Mikio Asakura , Masanori Hayashikoshi , Masaki Tsukude , Shinji Kawai , Tsukasa Ooishi
IPC分类号： H01L21/8234 , G05F1/46 , G11C5/14 , G11C11/401 , G11C11/403 , G11C11/407 , G11C11/409 , H01L21/822 , H01L21/8244 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/11 , H03K17/30
CPC分类号： H03K17/302 , G05F1/465 , G11C5/147 , H01L2924/0002
摘要： An n channel driver circuit comprised of an N channel MOS transistor is provided in parallel to a driver circuit comprised of a P channel MOS transistor. Normally, n channel driver circuit supplies an internal supply voltage, to activate driver circuit only at the time of current peak. Thus, an insufficient capability of n.sup.- channel driver circuit to supply current is supplemented.
摘要翻译：由N沟道MOS晶体管构成的n沟道驱动电路与由P沟道MOS晶体管构成的驱动电路并联设置。通常，n通道驱动电路提供内部电源电压，仅在当前峰值时激活驱动电路。因此，补充了n沟道驱动电路不足以提供电流的能力。

8. 发明授权

US5177375A Power on reset circuit for semiconductor integrated circuit device 失效
标题翻译：用于半导体集成电路器件的上电复位电路
公开(公告)号：US5177375A
公开(公告)日：1993-01-05
申请号：US628696
申请日：1990-12-14
申请人： Toshiyuki Ogawa , Shinji Kawai
发明人： Toshiyuki Ogawa , Shinji Kawai
IPC分类号： G11C11/401 , G06F1/24 , G11C11/41 , H01L27/10
CPC分类号： G06F1/24
摘要： A semiconductor integrated circuit device comprising an internal reset circuit generating one shot pulse for resetting an internal circuit upon a power on. In the internal reset circuit, inputted to a two-input NOR gate are an output potential of an inverter inverting a first node coupled to a power supply through a capacitor, and an internal clock signal which level inverts at a predetermined timing after rising to a "H" level upon the power on. Then, the output of the NOR gate is applied to a second node in an internal circuit to be reset. The internal reset circuit outputs one shot pulses synchronizing with the first fall of the internal clock signal after the power on irrespective of a potential change rate of the first node after the power on. The first node is set to more easily attain a "H" level than the second node to be reset to a "L" level at the power on by adjusting characteristics of circuit elements connected to the first node and those of circuit elements connected to the second node. As a result, the second node is set to be without fail at a "L" level requiring no resetting when the inverted potential of the first node has a value allowing a generation of one shot pulses at the NOR gate, thereby preventing malfunction of the internal circuit due to erroneous resetting.
摘要翻译：一种半导体集成电路器件，包括内部复位电路，其产生用于在通电时复位内部电路的单次脉冲。在内部复位电路中，输入到双输入或非门的是逆变器，其通过电容器与耦合到电源的第一节点反相，以及内部时钟信号，该电平在上升至 “H”级上电。然后，NOR门的输出被施加到要复位的内部电路中的第二节点。在电源接通之后，内部复位电路输出与内部时钟信号的第一次下降同步的单触发脉冲，而与上电之后第一节点的电位变化率无关。第一节点被设置为通过调节连接到第一节点的电路元件的特性和连接到第一节点的电路元件的特性，使得能够更容易地达到“H”电平而不是第二节点在上电时被重置为“L”电平第二个节点。结果，当第一节点的反相电位具有允许在或非门产生单次脉冲的值时，第二节点被设置为“L”电平而不需要复位，从而防止第内部电路由于错误的复位而导致。

9. 发明授权

US5146429A Semiconductor memory device including a redundancy circuitry for repairing a defective memory cell and a method for repairing a defective memory cell 失效
标题翻译：包括用于修复有缺陷的存储单元的冗余电路的半导体存储器件以及用于修复有缺陷的存储器单元的方法
公开(公告)号：US5146429A
公开(公告)日：1992-09-08
申请号：US617737
申请日：1990-11-26
申请人： Shinji Kawai , Shigeru Mori , Shigeru Kikuda
发明人： Shinji Kawai , Shigeru Mori , Shigeru Kikuda
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04
CPC分类号： G11C29/848
摘要： A semicondcutor memory device includes an array of a plurality of memory cells arranged in a matrix manner, and a row or column decoder responsive to an external address signal for generating a row or column selecting signal. The memory cell array comprises (n+1) rows or columns. The row or column decoder comprises n output nodes. Transmission gates are provided between the decoder output node and row lines or column selecting lines for connecting each output node and each row line or column selecting line. The transmission gates are formed of a pair of CMOS transmission gates, whereby one output node is connected to two adjacent row lines or column selecting lines. This memory device further includes a circuit defining the connection manner of the transmission gate. This defining circuit turns one pair of CMOS transmission gates ON and OFF complementally. When there is a defective memory cell, the decoder output nodes are grouped into a first group including the output node corresponding to the faulty row or column having the defective memory cell, and a second group formed of the remaining output nodes. The defining circuit applies control signals to the CMOS transmission gates so that the ON/OFF states of the CMOS transmission gate pair related to the first group of output nodes and the CMOS transmission gate pair related to the second group of output node differ. The memory device further includes switching devices provided corresponding to each row line or column selecting line, responsive to the control signal from the defining cirucit to be turned on/off. This switching device connects only the faulty row line or the faulty column selecting line to the reference potential fixedly.
摘要翻译：半切割器存储器件包括以矩阵方式布置的多个存储器单元的阵列，以及响应于用于产生行或列选择信号的外部地址信号的行或列解码器。存储单元阵列包括（n + 1）行或列。行或列解码器包括n个输出节点。在解码器输出节点和用于连接每个输出节点和每行行或列选择线的行线或列选择线之间提供传输门。传输门由一对CMOS传输门形成，其中一个输出节点连接到两个相邻的行线或列选择线。该存储装置还包括限定传输门的连接方式的电路。该定义电路互补地将一对CMOS传输门ON和OFF。当存在有缺陷的存储器单元时，解码器输出节点被分组为包括与具有缺陷存储单元的故障行或列相对应的输出节点的第一组，以及由剩余输出节点形成的第二组。定义电路将控制信号施加到CMOS传输门，使得与第一组输出节点相关的CMOS传输门对的ON / OFF状态和与第二组输出节点相关的CMOS传输门对不同。存储器件还包括响应于来自定义电路的控制信号而被打开/关闭而对应于每行行或列选择线提供的开关装置。该开关装置仅将故障行线或故障列选择线固定为参考电位。

10. 发明授权

US4551868A Washing device for parts of body 失效
标题翻译：身体部位清洗装置
公开(公告)号：US4551868A
公开(公告)日：1985-11-12
申请号：US539751
申请日：1983-10-06
申请人： Shinji Kawai , Yuji Yamaguchi , Koichi Suzuki , Hisanobu Takeda
发明人： Shinji Kawai , Yuji Yamaguchi , Koichi Suzuki , Hisanobu Takeda
IPC分类号： A61M3/02 , E03D9/08 , A61H35/00
CPC分类号： E03D9/08
摘要： In a washing device for parts of body including first cylinder means comprising a first cylinder and a first piston to be operated in the front end direction thereof by introducing pressurized water onto the first cylinder and a second piston to be operated in the front end direction thereof by introducing pressurized water into the second cylinder; pressurized water control means for selectively supplying pressurized water to both of the first and second cylinders, or to any one of them; and pressurized water supply means for supplying pressurized water to the pressurized water control means: the washing device further including sensor means for sensing that any one of the first and second pistons is operated over a predetermined operating position in the front end direction thereof. As one aspect of the invention, the pressurized water control means may be provided with a control member for controlling a supply amount pressurized water and which member is operated based on an input signal of the sensor means to supply a small amount of pressurized water. While, as another aspect of the invention, the pressurized water supply means may comprise pump means the capacity of which is variable to vary the capacity of pump means so as to reduce based on an input signal in the sensor means. The washing device of this invention can spout a weaken fountain for the purpose of bidet-washing with reliability, while it can spout an intensive fountain for the purpose of anus-washing. Also, there is no fear that a person who undergoes the anus or bidet-washing feels unpleasant.
摘要翻译：一种用于主体部件的清洗装置，包括第一气缸装置，该第一气缸装置包括第一气缸和通过将加压水引入第一气缸而在其前端方向上操作的第一活塞，以及在其前端方向上操作的第二活塞通过将加压水引入第二气缸; 加压水控制装置，用于选择性地将加压水供应到第一和第二气缸或它们中的任何一个; 以及用于向加压水控制装置供给加压水的加压供水装置，所述洗涤装置还包括用于感测所述第一活塞和所述第二活塞中的任一个在其前端方向上在预定操作位置上操作的传感器装置。作为本发明的一个方面，加压水控制装置可以设置有用于控制供给量的加压水的控制构件，并且基于传感器装置的输入信号来操作构件以供应少量的加压水。而作为本发明的另一方面，加压水供应装置可以包括泵装置，其能力是可变的以改变泵装置的容量，以便基于传感器装置中的输入信号而减小。本发明的洗涤装置可以以可靠的方式喷出柔软的喷泉，同时可以喷出强化喷泉以进行肛门清洗。另外，不用担心接触肛门或坐浴盆的人感到不愉快。

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