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1. 发明授权

US5061925A Phase equalization system for a digital-to-analog converter utilizing separate digital and analog sections 失效
标题翻译：使用单独的数字和模拟部分的数模转换器的相位均衡系统
公开(公告)号：US5061925A
公开(公告)日：1991-10-29
申请号：US571376
申请日：1990-08-22
申请人： Navdeep S. Sooch , Donald A. Kerth , Eric J. Swanson , Tetsurou Sugimoto
发明人： Navdeep S. Sooch , Donald A. Kerth , Eric J. Swanson , Tetsurou Sugimoto
IPC分类号： H03M1/66 , H03H17/00 , H03H17/02 , H03H17/06 , H03M3/02 , H03M7/00 , H03M7/32
CPC分类号： H03M3/37 , H03M3/50 , H03M7/3028 , H03M7/3035 , H03M7/3037
摘要： A phase equalization system for a digital-to-analog converter (DAC) includes a digital portion (10) having an interpolation section (14) for receiving a digital input and increasing the sampling frequency thereof for input to a delta-sigma modulator (16). A summing junction (24) is disposed between the interpolation circuit (14) and the delta-sigma modudlator (16) to allow an offset voltage to be summed therewith. This provides for D.C. offset, this offset being controlled by a calibration control (40). The output of the digital section (10) is input in an analog section (12), which has a one-bit DAC 21) that is input to an analog filter (22) for converting and filtering the one-bit digital stream output by the delta-sigma modulator (16). The interpolation circuit (14) includes a three stage interpolation filter comprising a first stage (50), a second stage (52) and a third stage (54). The second stage (52) is comprised of a finite impulse response filter (FIR) that has a nonlinear phase response. The nonlinear phase response of the interpolation filter (52) compensates for the phase deviation of the analog filter (22) from a linear phase response. Therefore, the composite phase provided by the combination of the phase equalization in the digital section (10) and the phase nonlinearity in the analog section (12) will result in a linear overall phase relationship for the DAC.
摘要翻译：用于数模转换器（DAC）的相位均衡系统包括具有插值部分（14）的数字部分（10），用于接收数字输入并增加其采样频率以输入到Δ-Σ调制器（16 ）。在插值电路（14）和Δ-Σ调制器（16）之间设置加法结（24），以允许偏移电压与其相加。这提供直流偏移，该偏移由校准控制（40）控制。数字部分（10）的输出被输入到模拟部分（12）中，模拟部分（12）具有一个比特DAC21），该模拟部分（12）被输入到模拟滤波器（22），用于转换和滤波由 Δ-Σ调制器（16）。内插电路（14）包括三级内插滤波器，包括第一级（50），第二级（52）和第三级（54）。第二级（52）由具有非线性相位响应的有限脉冲响应滤波器（FIR）组成。内插滤波器（52）的非线性相位响应补偿模拟滤波器（22）与线性相位响应的相位偏差。因此，通过数字部分（10）中的相位均衡和模拟部分（12）中的相位非线性的组合提供的复合相位将导致DAC的线性整体相位关系。

2. 发明授权

US5079550A Combining continuous time and discrete time signal processing in a delta-sigma modulator 失效
标题翻译：在Δ-Σ调制器中组合连续时间和离散时间信号处理
公开(公告)号：US5079550A
公开(公告)日：1992-01-07
申请号：US428396
申请日：1989-10-27
申请人： Navdeep S. Sooch , Donald A. Kerth , Bruce P. Del Signore , Eric J. Swanson
发明人： Navdeep S. Sooch , Donald A. Kerth , Bruce P. Del Signore , Eric J. Swanson
IPC分类号： H03M3/02
CPC分类号： H03M3/496 , H03M3/43 , H03M3/438
摘要： An oversampling analog-to-digital modulator includes an analog loop filter which has a first integrator stage which operates as a continuous time integrator. the second, third, and fourth integrator stages are discrete time or sampling integrators. The continuous time first integrator provides the required thermal noise characteristics of the loop filter while the discrete time integrator stages provide loop stability and transfer characteristics which are advantageous to the overall operation of the analog-to-digital modulator.
摘要翻译：过采样模数转换器包括具有作为连续时间积分器工作的第一积分器级的模拟环路滤波器。第二，第三和第四积分器级是离散时间或采样积分器。连续时间第一积分器提供环路滤波器所需的热噪声特性，而离散时间积分器级提供有利于模数转换器的整体运行的环路稳定性和传输特性。

3. 发明授权

US4588941A Cascode CMOS bandgap reference 失效
标题翻译： Cascode CMOS带隙参考
公开(公告)号：US4588941A
公开(公告)日：1986-05-13
申请号：US700600
申请日：1985-02-11
申请人： Donald A. Kerth , Navdeep S. Sooch
发明人： Donald A. Kerth , Navdeep S. Sooch
IPC分类号： G05F3/24 , G05F3/30 , G05F3/20
CPC分类号： G05F3/30 , Y10S323/907
摘要： A CMOS bandgap voltage reference which is temperature stable is disclosed. The large temperature-dependent p-tub resistors of prior art arrangements are replaced with relatively small, temperature stable p+ diffusion resistors. The increase in current level needed to compensate for the decrease in resistor value is provided by a simple cascode MOS circuit located between the ratioing resistors and the VSS potential.
摘要翻译：公开了一种温度稳定的CMOS带隙电压基准。现有技术的大型温度依赖性p型电位器替换为相对较小的温度稳定的p +扩散电阻器。通过位于比电阻和VSS电位之间的简单共源共栅MOS电路来提供补偿电阻值下降所需的电流增加。

4. 发明授权

US5579247A Method and apparatus for decreasing the interference and noise sensitivity of a ratiometric converter type of circuit 失效
标题翻译：减小比例转换器类型电路的干扰和噪声灵敏度的方法和装置
公开(公告)号：US5579247A
公开(公告)日：1996-11-26
申请号：US537224
申请日：1995-09-29
申请人： Donald A. Kerth , Navdeep S. Sooch
发明人： Donald A. Kerth , Navdeep S. Sooch
IPC分类号： G01R19/00 , G01D3/00 , G01R19/10 , G01R19/25 , H03M1/06 , H03M1/12 , H03M3/00 , G06F19/00
CPC分类号： H03M1/0621 , G01D3/00 , H03M3/324 , H03M1/12 , H03M3/342 , H03M3/458
摘要： A ratiometric converter receives an external sense signal and external reference signal and provides an output signal which is proportional to the sense signal and inversely proportional to the reference signal. Electromagnetic interference and noise coupled onto the sense and reference lines are effectively removed by converting the sense signal to a digital signal and converting the reference signal to a digital signal. The digital sense signal is then filtered through a low pass filter to provide a filtered signal, and similarly, the digital reference signal is filtered through a low pass filter to provide a filtered digital reference signal. A divider circuit then divides the filter digital sense signal by the filter digital reference signal to provide the output signal.
摘要翻译：比例转换器接收外部感测信号和外部参考信号，并提供与感测信号成比例并与参考信号成反比的输出信号。通过将感测信号转换为数字信号并将参考信号转换为数字信号，有效地消除耦合到感测和参考线上的电磁干扰和噪声。然后通过低通滤波器对数字感测信号进行滤波，以提供经过滤波的信号，类似地，数字参考信号通过低通滤波器滤波以提供经过滤波的数字参考信号。分频器电路然后将滤波器数字检测信号除以滤波器数字参考信号以提供输出信号。

5. 发明授权

US4746899A Method for reducing effects of electrical noise in an analog-to-digital converter 失效
标题翻译：降低模数转换器电噪声影响的方法
公开(公告)号：US4746899A
公开(公告)日：1988-05-24
申请号：US916160
申请日：1986-10-07
申请人： Eric J. Swanson , Navdeep S. Sooch , David J. Knapp
发明人： Eric J. Swanson , Navdeep S. Sooch , David J. Knapp
IPC分类号： H03M1/08 , H03M3/02
CPC分类号： H03M3/324 , H03M3/458
摘要： Method for reducing deleterious effects of electrical noise in an analog-to-digital converter wherein both the analog and digital circuitry of the A/D converter are embodied in the same integrated circuit. The method includes sampling an analog input voltage with a first clock signal, generating a second clock signal that is delayed with respect to the first clock signal, and using the second clock signal as a clock for the digital circuitry. In accordance with another aspect of the invention, the method for reducing effects of noise in an A/D converter wherein such noise is generated by a digital decimation filter includes synchronously pipelining the arithmetic operations of the digital decimation filter.
摘要翻译：用于减少模数转换器中电噪声的有害影响的方法，其中A / D转换器的模拟和数字电路都体现在相同的集成电路中。该方法包括用第一时钟信号对模拟输入电压进行采样，产生相对于第一时钟信号被延迟的第二时钟信号，并且使用第二时钟信号作为数字电路的时钟。根据本发明的另一方面，用于减少A / D转换器中的噪声影响的方法，其中这种噪声由数字抽取滤波器产生，包括同步流水线数字抽取滤波器的算术运算。

6. 发明授权

US07283584B2 Direct digital access arrangement circuitry and method for connecting to phone lines 失效
公开(公告)号：US07283584B2
公开(公告)日：2007-10-16
申请号：US10780142
申请日：2004-02-17
申请人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
发明人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： H04M1/573 , H04L7/033 , H04L25/0266 , H04L25/06 , H04M1/76 , H04M3/007 , H04M11/06 , H04M19/001 , H04M19/02
摘要： An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

7. 发明授权

US07190785B2 Subscriber line interface circuitry 有权
标题翻译：用户线接口电路
公开(公告)号：US07190785B2
公开(公告)日：2007-03-13
申请号：US10814862
申请日：2004-03-31
申请人： Jerrell P. Hein , Navdeep S. Sooch
发明人： Jerrell P. Hein , Navdeep S. Sooch
IPC分类号： H04M19/00
CPC分类号： H04M1/738 , H04M1/745 , H04M3/005 , H04M3/04 , H04M3/2272 , H04M19/00 , H04M19/005
摘要： Subscriber line interface circuitry includes an integrated circuit having sense inputs for a sensed tip signal and a sensed ring signal of a subscriber loop. The integrated circuit generates a subscriber loop linefeed driver control signal in response to the sensed signals. In one embodiment, A linefeed driver includes power circuitry for providing battery feed to the ring and tip nodes of the subscriber loop in accordance with the linefeed control signal. The linefeed driver includes sense circuitry providing a sensed tip signal and a sensed ring signal. The sensed tip and ring signals correspond to a tip current and a ring current of the subscriber loop. In one embodiment, the integrated circuit is a complementary metal oxide semiconductor (CMOS) integrated circuit. In one embodiment, the linefeed driver comprises only discrete components.
摘要翻译：用户线接口电路包括具有用于感测的尖端信号的感测输入和用户环路的感测振铃信号的集成电路。集成电路响应于感测信号产生用户环路线路馈送驱动器控制信号。在一个实施例中，线路馈送驱动器包括用于根据线路进给控制信号向用户环路的环和尖端节点提供电池馈电的电源电路。换行驱动器包括提供感测到的尖端信号和感测到的振铃信号的感测电路。感测到的尖端和振铃信号对应于用户回路的尖端电流和环形电流。在一个实施例中，集成电路是互补金属氧化物半导体（CMOS）集成电路。在一个实施例中，换行驱动器仅包括分立部件。

8. 发明授权

US07180999B1 Subscriber line interface circuitry 有权
标题翻译：用户线接口电路
公开(公告)号：US07180999B1
公开(公告)日：2007-02-20
申请号：US09298008
申请日：1999-04-22
申请人： Jerrell P. Hein , Navdeep S. Sooch
发明人： Jerrell P. Hein , Navdeep S. Sooch
IPC分类号： H04M19/00
CPC分类号： H04M1/738 , H04M1/745 , H04M3/005 , H04M3/04 , H04M3/2272 , H04M19/00 , H04M19/005
摘要： Subscriber line interface circuitry includes an integrated circuit having sense inputs for a sensed tip signal and a sensed ring signal of a subscriber loop. The integrated circuit generates a subscriber loop linefeed driver control signal in response to the sensed signals. The linefeed driver does not reside with the integrated circuit. In one embodiment, the linefeed driver includes power circuitry for providing battery feed to the ring and tip nodes of the subscriber loop in accordance with the linefeed control signal. The linefeed driver includes sense circuitry providing a sensed tip signal and a sensed ring signal. The sensed tip and ring signals correspond to a tip current and a ring current of the subscriber loop. In one embodiment, the integrated circuit is a complementary metal oxide semiconductor (CMOS) integrated circuit. In one embodiment, the linefeed driver comprises only discrete components.
摘要翻译：用户线接口电路包括具有用于感测的尖端信号的感测输入和用户环路的感测振铃信号的集成电路。集成电路响应于感测信号产生用户环路线路馈送驱动器控制信号。换行驱动器不在集成电路中。在一个实施例中，线路馈送驱动器包括用于根据线路馈送控制信号向用户环路的环和尖端节点提供电池馈送的电源电路。换行驱动器包括提供感测到的尖端信号和感测到的振铃信号的感测电路。感测到的尖端和振铃信号对应于用户回路的尖端电流和环形电流。在一个实施例中，集成电路是互补金属氧化物半导体（CMOS）集成电路。在一个实施例中，换行驱动器仅包括分立部件。

9. 发明授权

US07046755B2 Digital access arrangement circuitry and method for connecting to phone lines having a DC holding circuit with switchable time constants 有权
标题翻译：用于连接到具有可切换时间常数的DC保持电路的电话线的数字接入配置电路和方法
公开(公告)号：US07046755B2
公开(公告)日：2006-05-16
申请号：US10679046
申请日：2003-10-03
申请人： Timothy J. Dupuis , George Tyson Tuttle , Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
发明人： Timothy J. Dupuis , George Tyson Tuttle , Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
IPC分类号： H04L23/00
CPC分类号： H04L25/06 , H04L7/033 , H04L25/0266 , H04M11/06 , H04M19/001
摘要： A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.
摘要翻译：可以使用数字直接访问布置（DAA）电路来终止在用户端的电话连接，其提供用于到达和来自电话线的信号的通信路径。简要描述，DAA提供用于各种国际电话标准的DC终端的可编程装置。本发明还可以用于在电容隔离屏障上传输和接收信号的装置。更具体地，提供了一种DC可编程直流限流模式可用的直流保持电路。在限流模式下，功率可能会在DAA集成电路外部的器件中耗散。此外，大部分功率可能会在外部无源器件（如电阻）中消散。

10. 发明授权

US06975723B2 Architecture for minimum loop current during ringing and caller ID 失效
标题翻译：振铃期间最小回路电流的结构和来电显示
公开(公告)号：US06975723B2
公开(公告)日：2005-12-13
申请号：US10429795
申请日：2003-05-05
申请人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland , Jerrell P. Hein , Andrew W. Krone
发明人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland , Jerrell P. Hein , Andrew W. Krone
IPC分类号： H03M1/42 , H04L7/033 , H04L25/02 , H04L25/06 , H04M1/57 , H04M11/06 , H04M19/00 , H04M19/02 , H04M1/00 , H04M9/00
CPC分类号： H04M1/573 , H04L7/033 , H04L25/0266 , H04L25/06 , H04M11/06 , H04M19/001 , H04M19/02
摘要： A communication system is provided which draws virtually no loop current during a ringing burst and only draws on-hook loop current during the caller ID field. More particularly, ringer burst circuitry may be powered from the user powered circuitry by the transmission of power across the isolation barrier rather than being powered from the phone line. Thus, loop current need not be drawn from the TIP/RING lines during ringer bursts. The isolation barrier may be a capacitive isolation barrier which allows bidirectional communication and extraction of power from signals transmitted across the barrier.
摘要翻译：提供一种通信系统，其在振铃突发期间几乎不消除环路电流，并且仅在呼叫者ID字段期间吸引挂机环路电流。更具体地，振铃突发电路可以由用户供电的电路通过跨隔离屏障的功率传输而不是从电话线供电。因此，在振铃器脉冲串期间，不需要从TIP / RING线路中抽出回路电流。隔离屏障可以是电容隔离屏障，其允许通过屏障传输的信号的双向通信和功率提取。

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