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1. 发明授权

US5969997A Narrow data width DRAM with low latency page-hit operations 失效
标题翻译：狭窄的数据宽度DRAM，具有低延迟页命中操作
公开(公告)号：US5969997A
公开(公告)日：1999-10-19
申请号：US942825
申请日：1997-10-02
申请人： Michael P. Clinton , Marc R. Faucher , Erik L. Hedberg , Mark W. Kellogg , Wilbur D. Pricer
发明人： Michael P. Clinton , Marc R. Faucher , Erik L. Hedberg , Mark W. Kellogg , Wilbur D. Pricer
IPC分类号： G11C11/41 , G11C11/401 , G11C11/407 , G11C11/409 , G11C15/00
CPC分类号： G11C11/409 , G11C11/407
摘要： A high speed Random Access Memory (RAM) array device includes several logical banks, each of which can be uniquely addressed. Each of these logical banks contains a unique memory array segment and associated page register, the latter serving as a temporary storage location during high-speed page hit operations. To reduce latency during an initial page hit, further array optimization is realized by segmenting each logical bank into two segments with one, smaller segment, comprising a faster random access memory (FRAM) for storing initial data in a data stream. A high speed page register connects the FRAM directly to a multiplexer/demultiplexer connected to the device I/O ports bypassing an internal bus protocol such that the initial data can be transferred between the FRAM and the I/O ports faster thereby improving page-hit latency. Hence, segmenting the logical banks to include only a small high speed segment results in a performance gain approaching what could be achieved by implementing the entire memory device with a high speed FRAM, but at much lower cost.
摘要翻译：高速随机存取存储器（RAM）阵列器件包括几个逻辑存储体，每个逻辑存储体可以被唯一地寻址。这些逻辑组中的每一个包含唯一的存储器阵列段和相关联的页寄存器，后者在高速页命中操作期间用作临时存储位置。为了在初始页面命中期间减少延迟，通过将每个逻辑存储体分割成具有一个较小段的两个段来实现进一步的阵列优化，其包括用于在数据流中存储初始数据的更快的随机存取存储器（FRAM）。高速页寄存器将FRAM直接连接到绕过内部总线协议的设备I / O端口连接的多路复用器/解复用器，从而可以更快地在FRAM和I / O端口之间传输初始数据，从而提高页命中率潜伏。因此，将逻辑存储体分割为仅包含小的高速段导致通过以高速FRAM实现整个存储器件而可以以低得多的成本实现可达到的性能增益。

2. 发明授权

US6070262A Reconfigurable I/O DRAM 失效
标题翻译：可重配置I / O DRAM
公开(公告)号：US6070262A
公开(公告)日：2000-05-30
申请号：US833367
申请日：1997-04-04
申请人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
发明人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
IPC分类号： G06F11/10 , G06F12/00 , G11C7/10 , G11C29/00
CPC分类号： G11C7/1057 , G06F11/1044 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A Dynamic Random Access Memory (DRAM) configurable by eight (.times.8) or by nine (.times.9). The DRAM has nine Data Input/Outputs (I/Os). The memory array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is configured .times.8, one I/O is held in its high impedance state; one ninth of the DRAM's data path (between the array and the ninth I/O) is ignored; and, the entire array address space is available for data storage through eight I/Os. When the DRAM is configured .times.9, all nine I/Os are active; the DRAM I/O path is reconfigured with part of the array providing the ninth bit through the ninth I/O; and the array address space reduced by one-eighth. All nine bits may be from a common sub-array. Alternatively, sub-arrays may be paired so that when the DRAM is configured .times.9, eight bits are accessed in seven-eighths of one sub-array, with the ninth bit being accessed in one eighth of the other sub-array of the pair.
摘要翻译：动态随机存取存储器（DRAM）可由八（x8）或九（x9）配置。 DRAM具有9个数据输入/输出（I / O）。存储器阵列被分成两个或更多个子阵列，子阵列单元被布置成可寻址的行和列。当DRAM被配置为x8时，一个I / O保持在其高阻抗状态; DRAM的数据路径（阵列和第九个I / O之间）的九分之一被忽略; 并且整个阵列地址空间可用于通过八个I / O进行数据存储。当DRAM配置为x9时，所有9个I / O都有效; DRAM I / O路径被配置为通过第九个I / O提供第九位的阵列的一部分; 并且阵列地址空间减少了八分之一。所有9位可能来自公共子阵列。或者，子阵列可以配对，使得当DRAM被配置为x9时，在一个子阵列的七分之八中访问八个比特，其中第九比特在该对的另一个子阵列的八分之一中被访问。

3. 发明授权

US6065093A High bandwidth narrow I/O memory device with command stacking 失效
标题翻译：带带命令的高带宽窄I / O存储器
公开(公告)号：US6065093A
公开(公告)日：2000-05-16
申请号：US79572
申请日：1998-05-15
申请人： Timothy J. Dell , Erik L. Hedberg , Mark W. Kellogg
发明人： Timothy J. Dell , Erik L. Hedberg , Mark W. Kellogg
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/401 , G06F13/00
CPC分类号： G11C7/1072 , G11C7/22
摘要： A memory device is provided which stacks commands and internally executes each command at the appropriate time, thereby ensuring contiguous data I/O. The memory device is capable of initiating memory accesses either immediately or "stacking" the command along with a "clock count". The clock count defines the number of clock cycles that must occur prior to execution of the command by the memory device. The memory device initiates memory accesses either immediately, or delayed by the number of clocks defined by the clock count for that command. The memory device operates as a slave to the memory controller and therefore has no ability to execute instructions at a time other than that defined by the memory controller.
摘要翻译：提供一种存储器件，其堆叠命令并在适当的时间内部执行每个命令，从而确保连续的数据I / O。存储器件能够立即启动存储器访问或者“堆叠”命令以及“时钟计数”。时钟计数定义在存储器件执行命令之前必须发生的时钟周期数。存储器设备立即启动存储器访问，或延迟由该命令的时钟计数定义的时钟数。存储器件作为存储器控制器的从设备操作，因此在与由存储器控制器定义的时间以外的时间不具有执行指令的能力。

4. 发明授权

US06178517B1 High bandwidth DRAM with low operating power modes 失效
标题翻译：具有低工作功率模式的高带宽DRAM
公开(公告)号：US06178517B1
公开(公告)日：2001-01-23
申请号：US09121933
申请日：1998-07-24
申请人： Claude L. Bertin , Timothy J. Dell , Erik L. Hedberg , Mark W. Kellogg
发明人： Claude L. Bertin , Timothy J. Dell , Erik L. Hedberg , Mark W. Kellogg
IPC分类号： G06F1200
CPC分类号： G06F13/1684 , Y02D10/14
摘要： A high bandwidth DRAM is provided with two separate bus networks connecting the DRAM to a processor. One bus network is a high speed (e.g., 500 MHZ) 8:1 or 16:1 multiplexed I/O bus and the second is a slower (e.g., 64-bit) bus. The high-speed bus is used for example for graphic intensive applications which require fast access to large numbers of bits in the DRAM memory array. This of course results in higher power requirements. Since, not all applications require such large amounts of data to be transferred between the DRAM and the processor, the slower bus is provided for these less demanding applications such as word processors, spreadsheets, and the like. The slower bus requires less power to operate and therefore results in a power saving mode which, among other things, facilitates longer battery life.
摘要翻译：高带宽DRAM具有将DRAM连接到处理器的两个单独的总线网络。一个总线网络是高速（例如，500MHz）8：1或16：1多路复用I / O总线，第二个是较慢（例如，64位）总线。例如，高速总线用于需要快速访问DRAM存储器阵列中大量位的图形密集型应用。这当然会导致更高的功率需求。由于并非所有应用都需要在DRAM和处理器之间传输大量数据，所以为这些不太要求苛刻的应用程序提供较慢的总线，例如文字处理器，电子表格等。较慢的总线需要更少的功率来进行操作，因此导致省电模式，其中尤其有助于延长电池寿命。

5. 发明授权

US5896404A Programmable burst length DRAM 失效
标题翻译：可编程突发长度DRAM
公开(公告)号：US5896404A
公开(公告)日：1999-04-20
申请号：US833371
申请日：1997-04-04
申请人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
发明人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
IPC分类号： G06F12/16 , G06F11/10 , G11C7/10 , G11C11/401 , G11C29/42 , G11C29/00
CPC分类号： G06F11/1008 , G11C7/1018 , G06F11/1052
摘要： A Dynamic Random Access Memory (DRAM) with a burst length programmable as eight (8) or nine (9) bytes. The DRAM array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is programmed in Normal mode, the burst length is 8 and the entire array address space is available for data storage. When the DRAM is programmed for error checking (ECC mode), the burst length is nine and the array is reconfigured with part of the array providing the ninth byte. The DRAM's address space is reduced by one-eighth in ECC mode. Preferably, all nine locations are in the same page, with each page being divided into eight equal portions. In Normal mode all eight equal portions are data storage; and, in ECC mode, seven-eighths of the page is data storage, the remaining one eighth being assigned to check bit storage.
摘要翻译：具有可编程为八（8）或九（9）字节的突发长度的动态随机存取存储器（DRAM）。 DRAM阵列分为两个或更多个子阵列，子阵列单元以可寻址的行和列排列。当DRAM在正常模式下编程时，突发长度为8，整个阵列地址空间可用于数据存储。当DRAM被编程用于错误检查（ECC模式）时，突发长度为9，并且阵列被配置为提供第九个字节的阵列的一部分。在ECC模式下，DRAM的地址空间减少了八分之一。优选地，所有九个位置在同一页面中，每个页面被分成八个相等的部分。在正常模式下，所有八个相等的部分都是数据存储; 并且在ECC模式中，页面的七分之一是数据存储，剩下的八分之一被分配给校验位存储。

6. 发明授权

US08024513B2 Method and system for implementing dynamic refresh protocols for DRAM based cache 有权
标题翻译：用于实现基于DRAM的缓存动态刷新协议的方法和系统
公开(公告)号：US08024513B2
公开(公告)日：2011-09-20
申请号：US11949904
申请日：2007-12-04
申请人： John E. Barth, Jr. , Philip G. Emma , Erik L. Hedberg , Hillery C. Hunter , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
发明人： John E. Barth, Jr. , Philip G. Emma , Erik L. Hedberg , Hillery C. Hunter , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , Y02D10/13
摘要： A method for implementing dynamic refresh protocols for DRAM based cache includes partitioning a DRAM cache into a refreshable portion and a non-refreshable portion, and assigning incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines. Cache lines corresponding to data having a usage history below a defined frequency are assigned to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.
摘要翻译：一种用于实现基于DRAM的高速缓存的动态刷新协议的方法包括将DRAM高速缓存划分为可刷新部分和不可刷新部分，以及基于以下方式将输入的各个高速缓存行分配到高速缓存的可刷新部分和不可刷新部分之一：高速缓存行的使用历史。对应于具有低于定义频率的使用历史的数据的缓存线被分配给高速缓存的可刷新部分，并且与具有等于或高于定义频率的使用历史的数据相对应的高速缓存行被分配给高速缓存的不可刷新部分。

7. 发明申请

US20090144506A1 METHOD AND SYSTEM FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DRAM BASED CACHE 有权
标题翻译：用于实现基于DRAM的缓存的动态刷新协议的方法和系统
公开(公告)号：US20090144506A1
公开(公告)日：2009-06-04
申请号：US11949904
申请日：2007-12-04
申请人： John E. Barth, JR. , Philip G. Emma , Erik L. Hedberg , Hillery C. Hunter , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
发明人： John E. Barth, JR. , Philip G. Emma , Erik L. Hedberg , Hillery C. Hunter , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
IPC分类号： G06F12/08
CPC分类号： G06F12/0893 , Y02D10/13
摘要： A method for implementing dynamic refresh protocols for DRAM based cache includes partitioning a DRAM cache into a refreshable portion and a non-refreshable portion, and assigning incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines. Cache lines corresponding to data having a usage history below a defined frequency are assigned to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.
摘要翻译：一种用于实现基于DRAM的高速缓存的动态刷新协议的方法包括将DRAM高速缓存划分为可刷新部分和不可刷新部分，以及基于以下方式将输入的各个高速缓存行分配到高速缓存的可刷新部分和不可刷新部分之一：高速缓存行的使用历史。对应于具有低于定义频率的使用历史的数据的高速缓存行被分配给高速缓存的可刷新部分，并且与具有等于或高于定义频率的使用历史的数据相对应的高速缓存行被分配给高速缓存的不可刷新部分。

8. 发明授权

US06574763B1 Method and apparatus for semiconductor integrated circuit testing and burn-in 失效
标题翻译：用于半导体集成电路测试和老化的方法和装置
公开(公告)号：US06574763B1
公开(公告)日：2003-06-03
申请号：US09473886
申请日：1999-12-28
申请人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , William R. Tonti
发明人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , William R. Tonti
IPC分类号： G01R3128
CPC分类号： G01R31/287
摘要： A burn-in process is provided for a memory array having redundant bits and addressable storage locations. The burn-in process includes the steps of raising the temperature of the memory array to a pre-determined temperature, testing all bits in the array, detecting faulty bits and operable bits, replacing faulty bits with redundant operable bits, correcting any defects in the array in-situ, and lowering the temperature of the memory array to ambient temperature to complete the burn-in process. An apparatus for carrying out the above process is provided that includes a test circuit for generating a test pattern and for applying the test pattern to the memory array so as to test all bits within the memory array. A comparison circuit, coupled to the test circuit and adapted to couple to the memory array, compares an actual response and an expected response of the memory array to the test pattern and detects faulty and operable bits based thereon. A failed address buffer register, coupled to the comparison circuit and to the test circuit, stores an address of each addressable storage location that has a faulty bit. Sparing control logic, coupled to the failed address buffer register and adapted to couple to the memory array, reads out each address stored by the failed address buffer register and replaces each faulty bit with a redundant operable bit.
摘要翻译：为具有冗余位和可寻址存储位置的存储器阵列提供老化过程。老化过程包括以下步骤：将存储器阵列的温度升高到预定温度，测试阵列中的所有位，检测故障位和可操作位，用冗余的可操作位代替故障位，校正在阵列原位，并将存储器阵列的温度降低到环境温度以完成老化过程。提供了一种用于执行上述处理的装置，其包括用于生成测试图案并将测试图案应用于存储器阵列的测试电路，以便测试存储器阵列内的所有位。耦合到测试电路并且适于耦合到存储器阵列的比较电路将存储器阵列的实际响应和预期响应与测试模式进行比较，并基于此检测故障和可操作的位。耦合到比较电路和测试电路的故障地址缓冲寄存器存储具有错误位的每个可寻址存储位置的地址。冗余控制逻辑耦合到故障地址缓冲寄存器并适于耦合到存储器阵列，读出由故障地址缓冲寄存器存储的每个地址，并用冗余可操作位替换每个故障位。

9. 发明授权

US5561622A Integrated memory cube structure 失效
标题翻译：集成内存立方体结构
公开(公告)号：US5561622A
公开(公告)日：1996-10-01
申请号：US120993
申请日：1993-09-13
申请人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , Gordon A. Kelley, Jr.
发明人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , Gordon A. Kelley, Jr.
IPC分类号： G11C5/00 , H01L25/065 , G11C5/06 , H01L23/02
CPC分类号： H01L25/0657 , G11C5/06 , H01L2224/48091 , H01L2225/0651 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06596 , H01L2924/10253
摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.
摘要翻译：一种集成的存储立方体结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得更强大的存储器架构被定义为单个更高级存储器芯片的功能外观。形成具有N个存储器芯片和至少一个逻辑芯片的存储器/逻辑立方体，其中立方体的每个存储器芯片具有M个存储器件。控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有NxM存储器件的单个存储器芯片架构出现在立方体的I / O引脚处。相应的制造技术包括用于在存储器子单元的侧表面上促进金属化图案化的方法。

10. 发明授权

US5173906A Built-in self test for integrated circuits 失效
标题翻译：集成电路内置自检
公开(公告)号：US5173906A
公开(公告)日：1992-12-22
申请号：US576646
申请日：1990-08-31
申请人： Jeffrey H. Dreibelbis , Erik L. Hedberg , John G. Petrovick, Jr.
发明人： Jeffrey H. Dreibelbis , Erik L. Hedberg , John G. Petrovick, Jr.
IPC分类号： G01R31/28 , G06F11/22 , G06F11/27 , G06F15/78 , G11C29/10 , G11C29/12 , G11C29/16 , G11C29/38 , G11C29/44 , H01L27/10
CPC分类号： G11C29/16 , G06F11/27 , G11C29/44 , G11C29/10 , G11C29/38
摘要： A built-in, i.e., on-chip, self-test system for a VLSI logic or memory module. A deterministic data pattern generator is provided on the VLSI chip, and operates to test a chip module and provide a fail/no-fail result, along with data identifying where the fail occurred. This location data is captured and made available for subsequent utilization. The built-in test circuitry is programmable, and is provided with a looping capability to provide enhanced burn-in testing, for example.

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