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1. 发明申请

US20090003049A1 PHASE CHANGE MEMORY DEVICE AND PROGRAM METHOD THEREOF 有权
标题翻译：相变存储器件及其程序方法
公开(公告)号：US20090003049A1
公开(公告)日：2009-01-01
申请号：US12168742
申请日：2008-07-07
申请人： Kwang-Jin LEE , Du-Eung KIM , Sang-Beom KANG , Woo-Yeong CHO
发明人： Kwang-Jin LEE , Du-Eung KIM , Sang-Beom KANG , Woo-Yeong CHO
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C5/145 , G11C7/1078 , G11C7/1096 , G11C11/5678 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2213/79
摘要： A phase change memory device includes a memory cell having a phase change material, a write driver adapted to supply a program current to the memory cell during a programming interval, and a pump circuit adapted to enhance a current supply capacity of the write driver during the programming interval. The pump circuit is activated prior to the programming interval in response to an external control signal.
摘要翻译：相变存储器件包括具有相变材料的存储单元，适于在编程间隔期间向存储单元提供编程电流的写入驱动器，以及用于在写入驱动器期间增强写入驱动器的电流供应容量的泵电路编程间隔。泵电路响应于外部控制信号在编程间隔之前被激活。

2. 发明申请

US20080175031A1 MEMORY CELL OF A RESISTIVE SEMICONDUCTOR MEMORY DEVICE, A RESISTIVE SEMICONDUCTOR MEMORY DEVICE HAVING A THREE-DIMENSIONAL STACK STRUCTURE, AND RELATED METHODS 有权
标题翻译：电阻半导体存储器件的存储单元，具有三维堆叠结构的电阻半导体存储器件及相关方法
公开(公告)号：US20080175031A1
公开(公告)日：2008-07-24
申请号：US12015624
申请日：2008-01-17
申请人： Joon-Min PARK , Sang-Beom KANG , Hyung-Rok OH , Woo-Yeong CHO
发明人： Joon-Min PARK , Sang-Beom KANG , Hyung-Rok OH , Woo-Yeong CHO
IPC分类号： G11C5/02 , G11C11/21
CPC分类号： G11C5/02 , G11C13/00 , G11C13/0004 , G11C13/0023 , G11C2213/71 , G11C2213/72
摘要： A memory cell of a resistive semiconductor memory device, a resistive semiconductor memory device having a three-dimensional stack structure, and related methods are provided. The memory cell of a resistive semiconductor memory device includes a twin cell, wherein the twin cell stores data values representing one bit of data. The twin cell includes a main unit cell connected to a main bit line and a word line, and a sub unit cell connected to a sub bit line and the word line. Also, the main unit cell includes a first variable resistor and a first diode, and the sub unit cell includes a second variable resistor and a second diode.
摘要翻译：提供了电阻半导体存储器件的存储单元，具有三维堆叠结构的电阻半导体存储器件及相关方法。电阻半导体存储器件的存储单元包括双胞胎，其中双胞胎存储表示一位数据的数据值。双胞胎单元包括连接到主位线和字线的主单元，以及连接到子位线和字线的子单元。此外，主单元包括第一可变电阻器和第一二极管，并且子单元电池包括第二可变电阻器和第二二极管。

3. 发明申请

US20110103134A1 RESISTANCE RANDOM ACCESS MEMORY HAVING COMMON SOURCE LINE 审中-公开
标题翻译：具有普通源线的电阻随机存取存储器
公开(公告)号：US20110103134A1
公开(公告)日：2011-05-05
申请号：US13004251
申请日：2011-01-11
申请人： Hyung-Rok OH , Sang-Beom KANG , Joon-Min PARK , Woo-Yeong CHO
发明人： Hyung-Rok OH , Sang-Beom KANG , Joon-Min PARK , Woo-Yeong CHO
IPC分类号： G11C11/40
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2213/31 , G11C2213/79
摘要： A method writes data to a resistance random access memory (RRAM) memory cell through first and second write paths, and includes; applying a positive source voltage to a selected source line, applying a word line drive voltage to a selected word line, and applying a voltage at least twice the level of the positive source voltage to a selected bit line via the first write path when writing data having the first state in the memory cell, and applying a ground voltage to the selected bit line via the second write path when writing data having the second state in the memory cell.
摘要翻译：一种方法通过第一和第二写入路径将数据写入电阻随机存取存储器（RRAM）存储单元，并且包括：对所选择的源极线施加正的源极电压，将字线驱动电压施加到所选择的字线，并且当写入数据时，通过第一写入路径将正的源极电压的电平至少两倍的电压施加到所选择的位线在存储单元中具有第一状态，并且当在存储单元中写入具有第二状态的数据时，经由第二写入路径将接地电压施加到所选择的位线。

4. 发明申请

US20080273365A1 NONVOLATILE MEMORY DEVICE HAVING TWIN MEMORY CELLS 有权
标题翻译：具有两个存储单元的非易失存储器件
公开(公告)号：US20080273365A1
公开(公告)日：2008-11-06
申请号：US12107985
申请日：2008-04-23
申请人： Sang-Beom KANG , Woo-Yeong CHO , Hyung-Rok OH , Joon-Min PARK
发明人： Sang-Beom KANG , Woo-Yeong CHO , Hyung-Rok OH , Joon-Min PARK
IPC分类号： G11C5/02
CPC分类号： G11C13/003 , G11C11/14 , G11C11/22 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2213/31 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76
摘要： A nonvolatile memory device includes multiple first bit lines extending in a first direction, multiple word lines formed on the first bit lines and extending in a second direction different from the first direction, and multiple second bit lines, formed on the word lines and extending in the first direction. The nonvoliative memory device also includes multiple twin memory cells, each of which includes a first memory cell coupled between a first bit line and a word line and a second memory cell coupled between the word line and a second bit line. The first and second memory cells store different data.
摘要翻译：非易失性存储器件包括沿第一方向延伸的多个第一位线，形成在第一位线上并在与第一方向不同的第二方向上延伸的多个字线以及形成在字线上并在字线上延伸的多个第二位线第一个方向。非易失性存储器件还包括多个双存储器单元，每个存储单元包括耦合在第一位线和字线之间的第一存储器单元和耦合在字线和第二位线之间的第二存储单元。第一和第二存储单元存储不同的数据。

5. 发明申请

US20080180981A1 RESISTANCE SEMICONDUCTOR MEMORY DEVICE HAVING THREE-DIMENSIONAL STACK AND WORD LINE DECODING METHOD THEREOF 有权
标题翻译：具有三维堆叠的电阻半导体存储器件及其线解码方法
公开(公告)号：US20080180981A1
公开(公告)日：2008-07-31
申请号：US12020237
申请日：2008-01-25
申请人： Joon Min PARK , Sang-Beom KANG , Hyung-Rok OH , Woo-Yeong CHO
发明人： Joon Min PARK , Sang-Beom KANG , Hyung-Rok OH , Woo-Yeong CHO
IPC分类号： G11C5/02 , G11C8/10 , G11C11/36
CPC分类号： G11C8/08 , G11C8/14 , G11C11/16 , G11C13/00 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C2213/71 , G11C2213/72
摘要： A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided. In the resistance semiconductor memory device of a three-dimensional stack structure, in which a plurality of word line layers and a plurality of bit line layers are disposed alternately and perpendicularly, and in which a plurality of memory cell layers are disposed between the word line layers and the bit line layers; the resistance semiconductor memory device includes a plurality of bit lines disposed on each of the bit line layers in a first direction as a length direction; a plurality of sub word lines disposed on each of the word line layers in a second direction as a length direction, intersected to the first direction; a plurality of memory cells disposed on the memory cell layers; and a plurality of main word lines individually disposed on a main word line layer specifically adapted over the bit line layers and the word line layers, in the second direction as a length direction, each one of the plurality of main word lines being shared by a predetermined number of sub word lines. An efficient word line decoding adequate to high integration can be achieved.
摘要翻译：提供三维堆栈结构的电阻半导体存储器件及其字线解码方法。在三维堆叠结构的电阻半导体存储器件中，其中多个字线层和多个位线层交替和垂直地布置，并且其中多个存储单元层设置在字线层和位线层; 电阻半导体存储器件包括沿着第一方向设置在每个位线层上的多个位线作为长度方向; 在与第一方向相交的长度方向的第二方向上配置在每个字线层上的多个子字线; 设置在所述存储单元层上的多个存储单元; 以及多个主字线分别设置在主字线层上，特别适用于位线层和字线层，在第二方向上作为长度方向，多个主字线中的每一条由预定数量的子字线。可以实现足够高集成度的有效的字线解码。

6. 发明申请

US20080175036A1 RESISTANCE RANDOM ACCESS MEMORY HAVING COMMON SOURCE LINE 有权
标题翻译：具有普通源线的电阻随机存取存储器
公开(公告)号：US20080175036A1
公开(公告)日：2008-07-24
申请号：US11964142
申请日：2007-12-26
申请人： Hyung-Rok OH , Sang-Beom KANG , Joon-Min PARK , Woo-Yeong CHO
发明人： Hyung-Rok OH , Sang-Beom KANG , Joon-Min PARK , Woo-Yeong CHO
IPC分类号： G11C11/21
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2213/31 , G11C2213/79
摘要： A resistance random access memory (RRAM) having a source line shared structure and an associated data access method. The RRAM, in which a write operation of writing data of first state and second state to a selected memory cell is performed through first and second write paths having mutually opposite directions, includes word lines, bit lines, a memory cell array and a plurality of source lines. The memory cell array includes a plurality of memory cells each constructed of an access transistor coupled to a resistive memory device. The memory cells are disposed in a matrix of rows and columns and located at each intersection of a word line and a bit line. Each of the plurality of source lines is disposed between a pair of word lines and in the same direction as the word lines. A positive voltage is applied to a source line in a memory cell write operation. Through the source line shared structure, occupied chip area is reduced and, in a write operating mode, a bit line potential can be determined within a positive voltage level range.
摘要翻译：具有源线共享结构的电阻随机存取存储器（RRAM）和相关联的数据存取方法。其中通过具有相互相反方向的第一和第二写入路径来执行将第一状态和第二状态的数据写入所选存储单元的写入操作，包括字线，位线，存储单元阵列和多个源线。存储单元阵列包括多个存储单元，每个存储单元由耦合到电阻存储器件的存取晶体管构成。存储单元被布置成行和列的矩阵并且位于字线和位线的每个交叉点处。多个源极线中的每一个被设置在一对字线之间并且在与字线相同的方向上。在存储单元写入操作中，将正电压施加到源极线。通过源极线共享结构，占用的芯片面积减小，并且在写入操作模式中，可以在正电压电平范围内确定位线电位。

7. 发明申请

US20090291522A1 LAYOUT STRUCTURE IN SEMICONDUCTOR MEMORY DEVICE COMPRISING GLOBAL WORD LINES, LOCAL WORD LINES, GLOBAL BIT LINES AND LOCAL BIT LINES 有权
标题翻译：包含全球字线，本地字线，全球位线和本地位线的半导体存储器件中的布局结构
公开(公告)号：US20090291522A1
公开(公告)日：2009-11-26
申请号：US12509617
申请日：2009-07-27
申请人： Hyung-Rok OH , Sang-Beom KANG , Du-Eung KIM
发明人： Hyung-Rok OH , Sang-Beom KANG , Du-Eung KIM
IPC分类号： H01L21/06 , G11C5/02
CPC分类号： G11C7/18 , G11C5/063 , G11C13/0004 , G11C2213/72 , H01L27/24
摘要： A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line, and a global bit line and a local bit line, and individually disposing all of the global word line, the local word line, the global bit line and the local bit line at conductive layers among at least three layers; at least two of the global word line, the local word line, the global bit line and the local bit line are together disposed in parallel on one conductive layer. Signal lines constituting a semiconductor memory device are disposed in a hierarchical structure, whereby a semiconductor memory device advantageously having high integration, high speed and high performance may be obtained.
摘要翻译：提供了具有层次结构的半导体存储器件中的线路布局结构和方法。在具有全局字线和本地字线以及全局位线和局部位线的半导体存储器件中，并且单独地布置全局全局字线，局部字线，全局位线和局部位在至少三层中的导电层上线; 全局字线，本地字线，全局位线和局部位线中的至少两个在一个导电层上一并设置。构成半导体存储器件的信号线以分层结构设置，从而可以获得有利地具有高集成度，高速度和高性能的半导体存储器件。

8. 发明申请

US20140022836A1 SEMICONDUCTOR MEMORY DEVICE HAVING RESISTIVE MEMORY CELLS AND METHOD OF TESTING THE SAME 有权
标题翻译：具有电阻记忆体的半导体存储器件及其测试方法
公开(公告)号：US20140022836A1
公开(公告)日：2014-01-23
申请号：US13945007
申请日：2013-07-18
申请人： Hye-Jin KIM , Hyung-Rok OH , Dong-Seok KANG , Dong-Hyun SOHN , Sang-Beom KANG , Chul-Woo PARK , Yun-Sang LEE
发明人： Hye-Jin KIM , Hyung-Rok OH , Dong-Seok KANG , Dong-Hyun SOHN , Sang-Beom KANG , Chul-Woo PARK , Yun-Sang LEE
IPC分类号： G11C29/10 , G11C11/16
CPC分类号： G11C29/10 , G11C11/16 , G11C11/161 , G11C11/165 , G11C11/1673 , G11C11/1675 , G11C29/32 , G11C29/34 , G11C2029/2602
摘要： A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. The MTJ element includes a free layer, a barrier layer and a pinned layer. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set.
摘要翻译：半导体存储器件包括存储单元阵列，模式寄存器组和测试电路。存储单元阵列包括多个字线，多个位线和多个自旋转移转矩磁阻随机存取存储器（STT-MRAM）单元，每个STT-MRAM单元设置在每个字线的交叉区域和位线，并且STT-MRAM单元包括磁隧道结（MTJ）元件和单元晶体管。 MTJ元件包括自由层，阻挡层和钉扎层。单元晶体管的栅极耦合到字线，单元晶体管的第一电极通过MTJ元件耦合到位线，并且单元晶体管的第二电极耦合到源极线。模式寄存器组被配置为设置测试模式，并且测试电路被配置为通过使用模式寄存器集执行测试操作。

9. 发明申请

US20110231735A1 STACKED SEMICONDUCTOR MEMORY DEVICE AND RELATED ERROR-CORRECTION METHOD 有权
标题翻译：堆叠半导体存储器件及相关误差校正方法
公开(公告)号：US20110231735A1
公开(公告)日：2011-09-22
申请号：US13015850
申请日：2011-01-28
申请人： Chul-Woo PARK , Hong-Sun HWANG , Kwan-Young OH , Sang-Beom KANG
发明人： Chul-Woo PARK , Hong-Sun HWANG , Kwan-Young OH , Sang-Beom KANG
IPC分类号： G06F11/00
CPC分类号： G06F11/1044
摘要： A stacked semiconductor memory device comprises an error correction code (ECC) controller that controls the number of bits in an ECC word and corrects errors in memory cell array layers using the ECC word.
摘要翻译：叠层半导体存储器件包括纠错码（ECC）控制器，该纠错码控制ECC字中的位数，并使用ECC字校正存储单元阵列层中的错误。

10. 发明申请

US20110228581A1 STACKED MEMORY DEVICE AND METHOD OF REPAIRING SAME 失效
标题翻译：堆叠式存储器件及其修复方法
公开(公告)号：US20110228581A1
公开(公告)日：2011-09-22
申请号：US13015847
申请日：2011-01-28
申请人： Chul-Woo PARK , Hong-Sun HWANG , Sang-Beom KANG , Won-Seok LEE
发明人： Chul-Woo PARK , Hong-Sun HWANG , Sang-Beom KANG , Won-Seok LEE
IPC分类号： G11C5/02 , G11C29/04
CPC分类号： G11C5/025 , G11C29/80
摘要： A stacked semiconductor memory device comprises memory cell array layers that are stacked in an inverted wedge shape and have different redundancy sizes from each other. The stacked semiconductor memory device has space for vertical connection between layers, a relatively small size, and a relatively high yield.
摘要翻译：层叠的半导体存储器件包括以倒置的楔形堆叠并且具有彼此不同的冗余尺寸的存储单元阵列层。层叠的半导体存储器件具有用于层之间的垂直连接的空间，相对较小的尺寸和相对高的产量。

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