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1. 发明申请

US20050070098A1 PRE-ANNEAL OF COSI, TO PREVENT FORMATION OF AMORPHOUS LAYER BETWEEN TI-O-N AND COSI 失效
标题翻译： COSE预先预防TI-O-N和COSI之间形成非晶层
公开(公告)号：US20050070098A1
公开(公告)日：2005-03-31
申请号：US10674645
申请日：2003-09-30
申请人： John Bruley , Cyril Cabral , Christian Lavoie , Tina Wagner , Yun Wang , Horatl Wlldman , Wong Hon
发明人： John Bruley , Cyril Cabral , Christian Lavoie , Tina Wagner , Yun Wang , Horatl Wlldman , Wong Hon
IPC分类号： H01L21/336 , H01L21/44 , H01L21/768 , H01L23/52
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/76814 , H01L21/76855 , H01L21/76856 , H01L29/665
摘要： The present invention provides a method for forming an interconnect to a cobalt or nickel silicide having a TiN diffusion barrier. The inventive method comprises providing an initial structure having vias to exposed silicide regions positioned on a substrate; annealing the initial structure in a nitrogen-containing ambient, wherein a nitrogen passivation layer is formed atop the exposed silicide region; depositing Ti atop the nitrogen passivation layer; annealing the Ti in a nitrogen-containing ambient to form a TiN diffusion barrier and an amorphous Ti cobalt silicide between the TiN diffusion layer and the cobalt or nickel silicide and depositing an interconnect metal within the vias and atop the TiN diffusion barrier. The nitrogen passivation layer substantially restricts diffusion between the Ti and silicide layers minimizing the amorphous Ti cobalt silicide layer that forms. Therefore, the amorphous Ti cobalt or Ti nickel silicide is restricted to a thickness of less than about 3.0 nm.
摘要翻译：本发明提供一种用于形成具有TiN扩散阻挡层的钴或镍硅化物的互连的方法。本发明的方法包括提供具有通孔的初始结构，以暴露出位于基板上的硅化物区域; 在含氮环境中退火初始结构，其中在暴露的硅化物区域上形成氮钝化层; 在氮钝化层顶上沉积Ti; 在含氮环境中退火Ti以在TiN扩散层和钴或镍硅化物之间形成TiN扩散阻挡层和非晶Ti钴硅化物，并在通孔内和TiN扩散势垒顶上沉积互连金属。氮钝化层基本上限制了Ti和硅化物层之间的扩散，使形成的无定形Ti钴硅化物层最小化。因此，非晶Ti钴或Ti镍硅化物被限制在小于约3.0nm的厚度。

2. 发明授权

US06878624B1 Pre-anneal of CoSi, to prevent formation of amorphous layer between Ti-O-N and CoSi 失效
标题翻译： CoSi的预退火，以防止在Ti-O-N和CoSi之间形成非晶层
公开(公告)号：US06878624B1
公开(公告)日：2005-04-12
申请号：US10674645
申请日：2003-09-30
申请人： John Bruley , Cyril Cabral, Jr. , Christian Lavoie , Tina J. Wagner , Yun Yu Wang , Horati S. Wildman , Wong Kwong Hon
发明人： John Bruley , Cyril Cabral, Jr. , Christian Lavoie , Tina J. Wagner , Yun Yu Wang , Horati S. Wildman , Wong Kwong Hon
IPC分类号： H01L21/336 , H01L21/44 , H01L21/768 , H01L23/52
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/76814 , H01L21/76855 , H01L21/76856 , H01L29/665
摘要： The present invention provides a method for forming an interconnect to a cobalt or nickel silicide having a TiN diffusion barrier. The inventive method comprises providing an initial structure having vias to exposed silicide regions positioned on a substrate; annealing the initial structure in a nitrogen-containing ambient, wherein a nitrogen passivation layer is formed atop the exposed silicide region; depositing Ti atop the nitrogen passivation layer; annealing the Ti in a nitrogen-containing ambient to form a TiN diffusion barrier and an amorphous Ti cobalt silicide between the TiN diffusion layer and the cobalt or nickel silicide and depositing an interconnect metal within the vias and atop the TiN diffusion barrier. The nitrogen passivation layer substantially restricts diffusion between the Ti and silicide layers minimizing the amorphous Ti cobalt silicide layer that forms. Therefore, the amorphous Ti cobalt or Ti nickel silicide is restricted to a thickness of less than about 3.0 nm.
摘要翻译：本发明提供一种用于形成具有TiN扩散阻挡层的钴或镍硅化物的互连的方法。本发明的方法包括提供具有通孔的初始结构，以暴露出位于基板上的硅化物区域; 在含氮环境中退火初始结构，其中在暴露的硅化物区域上形成氮钝化层; 在氮钝化层顶上沉积Ti; 在含氮环境中退火Ti以在TiN扩散层和钴或镍硅化物之间形成TiN扩散阻挡层和非晶Ti钴硅化物，并在通孔内和TiN扩散势垒顶上沉积互连金属。氮钝化层基本上限制了Ti和硅化物层之间的扩散，使形成的无定形Ti钴硅化物层最小化。因此，非晶Ti钴或Ti镍硅化物被限制在小于约3.0nm的厚度。

3. 发明授权

US06436823B1 Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formed 有权
标题翻译：在半导体结构中的金属硅化物层的顶部上形成TiN层的方法和形成的结构
公开(公告)号：US06436823B1
公开(公告)日：2002-08-20
申请号：US09679738
申请日：2000-10-05
申请人： Cyril Cabral, Jr. , Chung-Ping Eng , Lynne Marie Gignac , Christian Lavoie , Patricia O'Neil , Kirk David Peterson , Tina Wagner , Yun-Yu Wang , Keith Wong
发明人： Cyril Cabral, Jr. , Chung-Ping Eng , Lynne Marie Gignac , Christian Lavoie , Patricia O'Neil , Kirk David Peterson , Tina Wagner , Yun-Yu Wang , Keith Wong
IPC分类号： H01L2144
CPC分类号： H01L21/76856 , H01L21/28518 , H01L2221/1078
摘要： A method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure without the formation of a thick amorphous layer containing Ti, Co and Si and the structure formed are provided. In the method, after a Ti layer is deposited on top of a metal silidide layer, a dual-step annealing process is conducted in which a low temperature annealing in a forming gas (or ammonia) at a temperature not higher than 500° C. is first conducted for less than 2 hours followed by a high temperature annealing in a nitrogen-containing gas (or ammonia) at a second temperature not lower than 500° for less than 2 hours to form the TiN layer. The present invention method prevents the problem usually caused by a thick amorphous material layer of Ti—Si—Co which produces weakly bonded Ti which reacts with fluorine atoms from WF6 during a subsequent CVD W deposition process and causes liner failure due to a volume expansion of the amorphous material. The maximum thickness of the amorphous material layer formed by the present invention method is less than 5 nm which minimizes the line failure problem.
摘要翻译：提供了一种在半导体结构中的金属硅化物层的顶部上形成TiN层的方法，而不形成含有Ti，Co和Si的厚非晶层以及形成的结构。在该方法中，在金属硅化物层的顶部沉积Ti层之后，进行双相退火工艺，其中在不高于500℃的温度下在成形气体（或氨）中进行低温退火。首先进行少于2小时，然后在不低于500℃的第二温度下在含氮气体（或氨）中进行低温退火2小时以形成TiN层。本发明的方法防止了在随后的CVD W沉积过程中由Ti-Si-Co的厚的无定形材料层产生的弱结合的Ti与来自WF6的氟原子反应而产生的弱结合的问题，并导致由于体积膨胀引起的衬管故障无定形材料。通过本发明方法形成的非晶材料层的最大厚度小于5nm，这使线路故障问题最小化。

4. 发明申请

US20130040454A1 Annealing Copper Interconnects 失效
标题翻译：退火铜互连
公开(公告)号：US20130040454A1
公开(公告)日：2013-02-14
申请号：US13205063
申请日：2011-08-08
申请人： Cyril Cabral, JR. , Gregory M. Fritz , Christian Lavoie , Conal E. Murray , Kenneth P. Rodbell
发明人： Cyril Cabral, JR. , Gregory M. Fritz , Christian Lavoie , Conal E. Murray , Kenneth P. Rodbell
IPC分类号： H01L21/28 , H01L21/304 , H01L21/302
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/76828 , H01L21/76886 , H01L21/823814 , H01L21/823842 , H01L21/823871 , H01L21/84 , H01L27/1203
摘要： A method for modifying the chemistry or microstructure of silicon-based technology via an annealing process is provided. The method includes depositing a reactive material layer within a selected proximity to an interconnect, igniting the reactive material layer, and annealing the interconnect via heat transferred from the ignited reactive material layer. The method can also be implemented in connection with a silicide/silicon interface as well as a zone of silicon-based technology.
摘要翻译：提供了一种通过退火工艺改性硅基技术的化学或微结构的方法。该方法包括将反应性材料层沉积在选定的互连附近，点燃反应性材料层，以及通过从点燃的反应性材料层传递的热量使互连件退火。该方法还可以结合硅化物/硅界面以及硅基技术的区域来实现。

5. 发明申请

US20120009771A1 Implantless Dopant Segregation for Silicide Contacts 有权
标题翻译：用于硅胶接触的无植入物掺杂剂分离
公开(公告)号：US20120009771A1
公开(公告)日：2012-01-12
申请号：US12833272
申请日：2010-07-09
申请人： Cyril Cabral, JR. , John M. Cotte , Dinesh R. Koli , Laura L. Kosbar , Mahadevaiyer Krishnan , Christian Lavoie , Stephen M. Rossnagel , Zhen Zhang
发明人： Cyril Cabral, JR. , John M. Cotte , Dinesh R. Koli , Laura L. Kosbar , Mahadevaiyer Krishnan , Christian Lavoie , Stephen M. Rossnagel , Zhen Zhang
IPC分类号： H01L21/3205
CPC分类号： H01L21/28512 , H01L21/28518 , H01L29/456
摘要： A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.
摘要翻译：在半导体材料和硅化物层之间的结处形成分离的界面掺杂剂层的方法包括在半导体材料上沉积掺杂的金属层; 退火所述掺杂金属层和所述半导体材料，其中所述退火使所述掺杂金属层的一部分和所述半导体材料的一部分反应以在所述半导体材料上形成所述硅化物层，并且其中所述退火还导致所述分离的界面掺杂剂层，以形成在半导体材料和硅化物层之间，分离的界面掺杂剂层包含来自掺杂金属层的掺杂剂; 以及从所述硅化物层去除所述掺杂金属层的未反应部分。

6. 发明授权

US07682968B2 Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby 失效
标题翻译：自对准金属与Ge形成的基板和由此形成的结构形成接触
公开(公告)号：US07682968B2
公开(公告)日：2010-03-23
申请号：US12108001
申请日：2008-04-23
申请人： Cyril Cabral, Jr. , Roy A. Carruthers , Christophe Detavernier , Simon Gaudet , Christian Lavoie , Huiling Shang
发明人： Cyril Cabral, Jr. , Roy A. Carruthers , Christophe Detavernier , Simon Gaudet , Christian Lavoie , Huiling Shang
IPC分类号： H01L21/44
CPC分类号： H01L21/28525 , H01L21/28052 , H01L21/28518 , H01L29/665
摘要： A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate.
摘要翻译：提供了一种形成锗硅化物的方法，该方法与由纯金属形成的常规硅化物接触相比更能抵抗蚀刻的含Ge层顶部接触。本发明的方法包括首先提供一种结构，该结构包括位于其中具有源极/漏极区域的含Ge衬底顶部的多个栅极区域。在本发明的该步骤之后，在所述含Ge基材上形成含Si金属层。在暴露的区域中，含Ge衬底与含Si金属层接触。然后进行退火以在含Si金属层和含Ge基板接触的区域中形成锗化硅化合物; 此后，使用选择性蚀刻工艺从结构中除去任何未反应的含Si金属层。在一些实施方案中，附加的退火步骤可以跟随去除步骤。本发明的方法提供了一种在含Ge衬底顶上具有锗硅化物接触层的结构，其中锗硅化物接触层含有比下面的含Ge衬底更多的Si。

7. 发明授权

US07271486B2 Retarding agglomeration of Ni monosilicide using Ni alloys 有权
标题翻译：使用Ni合金抑制Ni一硅化物的团聚
公开(公告)号：US07271486B2
公开(公告)日：2007-09-18
申请号：US11075289
申请日：2005-03-08
申请人： Cyril Cabral, Jr. , Roy A. Carruthers , Christophe Detavernier , James M. E. Harper , Christian Lavoie
发明人： Cyril Cabral, Jr. , Roy A. Carruthers , Christophe Detavernier , James M. E. Harper , Christian Lavoie
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： C04B35/58 , C04B35/58085 , C04B2235/40 , C04B2235/404 , C04B2235/405 , C04B2235/408 , C23C26/00 , C23C30/00 , H01L21/28518 , H01L21/76889
摘要： A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy layer over a portion of a Si-containing substrate, wherein said metal alloy layer comprises of Ni and one or multiple alloying additive(s), where said alloying additive is Ti, V, Ge, Cr, Zr, Nb, Mo, Hf, Ta, W, Re, Rh, Pd or Pt or mixtures thereof; annealing the metal alloy layer at a temperature to convert a portion of said metal alloy layer into a Ni alloy monosilicide layer; and removing remaining metal alloy layer not converted into Ni alloy monosilicide. The alloying additives are selected for phase stability and to retard agglomeration. The alloying additives most efficient in retarding agglomeration are most efficient in producing silicides with low sheet resistance.
摘要翻译：一种用于提供半导体器件中有用的低电阻非聚集Ni单硅化物接触的方法。在制造基本上非团聚的Ni合金一硅化硅的本发明方法中，包括以下步骤：在含Si衬底的一部分上形成金属合金层，其中所述金属合金层包括Ni和一种或多种合金添加剂），其中所述合金添加剂为Ti，V，Ge，Cr，Zr，Nb，Mo，Hf，Ta，W，Re，Rh，Pd或Pt或其混合物; 在将所述金属合金层的一部分转化为Ni合金一硅化物层的温度下退火金属合金层; 并且除去未转化为Ni合金一硅化物的剩余金属合金层。选择合金添加剂用于相稳定性并阻止团聚。延迟聚集中最有效的合金添加剂在生产低薄层电阻的硅化物中是最有效的。

8. 发明申请

US20060121662A1 METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES 有权
公开(公告)号：US20060121662A1
公开(公告)日：2006-06-08
申请号：US10904884
申请日：2004-12-02
申请人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , John Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James Nakos , An Steegen , Clement Wann
发明人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , John Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James Nakos , An Steegen , Clement Wann
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

9. 发明授权

US06777298B2 Elevated source drain disposable spacer CMOS 失效
标题翻译：高排放源一次性间隔CMOS
公开(公告)号：US06777298B2
公开(公告)日：2004-08-17
申请号：US10172649
申请日：2002-06-14
申请人： Ronnen A. Roy , Cyril Cabral, Jr. , Christian Lavoie , Kam-Leung Lee
发明人： Ronnen A. Roy , Cyril Cabral, Jr. , Christian Lavoie , Kam-Leung Lee
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/26513 , H01L21/2652 , H01L21/26586 , H01L21/28035 , H01L21/28114 , H01L21/28518 , H01L21/28525 , H01L21/324 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6659 , Y10S438/924
摘要： In one embodiment of the invention, source and drain regions are formed as well as source and drain contact regions. Thereafter source and drain extension regions are formed. In another embodiment, elevated source and drain regions are formed as well as source and drain extension regions. Thereafter source and drain contact regions are formed at a temperature up to about 600° C. and an annealing time of up to about one minute.
摘要翻译：在本发明的一个实施例中，形成源极和漏极区以及源极和漏极接触区域。此后形成源极和漏极延伸区域。在另一个实施例中，形成升高的源极和漏极区以及源极和漏极延伸区。此后，源极和漏极接触区域形成在高达约600℃的温度和高达约1分钟的退火时间。

10. 发明授权

US06690072B2 Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device 有权
标题翻译：通过垂直自对准COSI2在升高的源极漏极Si / SiGe器件上形成的超低接触电阻CMOS的方法和结构
公开(公告)号：US06690072B2
公开(公告)日：2004-02-10
申请号：US10156782
申请日：2002-05-24
申请人： Cyril Cabral, Jr. , Roy A. Carruthers , Kevin K. Chan , Jack O. Chu , Guy Moshe Cohen , Steven J. Koester , Christian Lavoie , Ronnen A. Roy
发明人： Cyril Cabral, Jr. , Roy A. Carruthers , Kevin K. Chan , Jack O. Chu , Guy Moshe Cohen , Steven J. Koester , Christian Lavoie , Ronnen A. Roy
IPC分类号： H01L2904
CPC分类号： H01L29/41783 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L29/161 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure) of forming a vertically-self-aligned silicide contact to an underlying SiGe layer, includes forming a layer of silicon of a first predetermined thickness on the SiGe layer and forming a layer of metal on the silicon layer, where the metal layer has a second predetermined thickness. A thermal annealing process at a predetermined temperature then forms a silicide of the silicon and metal, where the predetermined temperature is chosen to substantially preclude penetration of the silicide into the underlying SiGe layer.
摘要翻译：形成垂直自对准的硅化物接触到下面的SiGe层的方法（和结构）包括在SiGe层上形成第一预定厚度的硅层，并在硅层上形成一层金属，其中金属层具有第二预定厚度。然后在预定温度下的热退火工艺形成硅和金属的硅化物，其中选择预定温度以基本排除硅化物渗透到下面的SiGe层中。

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