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1. 发明授权

US07808812B2 Robust 8T SRAM cell 有权
标题翻译：坚固的8T SRAM单元
公开(公告)号：US07808812B2
公开(公告)日：2010-10-05
申请号：US12238850
申请日：2008-09-26
申请人： Jack Liu , Shao-Yu Chou , Hung-Jen Liao
发明人： Jack Liu , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： This invention discloses a static random access memory (SRAM) cell which comprises a pair of cross-coupled inverters having a first storage node, a first NMOS transistor having a source and a drain connected between the first storage node and a bit-line, a second NMOS transistor having a source and a drain connected between a gate of the first NMOS transistor and a word-line, the second NMOS transistor having a gate connected to a first column select line, and a third NMOS transistor having a source and a drain connected between a ground (VSS) and the gate of the first NMOS transistor, and a gate connected to a second column select line, the second column select line being complementary to the first column select line.
摘要翻译：本发明公开了一种静态随机存取存储器（SRAM）单元，其包括具有第一存储节点的一对交叉耦合的反相器，具有连接在第一存储节点和位线之间的源极和漏极的第一NMOS晶体管，第二NMOS晶体管，其源极和漏极连接在第一NMOS晶体管的栅极和字线之间，第二NMOS晶体管具有连接到第一列选择线的栅极和具有源极和漏极的第三NMOS晶体管连接在接地（VSS）和第一NMOS晶体管的栅极之间，以及连接到第二列选择线的栅极，第二列选择线与第一列选择线互补。

2. 发明申请

US20100080045A1 ROBUST 8T SRAM CELL 有权
标题翻译：稳定的8T SRAM单元
公开(公告)号：US20100080045A1
公开(公告)日：2010-04-01
申请号：US12238850
申请日：2008-09-26
申请人： Jack Liu , Shao-Yu Chou , Hung-Jen Liao
发明人： Jack Liu , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： This invention discloses a static random access memory (SRAM) cell which comprises a pair of cross-coupled inverters having a first storage node, a first NMOS transistor having a source and a drain connected between the first storage node and a bit-line, a second NMOS transistor having a source and a drain connected between a gate of the first NMOS transistor and a word-line, the second NMOS transistor having a gate connected to a first column select line, and a third NMOS transistor having a source and a drain connected between a ground (VSS) and the gate of the first NMOS transistor, and a gate connected to a second column select line, the second column select line being complementary to the first column select line.
摘要翻译：本发明公开了一种静态随机存取存储器（SRAM）单元，其包括具有第一存储节点的一对交叉耦合的反相器，具有连接在第一存储节点和位线之间的源极和漏极的第一NMOS晶体管，第二NMOS晶体管，其源极和漏极连接在第一NMOS晶体管的栅极和字线之间，第二NMOS晶体管具有连接到第一列选择线的栅极和具有源极和漏极的第三NMOS晶体管连接在接地（VSS）和第一NMOS晶体管的栅极之间，以及连接到第二列选择线的栅极，第二列选择线与第一列选择线互补。

3. 发明申请

US20100124099A1 8T LOW LEAKAGE SRAM CELL 有权
标题翻译： 8T低漏电SRAM单元
公开(公告)号：US20100124099A1
公开(公告)日：2010-05-20
申请号：US12273959
申请日：2008-11-19
申请人： Jui-Jen Wu , Yen-Huei Chen , Shao-Yu Chou , Hung-Jen Liao
发明人： Jui-Jen Wu , Yen-Huei Chen , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C11/412
CPC分类号： G11C11/412
摘要： This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters having a storage node, and a NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the storage node, a read word-line (RWL) and a read bit-line (RBL), respectively, the RWL and RBL being activated during a read operation and not being activated during any write operation.
摘要翻译：本发明公开了一种静态随机存取存储器（SRAM）单元，其包括具有存储节点的一对交叉耦合的反相器，以及具有栅极端子，连接到存储节点的第一和第二源极/漏极端子的NMOS晶体管，分别读取字线（RWL）和读位线（RBL），RWL和RBL在读操作期间被激活，并且在任何写操作期间未被激活。

4. 发明授权

US08077517B2 Distributed VDC for SRAM memory 有权
标题翻译：分布式VDC用于SRAM存储器
公开(公告)号：US08077517B2
公开(公告)日：2011-12-13
申请号：US12338732
申请日：2008-12-18
申请人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
发明人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C11/34
CPC分类号： G11C11/413 , G11C5/04 , G11C5/147
摘要： An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.
摘要翻译：集成电路结构包括存储器。存储器包括与第一存储器宏相同的第一存储器宏和第二存储器宏。第一功率块连接到第一存储器宏，并被配置为向第一存储器宏提供调节电压。第一功率块具有第一输入和第一输出。基本上与第一功率块相同的第二功率块连接到第二存储器宏，并且被配置为向第二存储器宏提供调节电压。第二功率块具有第二输入和第二输出。第一输入和第二输入互连。第一个输出和第二个输出相互连接。

5. 发明授权

US09041069B2 Distributed metal routing 有权
标题翻译：分布式金属布线
公开(公告)号：US09041069B2
公开(公告)日：2015-05-26
申请号：US13007235
申请日：2011-01-14
申请人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
发明人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L23/52 , H01L23/485 , H01L23/528 , H01L23/482 , H01L23/522
CPC分类号： H01L21/76879 , H01L21/768 , H01L21/76832 , H01L23/4824 , H01L23/485 , H01L23/522 , H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.
摘要翻译：公开了一种用于分布式金属布线的系统和方法。一个实施例包括具有覆盖在metal_0层上的metal_1层的metal_0层。金属层1包括分开的平行线，具有不同信号的线分布在metal_1层上。这样的布局减小了metal_0层内的寄生电阻，因为它减小了电流行进的距离。此外，metal_1中的分布式布局允许连接到metal_2层，而不需要通孔的锤头连接。

6. 发明授权

US08395950B2 Memory device having a clock skew generator 有权
标题翻译：具有时钟偏移发生器的存储器件
公开(公告)号：US08395950B2
公开(公告)日：2013-03-12
申请号：US12968582
申请日：2010-12-15
申请人： Tzu-Kuei Lin , Hung-Jen Liao , Shao-Yu Chou , Ching-Wei Wu
发明人： Tzu-Kuei Lin , Hung-Jen Liao , Shao-Yu Chou , Ching-Wei Wu
IPC分类号： G11C7/00
CPC分类号： G11C7/222
摘要： A memory device is provided with memory components and a clock skew generator, supporting at least two read and write operations that can occur coincidentally in read-read, read-write and write-write modes of operation of the memory device. The clock skew generator produces at least two stable and balanced clock channels carrying the at least two clock signals and varies relative timing of the clock signal edges so as to displace the edges in time, in those modes of operation wherein simultaneous edges would lead to detrimental loading.
摘要翻译：存储器件具有存储器组件和时钟偏斜发生器，支持在存储器件的读取，读写和写入 - 写入操作模式中可能巧合地发生的至少两个读和写操作。时钟偏移发生器产生至少两个稳定和平衡的时钟通道，其承载至少两个时钟信号，并且改变时钟信号边沿的相对定时，从而在这些操作模式中随时移动边缘，其中同时的边缘将导致有害的加载。

7. 发明授权

US08363454B2 SRAM bit cell 有权
标题翻译： SRAM位单元
公开(公告)号：US08363454B2
公开(公告)日：2013-01-29
申请号：US13015773
申请日：2011-01-28
申请人： Ping Wang , Hung-Jen Liao , Yen-Huei Chen , Jihi-Yu Lin , Shao-Yu Chou
发明人： Ping Wang , Hung-Jen Liao , Yen-Huei Chen , Jihi-Yu Lin , Shao-Yu Chou
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A semiconductor memory bit cell includes an inverter latch including a pair of cross-coupled inverters. A first transistor has a gate coupled to a first control line and a source coupled to the inverter latch, and a second transistor has a gate coupled to a second control line and a drain coupled to the drain of the first transistor at a first node. A third transistor has a source coupled to the first node and a gate coupled to a word line, and a fourth transistor has a gate coupled to a source of the second transistor and to the inverter latch. A fifth transistor has a gate coupled to the word line and a drain coupled to a read bit line.
摘要翻译：半导体存储器位单元包括具有一对交叉耦合的反相器的反相器锁存器。第一晶体管具有耦合到第一控制线的栅极和耦合到反相器锁存器的源极，并且第二晶体管具有耦合到第二控制线的栅极和在第一节点耦合到第一晶体管的漏极的漏极。第三晶体管具有耦合到第一节点的源极和耦合到字线的栅极，并且第四晶体管具有耦合到第二晶体管的源极和反相器锁存器的栅极。第五晶体管具有耦合到字线的栅极和耦合到读位线的漏极。

8. 发明申请

US20120256235A1 LAYOUT SCHEME AND METHOD FOR FORMING DEVICE CELLS IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于在半导体器件中形成器件电池的布局方案和方法
公开(公告)号：US20120256235A1
公开(公告)日：2012-10-11
申请号：US13082497
申请日：2011-04-08
申请人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
发明人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L27/1116 , H01L21/768 , H01L27/0207 , H01L27/11 , H01L2027/11887
摘要： A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.
摘要翻译：用于形成字线解码器装置和具有字线解码器单元的其它装置的方法和布局提供了使用非DPL光刻操作形成金属互连层，并且使用下部或中间金属层或下部导电材料提供了用于缝合的远端布置的晶体管。晶体管可以设置在纵向布置的字线解码器或其他单元中或其附近，并且使用金属或导电材料的导电耦合降低晶体管之间的栅极电阻并避免RC信号延迟。

9. 发明申请

US20100157692A1 Distributed VDC for SRAM Memory 有权
标题翻译：分布式VDC用于SRAM存储器
公开(公告)号：US20100157692A1
公开(公告)日：2010-06-24
申请号：US12338732
申请日：2008-12-18
申请人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
发明人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C11/413 , G11C5/04 , G11C5/147
摘要： An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.
摘要翻译：集成电路结构包括存储器。存储器包括与第一存储器宏相同的第一存储器宏和第二存储器宏。第一功率块连接到第一存储器宏，并被配置为向第一存储器宏提供调节电压。第一功率块具有第一输入和第一输出。基本上与第一功率块相同的第二功率块连接到第二存储器宏，并且被配置为向第二存储器宏提供调节电压。第二功率块具有第二输入和第二输出。第一输入和第二输入互连。第一个输出和第二个输出相互连接。

10. 发明授权

US08928113B2 Layout scheme and method for forming device cells in semiconductor devices 有权
标题翻译：用于在半导体器件中形成器件单元的布局方案和方法
公开(公告)号：US08928113B2
公开(公告)日：2015-01-06
申请号：US13082497
申请日：2011-04-08
申请人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
发明人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： H01L23/52 , H01L27/108 , H01L29/94 , H01L21/70 , H01L27/02 , H01L27/11 , H01L27/118
CPC分类号： H01L27/1116 , H01L21/768 , H01L27/0207 , H01L27/11 , H01L2027/11887
摘要： A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.
摘要翻译：用于形成字线解码器装置和具有字线解码器单元的其它装置的方法和布局提供了使用非DPL光刻操作形成金属互连层，并且使用下部或中间金属层或下部导电材料提供了用于缝合的远端布置的晶体管。晶体管可以设置在纵向布置的字线解码器或其他单元中或其附近，并且使用金属或导电材料的导电耦合降低晶体管之间的栅极电阻并避免RC信号延迟。

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