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    • 2. 发明授权
    • Method of manufacturing vertical power device
    • 垂直功率器件的制造方法
    • US5985708A
    • 1999-11-16
    • US816596
    • 1997-03-13
    • Akio NakagawaNaoharu SugiyamaTomoko MatsudaiNorio YasuharaAtsusi KurobeHideyuki FunakiYusuke KawaguchiYoshihiro Yamaguchi
    • Akio NakagawaNaoharu SugiyamaTomoko MatsudaiNorio YasuharaAtsusi KurobeHideyuki FunakiYusuke KawaguchiYoshihiro Yamaguchi
    • H01L27/12H01L29/73H01L29/739H01L29/786H01L21/8249
    • H01L29/78696H01L27/1203H01L29/7317H01L29/7394H01L29/78612H01L29/78624H01L29/78639H01L29/78645H01L29/78687
    • A semiconductor apparatus comprising a vertical type semiconductor device having a first conducting type semiconductor substrate, a drain layer formed on the surface of the semiconductor substrate, a drain electrode formed on the surface of the drain layer, a second conducting type base layer selectively formed on the surface of the semiconductor substrate opposite to the drain layer, a first conducting type source layer selectively formed on the surface of the second conducting type base layer, a source electrode formed on the first conducting type source layer and the second conducting type base layer, and a gate electrode formed in contact with the first conducting type source layer, the second conducting type base layer and the semiconductor substrate through a gate insulating film and a lateral semiconductor device having an insulating layer formed in a region of the surface of the semiconductor substrate different from the second conducting type base layer, and a polycrystalline semiconductor layer formed on the insulating layer and having a first conducting type region and a second conducting type region, wherein the first conducting type source layer of the vertical semiconductor device and the first conducting type region of the polycrystalline semiconductor layer are simultaneously formed.
    • 一种半导体装置,包括具有第一导电型半导体衬底的垂直型半导体器件,形成在半导体衬底的表面上的漏极层,形成在漏极层的表面上的漏电极,第二导电型基极层, 所述半导体衬底的与所述漏极层相对的表面,选择性地形成在所述第二导电型基极层的表面上的第一导电型源极层,形成在所述第一导电型源极层和所述第二导电型基极层上的源电极, 以及通过栅极绝缘膜与第一导电型源极层,第二导电型基极层和半导体基板接触形成的栅电极,以及在半导体基板的表面的区域中形成有绝缘层的侧面半导体装置 不同于第二导电型基底层,和多晶 半导体层形成在绝缘层上并具有第一导电类型区域和第二导电类型区域,其中垂直半导体器件的第一导电型源极层和多晶半导体层的第一导电类型区域同时形成。
    • 9. 发明授权
    • Lateral IGBT
    • 横向IGBT
    • US5920087A
    • 1999-07-06
    • US970103
    • 1997-11-13
    • Akio NakagawaTomoko MatsudaiHideyuki Funaki
    • Akio NakagawaTomoko MatsudaiHideyuki Funaki
    • H01L21/331H01L29/06H01L29/739H01L29/74H01L27/01H01L31/111
    • H01L29/66325H01L29/0696H01L29/7394H01L29/7398
    • A sub-gate electrode is arranged to face, through a gate insulating film, a surface of a first p-type base layer which is interposed between a first n-type source layer and an n-type drift layer, and a surface of a second p-type base layer which is interposed between a second n-type source layer and the n-type drift layer and faces the first p-type base layer. A main gate electrode is arranged to face, through a gate insulating film, a surface of the second p-type base layer which is interposed between the second n-type source layer and the n-type drift layer and does not face the first p-type base layer. Three n-type MOSFETs are constructed such that one n-type channel is to be formed in the first p-type base layer and two n-type channels are to be formed in the second p-type base layer. The three channels are to be formed, so that the channel width is effectively enlarged and the current density is increased. The second p-type base layer has a length of 10 .mu.m or less in the drifting direction.
    • 子栅电极配置成通过栅极绝缘膜与介于第一n型源极层和n型漂移层之间的第一p型基极层的表面和 第二p型基极层,其介于第二n型源极层和n型漂移层之间并且面向第一p型基极层。 主栅极布置成通过栅极绝缘膜面对介于第二n型源极层和n型漂移层之间的第二p型基极层的表面,并且不面向第一p 型基层。 构造三个n型MOSFET,使得在第一p型基极层中形成一个n型沟道,并且在第二p型基极层中形成两个n型沟道。 要形成三个通道,从而有效地扩大通道宽度,增加电流密度。 第二p型基层在漂移方向上的长度为10μm以下。