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1. 发明授权

US07890561B2 Random number generator 失效
标题翻译：随机数发生器
公开(公告)号：US07890561B2
公开(公告)日：2011-02-15
申请号：US11204402
申请日：2005-08-16
申请人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
发明人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
IPC分类号： G06F1/02 , G06F7/58
CPC分类号： G06F7/588 , H04L9/001 , H04L9/0869
摘要： A random number generator, a method, and a computer program product are provided for producing a random number seed. Each oscillator within an array of oscillators operates at a different frequency. The operating frequencies of each oscillator are not harmonically related, such that no integer multiple exists between the frequencies of any two oscillators. In one embodiment, the outputs of the array of oscillators connect to a multiple input latch. The multiple input latch also receives a sample signal, which is a clock signal. The clock signal samples the outputs of the array of oscillators, and the multiple input latch in conjunction with the random number determination logic (“RNDL”) produces a digital output (0 or 1) for each oscillator within the array. The RNDL uses these digital outputs to create a random number seed.
摘要翻译：提供随机数生成器，方法和计算机程序产品用于产生随机数种子。振荡器阵列内的每个振荡器以不同的频率工作。每个振荡器的工作频率不是谐波相关的，使得在任何两个振荡器的频率之间不存在整数倍。在一个实施例中，振荡器阵列的输出连接到多输入锁存器。多输入锁存器还接收作为时钟信号的采样信号。时钟信号对振荡器阵列的输出采样，并且多输入锁存器与随机数确定逻辑（“RNDL”）一起为阵列内的每个振荡器产生数字输出（0或1）。 RNDL使用这些数字输出创建一个随机数字种子。

2. 发明授权

US07279996B2 Method of functionality testing for a ring oscillator 失效
公开(公告)号：US07279996B2
公开(公告)日：2007-10-09
申请号：US11204408
申请日：2005-08-16
申请人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
发明人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , H03K5/133
摘要： A method and apparatus is provided for testing the logic functionality and electrical continuity of a ring oscillator comprising an odd number of inverters connected to form a closed loop. In the method and apparatus, a known value is forced through the ring oscillator, to test the complete circuit path thereof. Thus, a low overhead deterministic test of the functionality of the ring oscillator is provided. In a useful embodiment of the invention, a method is provided for testing functionality and electrical continuity in a ring oscillator, wherein a first test device is inserted between the input of a first inverter and the output of an adjacent second inverter. The first test device is then operated to apply first and second test bits as input test signals to the first inverter input. The embodiment further comprises detecting the response to the applied first and second test bit signals at the output of the second inverter, and using the detected responses in providing an evaluation of functionality of the ring oscillator.

3. 发明授权

US07233212B2 Oscillator array with row and column control 有权
标题翻译：具有行和列控制的振荡器阵列
公开(公告)号：US07233212B2
公开(公告)日：2007-06-19
申请号：US11095895
申请日：2005-03-31
申请人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
发明人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
IPC分类号： H03B29/00 , H03K3/03
CPC分类号： G06F7/588 , H03K3/0315 , H03K3/84
摘要： A circuit topology which can be used to create an array of individually tuned oscillators operating at different frequencies determined by common control inputs and an easily managed variation in design dimensions of several components is provided. An array of oscillators are provided arranged in columns and rows. Each oscillator in a column is unique from the other oscillators in the column based on number of stages in the oscillator and fanout so that each oscillator will operate at a unique frequency. Oscillators of different columns within the array may differ by a common setting of the selects to these oscillators and the physical ordering of the oscillators in the column to further reduce the possibility of injection locking. A base delay cell provides selects to each column of oscillators such that each column may be programmed to operate at a different frequency from its neighbors.
摘要翻译：提供了一种电路拓扑结构，可用于创建由通用控制输入确定的不同频率运行的单独调谐的振荡器阵列，以及易于管理的多个组件的设计尺寸变化。提供了一列列和列排列的振荡器阵列。列中的每个振荡器都基于列中的其他振荡器是独特的，基于振荡器和扇出的级数，使得每个振荡器将以唯一的频率工作。阵列中不同列的振荡器可能会通过对这些振荡器的选择的共同设置以及列中的振荡器的物理顺序而不同，以进一步降低注入锁定的可能性。基本延迟单元为每列振荡器提供选择，使得每列可被编程为以与其邻居不同的频率工作。

4. 发明授权

US06335650B1 Method and apparatus for adjusting time delays in circuits with multiple operating supply voltages 有权
标题翻译：用于调整具有多个工作电源电压的电路中的时间延迟的方法和装置
公开(公告)号：US06335650B1
公开(公告)日：2002-01-01
申请号：US09670829
申请日：2000-09-28
申请人： David William Boerstler , Harm Peter Hofstee , Hung Cai Ngo , Kevin John Nowka
发明人： David William Boerstler , Harm Peter Hofstee , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03H1126
CPC分类号： H03K5/133 , H03K19/00384 , H03K19/018585 , H03K2005/0013
摘要： A method and apparatus for adjusting time delays in circuits with multiple operating supply voltages are disclosed. A voltage level detector and a delay means are coupled to a critical timing circuit of an integrated circuit capable of operating at multiple supply voltages. The voltage level detector detects a supply voltage at which the integrated circuit is operating. When the operating supply voltage of the integrated circuit changes from a first voltage level to a second voltage level, the voltage level detector sends a signal to the delay means and to a current enhancement circuit such that the delay means and current enhancement circuit can automatically modify the delay of the switching time of an output signal from the critical timing circuit.
摘要翻译：公开了一种用于调整具有多个工作电源电压的电路中的时间延迟的方法和装置。电压电平检测器和延迟装置耦合到能够在多个电源电压下工作的集成电路的关键定时电路。电压电平检测器检测集成电路正在工作的电源电压。当集成电路的工作电源电压从第一电压电平变化到第二电压电平时，电压电平检测器向延迟装置和当前增强电路发送信号，使得延迟装置和电流增强电路可以自动修改来自关键定时电路的输出信号的切换时间的延迟。

5. 发明授权

US06983387B2 Microprocessor chip simultaneous switching current reduction method and apparatus 有权
标题翻译：微处理器芯片同时开关电流降低方法和装置
公开(公告)号：US06983387B2
公开(公告)日：2006-01-03
申请号：US10273617
申请日：2002-10-17
申请人： David William Boerstler , Sang Hoo Dhong , Harm Peter Hofstee , Peichun Peter Liu
发明人： David William Boerstler , Sang Hoo Dhong , Harm Peter Hofstee , Peichun Peter Liu
IPC分类号： H03L7/06
CPC分类号： G06F1/06 , G06F1/10
摘要： Disclosed is an electronic chip containing a plurality of electronic circuit partitions, distributed over the area of the chip, each including a processor core and a clock phase domain different from cores in other partitions of the chip. A source of same frequency, but different phase clock signals representing different clock domains, provides different phase signals to adjacent partitions for the purpose of reducing instantaneous magnitude switching currents. Intra-chip communication circuitry distributes control and data signals between partitions.
摘要翻译：公开了一种电子芯片，其包含分布在芯片的区域上的多个电子电路分区，每个电子部件分别包括处理器核心和与芯片的其他分区中的核心不同的时钟相位域。相同频率的源，但是表示不同时钟域的不同相位时钟信号，为了减小瞬时幅度切换电流，向相邻分区提供不同的相位信号。片内通信电路在分区之间分配控制和数据信号。

6. 发明授权

US07747892B2 System for automatically selecting intermediate power supply voltages for intermediate level shifters 失效
标题翻译：用于自动选择中间电平转换器的中间电源电压的系统
公开(公告)号：US07747892B2
公开(公告)日：2010-06-29
申请号：US12036936
申请日：2008-02-25
申请人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
IPC分类号： G06F1/04
CPC分类号： H03K19/017581 , H03K19/00323 , H03K19/00346
摘要： The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal. A fixed potential is configured to generate a second comparison signal. A comparator is coupled to the filter, the fixed potential, and the counter and configured to receive the first comparison signal and the second comparison signal, and to generate the comparison result signal in response to the received first comparison signal and the second comparison signal.
摘要翻译：本发明提供了一种系统，包括电平移位器，其被配置为从第一功率域接收第一时钟信号，以接收计数器信号，以响应于所接收的计数器信号选择多个中间电压中的一个，并产生响应于所接收的第一时钟信号和所选择的中间电压的第二时钟信号。计数器耦合到电平移位器并被配置为接收分频时钟信号和比较结果信号，并且响应于接收到的分频时钟信号和比较结果信号产生计数器信号。分频器耦合到计数器并且被配置为接收第一时钟信号并响应于接收到的第一时钟信号产生分频时钟信号。滤波器耦合到电平移位器并且被配置为接收第二时钟信号并响应于所接收的第二时钟信号产生第一比较信号。固定电位被配置为产生第二比较信号。比较器耦合到滤波器，固定电位和计数器，并且被配置为接收第一比较信号和第二比较信号，并且响应于接收的第一比较信号和第二比较信号产生比较结果信号。

7. 发明授权

US07716516B2 Method for controlling operation of microprocessor which performs duty cycle correction process 失效
标题翻译：用于控制执行占空比校正处理的微处理器的操作的方法
公开(公告)号：US07716516B2
公开(公告)日：2010-05-11
申请号：US11471819
申请日：2006-06-21
申请人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry, Jr. , Sang Hoo Dhong
发明人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry, Jr. , Sang Hoo Dhong
IPC分类号： G06F1/04 , G06F1/24 , G06F11/00
CPC分类号： G06F1/04
摘要： A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.
摘要翻译：用于向微处理器提供电源电压的技术。在微处理器的正常运算处理之前，执行用于调整微处理器内的时钟信号占空比的占空比校正处理。在用于调整占空比的占空比校正处理中，调整时钟信号的占空比以使微处理器仍然可操作的电源电压最小化。

8. 发明授权

US07595675B2 Duty cycle measurement method and apparatus that operates in a calibration mode and a test mode 有权
标题翻译：在校准模式和测试模式下工作的占空比测量方法和装置
公开(公告)号：US07595675B2
公开(公告)日：2009-09-29
申请号：US11381031
申请日：2006-05-01
申请人： David William Boerstler , Eskinder Hailu , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K5/04
CPC分类号： G01R31/31727
摘要： The disclosed methodology and apparatus measure the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.
摘要翻译：所公开的方法和装置测量时钟电路提供给占空比测量（DCM）电路的参考时钟信号的占空比。在一个实施例中，DCM电路包括由电荷泵驱动的电容器。参考时钟信号驱动电荷泵。时钟电路在多个已知的占空比值之间改变参考时钟信号的占空比。 DCM电路将对应于每个已知占空比值的合成电容电压值存储在数据存储器中。 DCM电路通过电荷泵向电容器施加具有未知占空比的测试时钟信号，从而将电容器充电到对应于测试时钟信号占空比的新电压值。控制软件访问数据存储，以确定测试时钟信号对应的占空比。

9. 发明授权

US07330061B2 Method and apparatus for correcting the duty cycle of a digital signal 失效
标题翻译：用于校正数字信号占空比的方法和装置
公开(公告)号：US07330061B2
公开(公告)日：2008-02-12
申请号：US11381050
申请日：2006-05-01
申请人： David William Boerstler , Eskinder Hailu , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K5/04
CPC分类号： H03K5/1565
摘要： The disclosed methodology and apparatus measure and correct the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds, thus providing a measured duty cycle. The apparatus generates an error signal when the measured duty cycle varies from a predetermined duty cycle. The apparatus includes a variable duty cycle clock generator that alters the duty cycle of the test clock signal to reduce the error.
摘要翻译：所公开的方法和装置测量并校正时钟电路提供给占空比测量（DCM）电路的参考时钟信号的占空比。在一个实施例中，DCM电路包括由电荷泵驱动的电容器。参考时钟信号驱动电荷泵。时钟电路在多个已知的占空比值之间改变参考时钟信号的占空比。 DCM电路将对应于每个已知占空比值的合成电容电压值存储在数据存储器中。 DCM电路通过电荷泵向电容器施加具有未知占空比的测试时钟信号，从而将电容器充电到对应于测试时钟信号占空比的新电压值。控制软件访问数据存储器以确定测试时钟信号对应的占空比，从而提供测量的占空比。当测量的占空比从预定的占空比变化时，该装置产生误差信号。该装置包括可变占空比时钟发生器，其改变测试时钟信号的占空比以减少误差。

10. 发明授权

US06958636B2 Charge leakage correction circuit for applications in PLLs 有权
标题翻译：针对PLL应用的充电泄漏校正电路
公开(公告)号：US06958636B2
公开(公告)日：2005-10-25
申请号：US10759942
申请日：2004-01-16
申请人： David William Boerstler , Franklin Manuel Baez , Eskinder Hailu
发明人： David William Boerstler , Franklin Manuel Baez , Eskinder Hailu
IPC分类号： H03K5/13 , H03L7/06 , H03L7/089
CPC分类号： H03L7/0891 , H03L7/0895
摘要： An apparatus, a method, and a computer program are provided for correcting charge in a Phased Lock Loop (PLL). Typically, PLL's utilize a Low Pass Filter (LPF). However, as a result of improvement of Complimentary Metal-Oxide on a Semiconductor (CMOS) technology charge leakage has become prevalent within LPFs. As a result, the method, apparatus, and computer program provide a device and/or methodology for correcting for charge leakage.
摘要翻译：提供了一种用于在相位锁定环（PLL）中校正电荷的装置，方法和计算机程序。通常，PLL使用低通滤波器（LPF）。然而，由于半导体（CMOS）技术上的免费金属氧化物的改进，电荷泄漏已经在LPF内普遍存在。因此，该方法，装置和计算机程序提供用于校正电荷泄漏的装置和/或方法。

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