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1. 发明授权

US07453312B2 Voltage regulator outputting positive and negative voltages with the same offsets 有权
公开(公告)号：US07453312B2
公开(公告)日：2008-11-18
申请号：US12116229
申请日：2008-05-07
申请人： Yen-Tai Lin , Ching-Yuan Lin
发明人： Yen-Tai Lin , Ching-Yuan Lin
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , H02M2001/009 , H02M2003/071
摘要： A voltage regulator has a first charge circuit, a second charge circuit, and a control circuit. The control circuit has five input terminals and two output terminals. The five input terminals are respectively coupled to a reference voltage, a first voltage source, a second voltage source, an output terminal of the first charge circuit, and an output terminal of the second charge circuit. The control circuit equalizes a voltage difference between the output terminal of the first charge circuit and the first voltage source and a voltage difference between the second voltage source and the output terminal of the second charge circuit.

2. 发明申请

US20070252640A1 VOLTAGE REGULATOR OUTPUTTING POSITIVE AND NEGATIVE VOLTAGES WITH THE SAME OFFSETS 有权
标题翻译：电压调节器输出具有相同偏置的正负电压
公开(公告)号：US20070252640A1
公开(公告)日：2007-11-01
申请号：US11380661
申请日：2006-04-28
申请人： Yen-Tai Lin , Ching-Yuan Lin
发明人： Yen-Tai Lin , Ching-Yuan Lin
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , H02M2001/009 , H02M2003/071
摘要： A voltage regulator has a first charge circuit, a second charge circuit, and a control circuit. The control circuit has five input terminals and two output terminals. The five input terminals are respectively coupled to a reference voltage, a first voltage source, a second voltage source, an output terminal of the first charge circuit, and an output terminal of the second charge circuit. The control circuit equalizes a voltage difference between the output terminal of the first charge circuit and the first voltage source and a voltage difference between the second voltage source and the output terminal of the second charge circuit.
摘要翻译：电压调节器具有第一充电电路，第二充电电路和控制电路。控制电路有五个输入端和两个输出端。五个输入端子分别耦合到参考电压，第一电压源，第二电压源，第一充电电路的输出端子和第二充电电路的输出端子。控制电路使第一充电电路的输出端和第一电压源之间的电压差与第二电压源与第二充电电路的输出端之间的电压差相等。

3. 发明申请

US20070181937A1 P-CHANNEL NON-VOLATILE MEMORY AND OPERATING METHOD THEREOF 审中-公开
标题翻译： P-CHANNEL非易失性存储器及其操作方法
公开(公告)号：US20070181937A1
公开(公告)日：2007-08-09
申请号：US11307472
申请日：2006-02-09
申请人： Yen-Tai Lin
发明人： Yen-Tai Lin
IPC分类号： H01L29/788
CPC分类号： H01L27/115
摘要： A P-channel non-volatile memory is described. The P-channel non-volatile memory includes a substrate, a first memory cell, and second memory cell. An N-well is disposed over the substrate, and the first cell and the second cell are disposed over the N-well. The first memory cell includes a first gate, a first charge storage structure, a first doped region and a second doped region. The first doped region and the second doped region are disposed in the substrate on the respective sides of the first gate. The second cell includes a second gate, a second charge storage structure, a third doped region, and the second doped region. The third doped region and the second doped region are disposed in the substrate on the respective sides of the second gate. The second cell and the first cell share the second doped region.
摘要翻译：描述P沟道非易失性存储器。 P沟道非易失性存储器包括衬底，第一存储单元和第二存储单元。在衬底上设置N阱，并且将第一电池和第二电池设置在N阱上。第一存储单元包括第一栅极，第一电荷存储结构，第一掺杂区和第二掺杂区。第一掺杂区域和第二掺杂区域设置在第一栅极的相应侧面上的衬底中。第二单元包括第二栅极，第二电荷存储结构，第三掺杂区和第二掺杂区。第三掺杂区域和第二掺杂区域设置在第二栅极的相应侧上的衬底中。第二单元和第一单元共享第二掺杂区。

4. 发明授权

US07254086B2 Method for accessing memory 有权
标题翻译：访问内存的方法
公开(公告)号：US07254086B2
公开(公告)日：2007-08-07
申请号：US11163431
申请日：2005-10-19
申请人： Ching-Yuan Lin , Hong-Yi Liao , Yen-Tai Lin , Shih-Yun Lin , Chun-Hung Lu
发明人： Ching-Yuan Lin , Hong-Yi Liao , Yen-Tai Lin , Shih-Yun Lin , Chun-Hung Lu
IPC分类号： G11C8/00
CPC分类号： G11C16/105 , G11C16/3495 , G11C17/146 , G11C17/18 , G11C2216/26
摘要： The present invention provides a method for accessing a memory. The memory contains M one-time programmable memory blocks, and each has a first memory sector and a second memory sector. The method includes: selecting a first target memory block and reading the first target memory block. The step of selecting a first target memory block is performed by comparing the second memory sectors of N one-time programmable memory blocks from M one-time programmable memory blocks by following a search rule to select the first target memory block.
摘要翻译：本发明提供一种访问存储器的方法。存储器包含M个一次性可编程存储器块，并且每个具有第一存储器扇区和第二存储器扇区。该方法包括：选择第一目标存储块并读取第一目标存储块。通过按照搜索规则比较来自M个一次可编程存储器块的N个一次可编程存储器块的第二存储器扇区来选择第一目标存储器块来选择第一目标存储器块的步骤来选择第一目标存储器块。

5. 发明授权

US06819620B2 Power supply device with reduced power consumption 有权
标题翻译：电源设备功耗降低
公开(公告)号：US06819620B2
公开(公告)日：2004-11-16
申请号：US10248495
申请日：2003-01-23
申请人： Yen-Tai Lin , Ching-Yuan Lin , Chien-Hung Ho
发明人： Yen-Tai Lin , Ching-Yuan Lin , Chien-Hung Ho
IPC分类号： G11C1134
CPC分类号： G11C16/30
摘要： A power supply used for providing a flash memory with an operating voltage has a plurality of memory blocks and a plurality of decoders corresponding to the memory blocks. Each memory block has a plurality of memory cells for storing binary data. Each decoder is used for selecting memory cells in the corresponding memory block. The power supply has at least three power sources for generating different voltages, and controls the power sources for making a voltage difference between a high voltage level and a low voltage level of the unselected decoder less than a voltage difference between a high voltage level and a low voltage level of the selected decoder.
摘要翻译：用于提供具有工作电压的闪速存储器的电源具有多个存储块和对应于存储块的多个解码器。每个存储块具有用于存储二进制数据的多个存储单元。每个解码器用于选择相应存储块中的存储单元。电源具有用于产生不同电压的至少三个电源，并且控制电源以使未选择的解码器的高电压电平和低电压电平之间的电压差小于高电压电平和高电压电平之间的电压差所选解码器的低电压电平。

6. 发明授权

US06617637B1 Electrically erasable programmable logic device 失效
标题翻译：电可擦除可编程逻辑器件
公开(公告)号：US06617637B1
公开(公告)日：2003-09-09
申请号：US10065718
申请日：2002-11-13
申请人： Ching-Hsiang Hsu , Yen-Tai Lin , Chih-Hsun Chu , Shih-Jye Shen , Ching-Sung Yang , Ming-Chou Ho
发明人： Ching-Hsiang Hsu , Yen-Tai Lin , Chih-Hsun Chu , Shih-Jye Shen , Ching-Sung Yang , Ming-Chou Ho
IPC分类号： H01L2976
CPC分类号： H01L27/115 , G11C2216/10 , H01L29/42324 , H01L29/7885
摘要： An electrically erasable programmable logic device (EEPLD) includes a P type semiconductor substrate. An N type well is formed on the P type semiconductor substrate. A first PMOS transistor is formed on the N well. The first PMOS transistor comprises a floating gate, a first P+ doped region serving as a drain of the first PMOS transistor, and a P− doped region encompassing an N+ doped region for erasing the first PMOS transistor. A second PMOS transistor is also formed on the N well and serially connected to the first PMOS transistor. The first P+ doped region functions as a source of the second PMOS transistor, and the second PMOS transistor further comprises a select gate and a second P+ doped region serving as a drain of the second PMOS transistor.
摘要翻译：电可擦除可编程逻辑器件（EEPLD）包括P型半导体衬底。在P型半导体衬底上形成N型阱。在N阱上形成第一PMOS晶体管。第一PMOS晶体管包括浮置栅极，用作第一PMOS晶体管的漏极的第一P +掺杂区域和包围用于擦除第一PMOS晶体管的N +掺杂区域的P-掺杂区域。第二PMOS晶体管也形成在N阱上并串联连接到第一PMOS晶体管。第一P +掺杂区域用作第二PMOS晶体管的源极，并且第二PMOS晶体管还包括用作第二PMOS晶体管的漏极的选择栅极和第二P +掺杂区域。

7. 发明授权

US5998846A Layout structure of multi-use coupling capacitors in reducing ground bounces and replacing faulty logic components 失效
标题翻译：多用耦合电容器的布局结构，可减少地面反弹和更换故障逻辑元件
公开(公告)号：US5998846A
公开(公告)日：1999-12-07
申请号：US50621
申请日：1998-03-30
申请人： Tzong-Shi Jan , Yen-Tai Lin
发明人： Tzong-Shi Jan , Yen-Tai Lin
IPC分类号： H01L27/02 , H01L29/72
CPC分类号： H01L27/0207
摘要： A first mask includes a well mask formed over a first portion of the wafer to define a first conductive type well in the wafer. A first polysilicon mask is formed over the well mask including a plurality of first structures and a plurality of second structures to cover a first polysilicon layer, thereby defining polysilicon gates. A first implanting mask is formed over the first polysilicon mask for forming second conductive type region. A second implanting mask is formed over the first polysilicon mask for forming first conductive type region. A second polysilicon mask is formed between gates of a second conductive type MOS and gates of a first conductive type MOS. A contact hole mask is formed over the second polysilicon mask for forming contact holes. A metal mask is formed over the contact hole mask for forming connection.
摘要翻译：第一掩模包括在晶片的第一部分上形成的阱掩模，以在晶片中限定第一导电类型阱。第一多晶硅掩模形成在阱掩模之上，包括多个第一结构和多个第二结构以覆盖第一多晶硅层，从而限定多晶硅栅极。第一注入掩模形成在第一多晶硅掩模上，用于形成第二导电类型区域。在第一多晶硅掩模上形成第二注入掩模，用于形成第一导电类型区域。在第二导电型MOS的栅极和第一导电型MOS的栅极之间形成第二多晶硅掩模。在第二多晶硅掩模上形成接触孔掩模以形成接触孔。在用于形成连接的接触孔掩模上形成金属掩模。

8. 发明授权

US08373485B2 Voltage level shifting apparatus 有权
标题翻译：电压电平转换装置
公开(公告)号：US08373485B2
公开(公告)日：2013-02-12
申请号：US13090283
申请日：2011-04-20
申请人： Chen-Hao Po , Yen-Tai Lin , Way-Chen Wu , Ching-Shan Chien
发明人： Chen-Hao Po , Yen-Tai Lin , Way-Chen Wu , Ching-Shan Chien
IPC分类号： H03L5/00
CPC分类号： H03K3/356182
摘要： A voltage level shifting apparatus is disclosed. The voltage level shifting apparatus has a cross-coupled transistor pair, a plurality of transistor pairs, a first diode string, a second diode string and an input transistor pair. One of the transistor pairs is coupled to the cross-coupled transistor pair, and the transistor pairs are controlled by a plurality of reference voltages. The first and the second diode strings are coupled between two of the transistor pairs. Each of the first and the second diode strings has at least one diode. The input transistor pair receives a first and a second input voltage, and the first and second input voltages are complementary signals. The cross-coupled transistor pair generates and outputs a first output voltage and a second output voltage by shifting the voltage level of the first and the second input voltage.
摘要翻译：公开了一种电压电平转换装置。电压电平移位装置具有交叉耦合晶体管对，多个晶体管对，第一二极管串，第二二极管串和输入晶体管对。晶体管对中的一个耦合到交叉耦合晶体管对，并且晶体管对由多个参考电压控制。第一和第二二极管串耦合在两个晶体管对之间。第一和第二二极管串中的每一个具有至少一个二极管。输入晶体管对接收第一和第二输入电压，第一和第二输入电压是互补信号。交叉耦合晶体管对通过移位第一和第二输入电压的电压电平来产生并输出第一输出电压和第二输出电压。

9. 发明申请

US20080165587A1 OPERATING METHOD OF P-CHANNEL NON-VOLATILE MEMORY 失效
标题翻译： P-CHANNEL非易失性存储器的操作方法
公开(公告)号：US20080165587A1
公开(公告)日：2008-07-10
申请号：US12046477
申请日：2008-03-12
申请人： Yen-Tai Lin
发明人： Yen-Tai Lin
IPC分类号： G11C11/34
CPC分类号： H01L27/115
摘要： A P-channel non-volatile memory is described. The P-channel non-volatile memory includes a substrate, a first memory cell, and second memory cell. An N-well is disposed over the substrate, and the first cell and the second cell are disposed over the N-well. The first memory cell includes a first gate, a first charge storage structure, a first doped region and a second doped region. The first doped region and the second doped region are disposed in the substrate on the respective sides of the first gate. The second cell includes a second gate, a second charge storage structure, a third doped region, and the second doped region. The third doped region and the second doped region are disposed in the substrate on the respective sides of the second gate. The second cell and the first cell share the second doped region.
摘要翻译：描述P沟道非易失性存储器。 P沟道非易失性存储器包括衬底，第一存储单元和第二存储单元。在衬底上设置N阱，并且将第一电池和第二电池设置在N阱上。第一存储单元包括第一栅极，第一电荷存储结构，第一掺杂区和第二掺杂区。第一掺杂区域和第二掺杂区域设置在第一栅极的相应侧面上的衬底中。第二单元包括第二栅极，第二电荷存储结构，第三掺杂区和第二掺杂区。第三掺杂区域和第二掺杂区域设置在第二栅极的相应侧上的衬底中。第二单元和第一单元共享第二掺杂区。

10. 发明申请

US20080159008A1 OPERATING METHOD OF P-CHANNEL NON-VOLATILE MEMORY 审中-公开
公开(公告)号：US20080159008A1
公开(公告)日：2008-07-03
申请号：US12045030
申请日：2008-03-10
申请人： Yen-Tai Lin
发明人： Yen-Tai Lin
IPC分类号： G11C11/34
CPC分类号： H01L27/115
摘要： A P-channel non-volatile memory is described. The P-channel non-volatile memory includes a substrate, a first memory cell, and second memory cell. An N-well is disposed over the substrate, and the first cell and the second cell are disposed over the N-well. The first memory cell includes a first gate, a first charge storage structure, a first doped region and a second doped region. The first doped region and the second doped region are disposed in the substrate on the respective sides of the first gate. The second cell includes a second gate, a second charge storage structure, a third doped region, and the second doped region. The third doped region and the second doped region are disposed in the substrate on the respective sides of the second gate. The second cell and the first cell share the second doped region.

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