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1. 发明授权

US09431550B2 Trench polysilicon diode 有权
公开(公告)号：US09431550B2
公开(公告)日：2016-08-30
申请号：US13308375
申请日：2011-11-30
申请人： Qufei Chen , Robert Xu , Kyle Terrill , Deva Pattanayak
发明人： Qufei Chen , Robert Xu , Kyle Terrill , Deva Pattanayak
IPC分类号： H01L27/12 , H01L29/76 , H01L29/866 , H01L27/06 , H01L27/08 , H01L29/66 , H01L29/78 , H01L27/02
CPC分类号： H01L29/7813 , H01L27/0255 , H01L27/0629 , H01L27/0814 , H01L29/66727 , H01L29/66734 , H01L29/7808 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.

2. 发明授权

US07268032B2 Termination for trench MIS device having implanted drain-drift region 有权
标题翻译：具有植入漏极漂移区域的沟槽MIS器件的端接
公开(公告)号：US07268032B2
公开(公告)日：2007-09-11
申请号：US11232613
申请日：2005-09-21
申请人： Mohamed N. Darwish , Kyle W. Terrill , Jainhai Qi , Qufei Chen
发明人： Mohamed N. Darwish , Kyle W. Terrill , Jainhai Qi , Qufei Chen
IPC分类号： H01L21/8238
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/7811
摘要： A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench. The polysilicon material in each termination trenches.
摘要翻译：沟槽MIS器件形成在覆盖在N外延层和N +衬底上的P外延层中。在一个实施例中，器件包括从沟槽的底部延伸到N外延层的N型漏 - 漂移区。优选地，漏极漂移区域至少部分地通过在沟槽的侧壁上制造间隔物并且在侧壁间隔物之间并通过沟槽的底部注入N型掺杂剂而形成。漏极漂移区可以比在N外延层中形成的常规“漂移区”更重的掺杂。因此，器件具有低导通电阻。该器件可以由位于管芯边缘附近的多个多晶硅填充的端接沟槽端接，每个端接沟槽中的多晶硅与邻近端接沟槽的台面连接。每个终端沟槽中的多晶硅材料。

3. 发明申请

US20110089486A1 SUPER-HIGH DENSITY TRENCH MOSFET 有权
标题翻译：超高密度TRENCH MOSFET
公开(公告)号：US20110089486A1
公开(公告)日：2011-04-21
申请号：US12788158
申请日：2010-05-26
申请人： Robert Q. Xu , Kuo-In Chen , Karl Lichtenberger , Sharon Shi , Qufei Chen , Kyle Terrill
发明人： Robert Q. Xu , Kuo-In Chen , Karl Lichtenberger , Sharon Shi , Qufei Chen , Kyle Terrill
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0638 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L29/7811
摘要： A method, in one embodiment, can include forming a plurality of trenches in a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET). In addition, the method can include angle implanting source regions into the body region. Furthermore, dielectric material can be grown within the plurality of trenches. Gate polysilicon can be deposited within the plurality of trenches. Moreover, the method can include chemical mechanical polishing the gate polysilicon. The method can also include etching back the gate polysilicon within the plurality of trenches.
摘要翻译：在一个实施例中，一种方法可以包括在垂直金属氧化物半导体场效应晶体管（MOSFET）的主体区域中形成多个沟槽。此外，该方法可以包括将角度注入源区域进入体区域。此外，电介质材料可以在多个沟槽内生长。栅极多晶硅可以沉积在多个沟槽内。此外，该方法可以包括化学机械抛光栅极多晶硅。该方法还可以包括蚀刻多个沟槽内的栅极多晶硅。

4. 发明授权

US07544545B2 Trench polysilicon diode 有权
标题翻译：沟槽多晶硅二极管
公开(公告)号：US07544545B2
公开(公告)日：2009-06-09
申请号：US11322040
申请日：2005-12-28
申请人： Qufei Chen , Robert Xu , Kyle Terrill , Deva Pattanayak
发明人： Qufei Chen , Robert Xu , Kyle Terrill , Deva Pattanayak
IPC分类号： H01L21/20
CPC分类号： H01L29/7813 , H01L27/0255 , H01L27/0629 , H01L27/0814 , H01L29/66727 , H01L29/66734 , H01L29/7808 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention include a method of manufacturing a trench polysilicon diode. The method includes forming a N−(P−) type epitaxial region on a N+(P+) type substrate and forming a trench in the N−(P−) type epitaxial region. The method further includes forming a insulating layer in the trench and filling the trench with polysilicon forming a top surface of the trench. The method further includes forming P+(N+) type doped polysilicon region and N+(P+) type doped polysilicon region in the trench and forming a diode in the trench wherein a portion of the diode is lower than the top surface of the trench.
摘要翻译：本发明的实施例包括制造沟槽多晶硅二极管的方法。该方法包括在N +（P +）型衬底上形成N-（P-）型外延区，并在N-（P-）型外延区中形成沟槽。该方法还包括在沟槽中形成绝缘层，并用形成沟槽顶表面的多晶硅填充沟槽。该方法还包括在沟槽中形成P +（N +）型掺杂多晶硅区域和N +（P +）型掺杂多晶硅区域，并在沟槽中形成二极管，其中二极管的一部分低于沟槽的顶表面。

5. 发明申请

US20080157281A1 Ultra-low drain-source resistance power MOSFET 有权
标题翻译：超低漏源电阻功率MOSFET
公开(公告)号：US20080157281A1
公开(公告)日：2008-07-03
申请号：US12069712
申请日：2008-02-11
申请人： The-Tu Chau , Sharon Shi , Qufei Chen , Martin Hernandez , Deva Pattanayak , Kyle Terrill , Kuo-In Chen
发明人： The-Tu Chau , Sharon Shi , Qufei Chen , Martin Hernandez , Deva Pattanayak , Kyle Terrill , Kuo-In Chen
IPC分类号： H01L29/36
CPC分类号： H01L29/0878 , H01L29/167 , H01L29/7813
摘要： Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorus. The novel red Phosphorus doped substrate enables a desirable low drain-source resistance.
摘要翻译：超低漏源电阻功率MOSFET。根据本发明的实施例，半导体器件包括多个沟槽功率MOSFET。多个沟槽功率MOSFET形成在第二外延层中。第二外延层形成为与第一外延层相邻并邻接。第一外延层与高度掺杂有红磷的衬底相邻并邻接地形成。新颖的红色磷掺杂衬底能够实现所需的低漏源电阻。

6. 发明授权

US07045857B2 Termination for trench MIS device having implanted drain-drift region 有权
公开(公告)号：US07045857B2
公开(公告)日：2006-05-16
申请号：US10810031
申请日：2004-03-26
申请人： Mohamed N. Darwish , Kyle W. Terrill , Jainhai Qi , Qufei Chen
发明人： Mohamed N. Darwish , Kyle W. Terrill , Jainhai Qi , Qufei Chen
IPC分类号： H01L29/76 , H01L29/00
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/7811
摘要： A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench. The polysilicon material in each termination trenches.

7. 发明申请

US20060011976A1 Termination for trench MIS device having implanted drain-drift region 有权
公开(公告)号：US20060011976A1
公开(公告)日：2006-01-19
申请号：US11233145
申请日：2005-09-21
申请人： Mohamed Darwish , Kyle Terrill , Jainhai Qi , Qufei Chen
发明人： Mohamed Darwish , Kyle Terrill , Jainhai Qi , Qufei Chen
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/7811
摘要： A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench. The polysilicon material in each termination trenches.

8. 发明授权

US09887266B2 Ultra-low drain-source resistance power MOSFET 有权
公开(公告)号：US09887266B2
公开(公告)日：2018-02-06
申请号：US12069712
申请日：2008-02-11
申请人： The-Tu Chau , Sharon Shi , Qufei Chen , Martin Hernandez , Deva Pattanayak , Kyle Terrill , Kuo-In Chen
发明人： The-Tu Chau , Sharon Shi , Qufei Chen , Martin Hernandez , Deva Pattanayak , Kyle Terrill , Kuo-In Chen
IPC分类号： H01L29/08 , H01L29/167 , H01L29/78
CPC分类号： H01L29/0878 , H01L29/167 , H01L29/7813
摘要： Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorus. The novel red Phosphorus doped substrate enables a desirable low drain-source resistance.

9. 发明申请

US20140077287A1 BREAKDOWN VOLTAGE BLOCKING DEVICE 有权
标题翻译：断开电压闭锁装置
公开(公告)号：US20140077287A1
公开(公告)日：2014-03-20
申请号：US13622997
申请日：2012-09-19
申请人： Robert Q. Xu , Qufei Chen
发明人： Robert Q. Xu , Qufei Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/66356 , H01L29/407 , H01L29/4236 , H01L29/66143 , H01L29/66643 , H01L29/66666 , H01L29/7391 , H01L29/7828 , H01L29/7839 , H01L29/8613 , H01L29/8725
摘要： In one embodiment, a breakdown voltage blocking device can include an epitaxial region located above a substrate and a plurality of source trenches formed in the epitaxial region. Each source trench can include a dielectric layer surrounding a conductive region. The breakdown voltage blocking device can also include a contact region located in an upper surface of the epitaxial region along with a gate trench formed in the epitaxial region. The gate trench can include a dielectric layer that lines the sidewalls and bottom of the gate trench and a conductive region located between the dielectric layer. The breakdown voltage blocking device can include source metal located above the plurality of source trenches and the contact region. The breakdown voltage blocking device can include gate metal located above the gate trench.
摘要翻译：在一个实施例中，击穿电压阻挡装置可以包括位于衬底上方的外延区域和形成在外延区域中的多个源极沟槽。每个源沟槽可以包括围绕导电区域的介电层。击穿电压阻挡装置还可以包括位于外延区域的上表面中的接触区域以及形成在外延区域中的栅极沟槽。栅极沟槽可以包括在栅极沟槽的侧壁和底部以及位于介电层之间的导电区域的电介质层。击穿电压阻挡装置可以包括位于多个源极沟槽和接触区域上方的源极金属。击穿电压阻挡装置可以包括位于栅极沟槽上方的栅极金属。

10. 发明申请

US20120220092A1 METHOD OF FORMING A HYBRID SPLIT GATE SIMICONDUCTOR 审中-公开
标题翻译：形成混合隔离栅智能体的方法
公开(公告)号：US20120220092A1
公开(公告)日：2012-08-30
申请号：US13460600
申请日：2012-04-30
申请人： Madhur Bobde , Qufei Chen , Misbah Ul Azam , Kyle Terrill , Yang Gao , Sharon Shi
发明人： Madhur Bobde , Qufei Chen , Misbah Ul Azam , Kyle Terrill , Yang Gao , Sharon Shi
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/66727 , H01L29/66734
摘要： Method of forming a Hybrid Split Gate Semiconductor. In accordance with a method embodiment of the present invention, a plurality of first trenches is formed in a semiconductor substrate to a first depth. A plurality of second trenches is formed in the semiconductor substrate to a second depth. The first plurality of trenches are parallel with the second plurality of trenches. The trenches of the plurality of first trenches alternate with and are adjacent to trenches of the plurality of second trenches.
摘要翻译：形成混合分离栅极半导体的方法。根据本发明的方法实施例，在半导体衬底中形成多个第一沟槽至第一深度。多个第二沟槽在半导体衬底中形成第二深度。第一多个沟槽与第二多个沟槽平行。多个第一沟槽的沟槽与多个第二沟槽的沟槽交替并与之相邻。

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