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1. 发明授权

US08484448B2 Information processing device 有权
标题翻译：信息处理装置
公开(公告)号：US08484448B2
公开(公告)日：2013-07-09
申请号：US13399023
申请日：2012-02-17
申请人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
发明人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
IPC分类号： G06F9/00 , G06F15/177
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： Information processing system including a first and a second operation mode with operating current lower than the first, a register holding an address of an instruction executed by a processing unit first when a boot address register returns from second to first operation mode, wherein the address is output to the processing unit when second to first operation mode shifting, wherein the boot address register is rewritable, an information holding circuit holding a value of a peripheral circuit module register, wherein the information holding circuit holds, in the second operation mode, information about the peripheral circuit module register, and, transfers information held in the information holding circuit to the peripheral circuit module register regarding a second-to-first operation mode shift, and wherein when an interrupt request is posted from outside the system in the second operation mode, the information processing system performs interrupt processing corresponding to the interrupt request.
摘要翻译：信息处理系统，包括具有低于第一操作电流的第一操作模式和第二操作模式，当引导地址寄存器从第二操作模式返回到第一操作模式时，首先保存由处理单元执行的指令的地址的寄存器，其中该地址为当第二至第一操作模式转换时，输出到处理单元，其中引导地址寄存器是可重写的，信息保持电路保持外围电路模块寄存器的值，其中信息保持电路在第二操作模式中保持关于外围电路模块寄存器，并且将关于第二至第一操作模式移位的信息保持电路中保存的信息传送到外围电路模块寄存器，并且其中当在第二操作模式中从系统外部发布中断请求时信息处理系统执行与内部相对应的中断处理破产请求

2. 发明申请

US20120151197A1 INFORMATION PROCESSING DEVICE 有权
标题翻译：信息处理设备
公开(公告)号：US20120151197A1
公开(公告)日：2012-06-14
申请号：US13399023
申请日：2012-02-17
申请人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
发明人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
IPC分类号： G06F9/00
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： Information processing system including a first and a second operation mode with operating current lower than the first, a register holding an address of an instruction executed by a processing unit first when a boot address register returns from second to first operation mode, wherein the address is output to the processing unit when second to first operation mode shifting, wherein the boot address register is rewritable, an information holding circuit holding a value of a peripheral circuit module register, wherein the information holding circuit holds, in the second operation mode, information about the peripheral circuit module register, and, transfers information held in the information holding circuit to the peripheral circuit module register regarding a second-to-first operation mode shift, and wherein when an interrupt request is posted from outside the system in the second operation mode, the information processing system performs interrupt processing corresponding to the interrupt request.
摘要翻译：信息处理系统，包括具有低于第一操作电流的第一操作模式和第二操作模式，当引导地址寄存器从第二操作模式返回到第一操作模式时，首先保存由处理单元执行的指令的地址的寄存器，其中该地址为当第二至第一操作模式转换时，输出到处理单元，其中引导地址寄存器是可重写的，信息保持电路保持外围电路模块寄存器的值，其中信息保持电路在第二操作模式中保持关于外围电路模块寄存器，并且将关于第二至第一操作模式移位的信息保持电路中保存的信息传送到外围电路模块寄存器，并且其中当在第二操作模式中从系统外部发布中断请求时信息处理系统执行与内部相对应的中断处理破产请求

3. 发明授权

US07853776B2 Handover between software and hardware accelerator 有权
标题翻译：软件和硬件加速器之间切换
公开(公告)号：US07853776B2
公开(公告)日：2010-12-14
申请号：US11260423
申请日：2005-10-28
申请人： Tetsuya Yamada , Naohiko Irie
发明人： Tetsuya Yamada , Naohiko Irie
IPC分类号： G06F9/30
CPC分类号： G06F9/30174
摘要： A bytecode accelerator which translates stack-based intermediate language (bytecodes) into register-based CPU instructions transfers plural pieces of internal information from a register file of a CPU to the bytecode accelerator by means of an internal transfer bus between the bytecode accelerator and the CPU and an input selection logic of the bytecode accelerator when the bytecode accelerator is started and transfers plural pieces of internal information in the bytecode accelerator to the register file of the CPU by means of the internal transfer bus, an output selector and an output selector selection logic of the bytecode accelerator when the bytecode accelerator ends its operation in transition between hardware processing and software processing by software virtual machine.
摘要翻译：将基于堆栈的中间语言（字节码）转换为基于寄存器的CPU指令的字节码加速器通过字节码加速器和CPU之间的内部传输总线将多条内部信息从CPU的寄存器文件传送到字节码加速器以及当字节代码加速器启动时字节码加速器的输入选择逻辑，并且通过内部传送总线，输出选择器和输出选择器选择逻辑，将字节码加速器中的多条内部信息传送到CPU的寄存器文件字节码加速器在硬件处理和软件虚拟机的软件处理之间的转换中结束其操作。

4. 发明授权

US07788469B2 Information processing device having arrangements to inhibit coprocessor upon encountering data that the coprocessor cannot handle 失效
标题翻译：信息处理装置具有在遇到协处理器不能处理的数据时禁止协处理器的装置
公开(公告)号：US07788469B2
公开(公告)日：2010-08-31
申请号：US10883758
申请日：2004-07-06
申请人： Tetsuya Yamada , Naohiko Irie , Takahiro Irita , Masayuki Kabasawa
发明人： Tetsuya Yamada , Naohiko Irie , Takahiro Irita , Masayuki Kabasawa
IPC分类号： G06F15/76
CPC分类号： G06F9/30174 , G06F9/30014 , G06F9/3861 , G06F9/3877 , G06F9/3879
摘要： A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when corresponding data is detected in a data checking part.
摘要翻译：硬件加速器用于在信息处理设备中执行浮点字节码。对于浮点字节码，字节码加速器BCA将用于使用FPU的指令流馈送到CPU。当使用FPU时，首先将数据从通用寄存器传送到FPU寄存器，然后执行FPU操作。对于不能由FPU处理的数据，如非规范化数字，为了调用软件的浮点数学库，BCA的处理完成，并且处理转移到软件处理。为了实现这一点，由硬件加速器窥探从CPU到FPU的数据传输总线上的数据，并且当在数据检查中检测到对应的数据时，向CPU发送取消请求以禁止执行FPU操作部分。

5. 发明授权

US07612391B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07612391B2
公开(公告)日：2009-11-03
申请号：US12236170
申请日：2008-09-23
申请人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
发明人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
IPC分类号： H01L23/50
CPC分类号： G01R31/318572 , G11C5/063 , G11C11/417 , H01L27/0207 , H01L27/092 , H01L27/11807 , H01L2924/0002 , H03K3/356008 , H03K3/35625 , H03K19/0016 , H01L2924/00
摘要： In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefore for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.
摘要翻译：在功率关闭时保留先前数据的低功耗模式下，其返回速度增加。虽然可以考虑使用现有的数据保持触发器，但是这不是优选的，因为它增加了诸如扩大单元大小的面积开销。用于电源关闭的数据保持的电源线由比通常的主电源线更细的布线形成。优选地，用于数据保持电路的电力线被认为是信号线，并通过自动放置和安装进行布线。为此，预先通过以与现有信号线相同的方式为单元提供端子来设计用于数据保持的电力线的端子。电池线的附加布局不再需要，这使得现有的放置和布线工具能够减少面积和设计。

6. 发明授权

US07217963B2 Semiconductor integrated circuit device 有权
公开(公告)号：US07217963B2
公开(公告)日：2007-05-15
申请号：US11320751
申请日：2005-12-30
申请人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
发明人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
IPC分类号： H01L29/73
CPC分类号： G01R31/318572 , G11C5/063 , G11C11/417 , H01L27/0207 , H01L27/092 , H01L27/11807 , H01L2924/0002 , H03K3/356008 , H03K3/35625 , H03K19/0016 , H01L2924/00
摘要： In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

7. 发明申请

US20060085582A1 Multiprocessor system 审中-公开
标题翻译：多处理器系统
公开(公告)号：US20060085582A1
公开(公告)日：2006-04-20
申请号：US11203284
申请日：2005-08-15
申请人： Hiroaki Shikano , Naohiko Irie
发明人： Hiroaki Shikano , Naohiko Irie
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： An interrupt notification network is provided for a multiprocessor system in which many processor units are installed. An interrupt notification source processor unit transmits an interrupt notification packet to an interrupt notification destination processor unit. The interrupt notification packet to be transmitted by the interrupt notification source processor unit contains an interrupt destination process ID. A control section for the interrupt notification network analyzes the transmitted interrupt notification packet, references a table that defines the correspondence between internally retained IDs of processes and processor units that perform the processes, determines the interrupt notification destination processor unit, and transmits the interrupt notification packet to the processor unit. Consequently, the multiprocessor system in which many processor units are installed is capable of performing an inter-processor unit multiplex coordination process for inter-processor unit process synchronization and process control, increasing the system throughput, and providing increased real-time capability.
摘要翻译：为其中安装许多处理器单元的多处理器系统提供中断通知网络。中断通知源处理器单元向中断通知目的地处理器单元发送中断通知分组。要由中断通知源处理器单元发送的中断通知包含有中断目的地处理ID。用于中断通知网络的控制部分分析发送的中断通知分组，引用定义进程的内部保留ID和处理器单元之间的对应关系的表，确定中断通知目的地处理器单元，并发送中断通知分组到处理器单元。因此，其中安装有许多处理器单元的多处理器系统能够执行用于处理器间单元处理同步和过程控制的处理器间单元复用协调处理，增加系统吞吐量并提供增加的实时能力。

8. 发明授权

US07023757B2 Semiconductor device 有权
公开(公告)号：US07023757B2
公开(公告)日：2006-04-04
申请号：US10373042
申请日：2003-02-26
申请人： Takao Watanabe , Kunio Uchiyama , Osamu Nishii , Naohiko Irie , Hiroyuki Mizuno
发明人： Takao Watanabe , Kunio Uchiyama , Osamu Nishii , Naohiko Irie , Hiroyuki Mizuno
IPC分类号： G11C8/00 , G06F1/26
CPC分类号： G06F1/3203 , G06F1/3287 , G11C5/147 , G11C11/417 , Y02D10/171
摘要： When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

9. 发明授权

US06772325B1 Processor architecture and operation for exploiting improved branch control instruction 失效
标题翻译：处理器架构和操作，用于利用改进的分支控制指令
公开(公告)号：US06772325B1
公开(公告)日：2004-08-03
申请号：US09410682
申请日：1999-10-01
申请人： Naohiko Irie , Tony Lee Werner
发明人： Naohiko Irie , Tony Lee Werner
IPC分类号： G06F938
CPC分类号： G06F9/3885 , G06F9/30058 , G06F9/322 , G06F9/3806 , G06F9/3842 , G06F9/3846
摘要： A processor is disclosed utilizing improved branch control and branch instructions for optimizing performance of programs run on such processors. Flexible instruction parameter fields permit a variety of new branch control and branch instruction implementations best suited for a particular computing environment. These instructions also have separate prediction bits, which are used to optize loading of target instruction buffers in advance of program execution, so that a pipeline within the processor achieves superior performance during actual program execution.
摘要翻译：公开了利用改进的分支控制和分支指令来优化在这种处理器上运行的程序的性能的处理器。灵活的指令参数字段允许最适合特定计算环境的各种新的分支控制和分支指令实现。这些指令还具有单独的预测位，其用于在程序执行之前优化加载目标指令缓冲器，使得处理器内的流水线在实际程序执行期间实现优异的性能。

10. 发明授权

US06449712B1 Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions 失效
标题翻译：用较大的固定长度指令的序列来模拟执行较小的固定长度分支/延迟时隙指令
公开(公告)号：US06449712B1
公开(公告)日：2002-09-10
申请号：US09410851
申请日：1999-10-01
申请人： Naohiko Irie , Tony Lee Werner , Chih-Jui Peng , Sebastian H. Ziesler , Jackie A. Freeman , Sivaram Krishnan
发明人： Naohiko Irie , Tony Lee Werner , Chih-Jui Peng , Sebastian H. Ziesler , Jackie A. Freeman , Sivaram Krishnan
IPC分类号： G06F9455
CPC分类号： G06F9/30174 , G06F9/30058 , G06F9/3842
摘要： A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible for executing a 16-bit fixed length instruction set architecture by translating each of the 16-bit instructions into a sequence of one or more 32-bit instructions. The 32-bit instruction set architecture includes “prepare to branch” instructions that allow target addresses for branch instructions to be set up in advance of the branch. The 32-bit prepare to branch and branch instructions are combined to execute a 16-bit branch instruction coupled with a 16-bit Delay Slot instruction.
摘要翻译：构造为执行32位固定长度指令集体系结构的处理器元件向后兼容，用于通过将16位指令中的每一个转换为一个或多个32位的序列来执行16位固定长度指令集架构说明。 32位指令集架构包括“准备分支”指令，允许在分支之前设置分支指令的目标地址。组合32位准备到分支和分支指令以执行与16位延迟时隙指令相结合的16位分支指令。

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