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1. 发明授权

US07903013B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07903013B2
公开(公告)日：2011-03-08
申请号：US12507660
申请日：2009-07-22
申请人： Kenichiro Yamaguchi , Atsushi Okumura , Mitsugu Kusunoki , Tomoo Murata
发明人： Kenichiro Yamaguchi , Atsushi Okumura , Mitsugu Kusunoki , Tomoo Murata
IPC分类号： H03M1/66
CPC分类号： H03M1/0643 , H01L27/0203 , H03M1/687 , H03M1/745 , H03M1/785 , Y10T307/696
摘要： Operating speed as well as output accuracy of a D-A converter is enhanced. With a semiconductor device including unit current sources, and unit current source switches, plural current source elements constituting each of the unit current sources are disposed so as to be evenly dispersed, thereby reducing errors of the current source element, dependent on distance while the unit current source switches are concentratedly disposed in a small region, thereby mitigating delay in operation, attributable to parasitic capacitance. In addition, with the semiconductor device including R2R resistance ladders, the R2R resistance ladder is provided on the positive and the negative of each of the unit current source switches, and the respective R2R resistance ladders are shorted with each other at respective nodes on a unit current source switch-by-unit current source switch basis, are rendered identical in length, thereby cancelling out a nonlinearity error attributable to wiring parasitic resistance.
摘要翻译：提高了D-A转换器的工作速度和输出精度。利用包括单位电流源和单位电流源开关的半导体器件，构成每个单位电流源的多个电流源元件被布置成均匀分散，从而根据距离减小电流源元件的误差，而单元电流源开关集中地设置在较小的区域中，从而减轻了由寄生电容引起的工作延迟。另外，对于包含R2R电阻梯的半导体装置，在每个单位电流源开关的正极和负极上设置R2R电阻梯，并且相应的R2R电阻梯在单元的相应节点处相互短路电流源逐个电流源开关基础的长度相同，从而消除归因于布线寄生电阻的非线性误差。

2. 发明申请

US20060245266A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060245266A1
公开(公告)日：2006-11-02
申请号：US11409963
申请日：2006-04-25
申请人： Ryusuke Sahara , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
发明人： Ryusuke Sahara , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
IPC分类号： G11C7/10
CPC分类号： H03M1/1061 , H03M1/687 , H03M1/785 , H03M1/808
摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.
摘要翻译：具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入第二存储器部分。因此，可以提高D / A转换器的性能。

3. 发明申请

US20060244103A1 Semiconductor apparatus 失效
公开(公告)号：US20060244103A1
公开(公告)日：2006-11-02
申请号：US11411096
申请日：2006-04-26
申请人： Koji Ishikawa , Kazutaka Mori , Hiroshige Kogayu , Tamotsu Miyake , Mitsugu Kusunoki
发明人： Koji Ishikawa , Kazutaka Mori , Hiroshige Kogayu , Tamotsu Miyake , Mitsugu Kusunoki
IPC分类号： H01L27/082
CPC分类号： H01L23/5252 , H01L27/0823 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor apparatus includes a first transistor having a first emitter electrode, a first base electrode, and a first collector electrode in a region over a first region. Base lead-out polysilicon connecting the first base electrode and a first base region passes over a second region provided out of the first region and a resistor element is added. A writing voltage is reduced in an antifuse using two bipolar transistors.

4. 发明申请

US20120048028A1 APPARATUS FOR MEASURING A MECHANICAL QUANTITY 有权
标题翻译：用于测量机械数量的装置
公开(公告)号：US20120048028A1
公开(公告)日：2012-03-01
申请号：US13180603
申请日：2011-07-12
申请人： Kentaro MIYAJIMA , Mitsugu KUSUNOKI
发明人： Kentaro MIYAJIMA , Mitsugu KUSUNOKI
IPC分类号： G01L1/22
CPC分类号： G01L1/2281 , G01L1/2293
摘要： Because of stress occurring due to a change in temperature, and presence of heat distribution on a semiconductor substrate, and a dopant dosage gradient, an offset output occurs to a Wheatstone bridge circuit intended for detection of strain, posing a problem. To solve the problem, diffusion resistors are disposed in the form of a matrix, and bridge resistors Rv1, Rv2 each are formed by selectively connecting diffusion resistors disposed in each odd column, in series with each other, while Rh1, Rh2 each are formed by selectively connecting diffusion resistors disposed in each even column, in series with each other.
摘要翻译：由于温度变化引起的应力和半导体衬底上的热分布的存在以及掺杂剂剂量梯度，偏移输出发生在用于检测应变的惠斯通电桥电路中，造成问题。为了解决这个问题，扩散电阻器以矩阵的形式设置，桥式电阻器Rv1，Rv2分别通过选择性地连接设置在每个奇数列中的扩散电阻器彼此串联而形成，而Rh1，Rh2分别由选择性地连接设置在每个偶数列中的扩散电阻器彼此串联。

5. 发明授权

US07403408B2 Semiconductor memory device and semiconductor device 失效
标题翻译：半导体存储器件和半导体器件
公开(公告)号：US07403408B2
公开(公告)日：2008-07-22
申请号：US11134389
申请日：2005-05-23
申请人： Hiroshi Otori , Masatoshi Hasegawa , Mitsugu Kusunoki , Masatoshi Sakamoto
发明人： Hiroshi Otori , Masatoshi Hasegawa , Mitsugu Kusunoki , Masatoshi Sakamoto
IPC分类号： G11C5/02
CPC分类号： G11C5/06 , G11C8/12 , G11C11/4087
摘要： A semiconductor memory device that satisfies needs of both a large number of memory banks and a higher operation speed is provided. A semiconductor memory device includes a plurality of data terminal pads, and a plurality of memory banks independently subject to memory access. Each of the memory banks is divided into a plurality of submemory banks. The data terminal pads are also divided into a plurality of groups so as to be associated with submemory banks obtained by the division. Blocks each including submemory banks obtained by the division and data terminal pads associated with the submemory banks are arranged so as not to overlap each other on a semiconductor chip.
摘要翻译：提供一种满足大量存储体的需要和更高运算速度的半导体存储器件。半导体存储器件包括多个数据端子焊盘，以及独立地进行存储器访问的多个存储体。每个存储体被分成多个子存储体。数据终端焊盘也被分成多个组，以便与通过划分获得的子存储库相关联。通过划分获得的包括子存储体的块和与子存储体相关联的数据终端焊盘的块被布置为在半导体芯片上不彼此重叠。

6. 发明申请

US20080055140A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080055140A1
公开(公告)日：2008-03-06
申请号：US11877561
申请日：2007-10-23
申请人： Ryusuke SAHARA , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
发明人： Ryusuke SAHARA , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
IPC分类号： H03M1/66
CPC分类号： H03M1/1061 , H03M1/687 , H03M1/785 , H03M1/808
摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.
摘要翻译：具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入第二存储器部分。因此，可以提高D / A转换器的性能。

7. 发明授权

US07310266B2 Semiconductor device having memory cells implemented with bipolar-transistor-antifuses operating in a first and second mode 有权
标题翻译：具有以第一和第二模式工作的双极晶体管 - 反熔丝实现的存储单元的半导体器件
公开(公告)号：US07310266B2
公开(公告)日：2007-12-18
申请号：US11409963
申请日：2006-04-25
申请人： Ryusuke Sahara , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
发明人： Ryusuke Sahara , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
IPC分类号： G11C11/40 , H03M1/66
CPC分类号： H03M1/1061 , H03M1/687 , H03M1/785 , H03M1/808
摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions.
摘要翻译：具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结点是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入第二存储器部分。

8. 发明申请

US20050259500A1 Semiconductor memory device and semiconductor device 失效
标题翻译：半导体存储器件和半导体器件
公开(公告)号：US20050259500A1
公开(公告)日：2005-11-24
申请号：US11134389
申请日：2005-05-23
申请人： Hiroshi Otori , Masatoshi Hasegawa , Mitsugu Kusunoki , Masatoshi Sakamoto
发明人： Hiroshi Otori , Masatoshi Hasegawa , Mitsugu Kusunoki , Masatoshi Sakamoto
IPC分类号： H01L21/8242 , G11C5/06 , G11C8/00 , G11C8/12 , G11C11/401 , G11C11/408 , H01L27/108
CPC分类号： G11C5/06 , G11C8/12 , G11C11/4087
摘要： A semiconductor memory device that satisfies needs of both a large number of memory banks and a higher operation speed is provided. A semiconductor memory device includes a plurality of data terminal pads, and a plurality of memory banks independently subject to memory access. Each of the memory banks is divided into a plurality of submemory banks. The data terminal pads are also divided into a plurality of groups so as to be associated with submemory banks obtained by the division. Blocks each including submemory banks obtained by the division and data terminal pads associated with the submemory banks are arranged so as not to overlap each other on a semiconductor chip.
摘要翻译：提供一种满足大量存储体的需要和更高运算速度的半导体存储器件。半导体存储器件包括多个数据端子焊盘，以及独立地进行存储器访问的多个存储体。每个存储体被分成多个子存储体。数据终端焊盘也被分成多个组，以便与通过划分获得的子存储库相关联。通过划分获得的包括子存储体的块和与子存储体相关联的数据终端焊盘的块被布置为在半导体芯片上不彼此重叠。

9. 发明授权

US06828842B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06828842B2
公开(公告)日：2004-12-07
申请号：US10443035
申请日：2003-05-22
申请人： Kayoko Saito , Mitsugu Kusunoki , Hiroyasu Ishizuka , Shinichiro Masuda
发明人： Kayoko Saito , Mitsugu Kusunoki , Hiroyasu Ishizuka , Shinichiro Masuda
IPC分类号： H03K508
CPC分类号： H03K5/08 , G11C5/14 , G11C11/417 , H01L27/0266 , H01L27/105 , H01L27/11 , H01L27/1116 , H03K19/00315
摘要： A first clamp circuit and a second clamp circuit stacked thereon in vertical respectively for clamping unwanted level voltages are provided between the high potential side power source and low potential side power source and an intermediate node formed by vertical stacking of the first clamp circuit and second clamp circuit is coupled with the power source for internal circuit. Since a capacitor originally provided in the internal circuit is allocated in parallel to the first clamp circuit, impedance is reduced due to existence of the capacitor and potential difference due to over-current flowing in the chip is reduced. Accordingly, potential difference due to over-current flowing into the chip may be reduced and static electricity dielectric strength can be improved by allowing higher over-current. Thereby, impedance when the clamp circuits are stacked in two stages.
摘要翻译：在高电位侧电源和低电位侧电源之间设置有分别垂直于其上堆叠的第一钳位电路和第二钳位电路，用于夹紧不期望的电平电压，并且在第一钳位电路和第二钳位电路与内部电路的电源耦合。由于最初设置在内部电路中的电容器与第一钳位电路并联地分配，所以由于电容器的存在而导致的阻抗减小，并且由于芯片中的过电流流动导致的电位差减小。因此，由于过电流流入芯片的电位差可能降低，并且通过允许更高的过电流可以提高静电绝缘强度。因此，钳位电路以两级堆叠的阻抗。

10. 发明授权

US5825203A Variable logic integrated circuit device having connections through switch matrix and top layers for inter-cell connections 失效
标题翻译：可变逻辑集成电路器件具有通过开关矩阵和顶层连接的单元间连接的连接
公开(公告)号：US5825203A
公开(公告)日：1998-10-20
申请号：US747339
申请日：1996-11-12
申请人： Mitsugu Kusunoki , Nobuo Tamba
发明人： Mitsugu Kusunoki , Nobuo Tamba
IPC分类号： H01L21/82 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17792
摘要： A variable logic integrated circuit device formed on a semiconductor chip comprising variable logic blocks and switch matrices laid out alternately in the X and Y directions in a checkerboard pattern. Above the variable logic blocks is a block interconnection wiring arrangement formed by multiple-layer wiring techniques. The variable logic blocks and switch matrices are wired into circuits respectively by a lower wiring layer in the multiple wiring layer setup of the chip. The block interconnection wiring is formed by an upper wiring layer extending above the variable logic blocks and included in the multiple wiring layer setup. The switch matrices are used to connect the block interconnection lines to one another as well as to the variable logic blocks.
摘要翻译：形成在半导体芯片上的可变逻辑集成电路器件，其包括以棋盘图案在X和Y方向交替布置的可变逻辑块和开关矩阵。可变逻辑块之上是通过多层布线技术形成的块互连布线布置。可变逻辑块和开关矩阵分别通过芯片的多个布线层设置中的下布线层布线到电路中。块互连布线由在可变逻辑块之上延伸并包括在多个布线层设置中的上布线层形成。开关矩阵用于将块互连线彼此连接到可变逻辑块。

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