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1. 发明申请

US20110106287A1 Wiring forming system and wiring forming method for forming wiring on wiring board 审中-公开
标题翻译：用于在布线板上形成布线的布线形成系统和布线形成方法
公开(公告)号：US20110106287A1
公开(公告)日：2011-05-05
申请号：US12929169
申请日：2011-01-05
申请人： Masatoshi Akagawa , Kazunari Sekigawa , Shinichi Kabayashi
发明人： Masatoshi Akagawa , Kazunari Sekigawa , Shinichi Kabayashi
IPC分类号： G06F19/00
CPC分类号： H05K1/0269 , H01L2924/0002 , H05K3/0005 , H05K3/0082 , H05K3/064 , H05K3/125 , H05K2203/013 , H05K2203/107 , H05K2203/162 , H01L2924/00
摘要： A wiring forming system comprises: maskless exposure unit which directly exposes an unexposed board by using exposure data generated based on design data relating to an wiring board; post-development inspect unit which tests the board after development, by using the exposure data and the image data of the board exposed and developed by the maskless exposure unit; etching unit which etches the developed board; and post-etching inspect unit which tests an etching pattern formed on the etched board, by using etching inspect data generated based on the design data and the image data of the board etched by the etching unit.
摘要翻译：布线形成系统包括：无掩模曝光单元，其通过使用基于与布线板相关的设计数据生成的曝光数据来直接曝光未曝光的印刷电路板; 开发后检查单元，通过使用曝光数据和由无掩模曝光单元曝光和显影的板的图像数据进行开发后测试板; 蚀刻单元，蚀刻开发板; 以及蚀刻后检查单元，其通过使用基于设计数据生成的蚀刻检查数据和由蚀刻单元蚀刻的板的图像数据来测试形成在蚀刻板上的蚀刻图案。

2. 发明申请

US20080123070A1 Patterning method and computer readable medium therefor 失效
标题翻译：图案化方法及其计算机可读介质
公开(公告)号：US20080123070A1
公开(公告)日：2008-05-29
申请号：US11812450
申请日：2007-06-19
申请人： Keiji Yoshizawa , Toshinori Koyama , Masatoshi Akagawa
发明人： Keiji Yoshizawa , Toshinori Koyama , Masatoshi Akagawa
IPC分类号： G03B27/42
CPC分类号： G03B27/58 , G03F7/70291 , G03F7/70358
摘要： In a patterning apparatus for forming a desired pattern on a surface of an object by exposing the surface of the object to light by using a plurality of spatial light modulation elements assigned to respective exposure areas defined along a relative moving direction of the object, predetermined areas which are on the surface of the object and are to be positioned in the vicinity of borders of the respective exposure areas exposed to light by the spatial light modulation elements are exposed to light by the spatial light modulation elements corresponding to the exposure areas, after the object is shifted in a direction perpendicular to the relative moving direction, such that the predetermined areas are positioned in the vicinity of the center parts of the exposure areas.
摘要翻译：在通过使用分配给沿着物体的相对移动方向限定的各个曝光区域的多个空间光调制元件将物体表面曝光的对象的表面上形成期望图案的图案形成装置中，预定区域在物体的表面上并且被定位在由空间光调制元件暴露于光的各个曝光区域的边界附近的位置，在与曝光区域相对应的空间光调制元件之后被曝光物体沿垂直于相对移动方向的方向移动，使得预定区域位于曝光区域的中心部分附近。

3. 发明授权

US07307691B2 Maskless direct exposure system and user interface 有权
标题翻译：无掩膜直接曝光系统和用户界面
公开(公告)号：US07307691B2
公开(公告)日：2007-12-11
申请号：US10974327
申请日：2004-10-27
申请人： Kazunari Sekigawa , Toshinori Koyama , Kazutaka Kobayashi , Masatoshi Akagawa
发明人： Kazunari Sekigawa , Toshinori Koyama , Kazutaka Kobayashi , Masatoshi Akagawa
IPC分类号： G03B27/46 , G03B27/42
CPC分类号： G03F7/70283 , G03F7/70291 , H05K3/0002 , H05K3/0005 , H05K3/0082
摘要： A direct exposure system comprises: a data mask that is a data object including drawing data; and a control mask that is a data object including at least one logical layer in which information about exposure conditions applied according to regions on a substrate is specified, and performs a direct exposure process using integrated data generated by combining the data mask with the control mask.
摘要翻译：直接曝光系统包括：作为包括绘图数据的数据对象的数据掩模; 以及作为包括至少一个逻辑层的控制掩模，所述至少一个逻辑层指定了根据基板上的区域应用的关于曝光条件的信息，并且使用通过将数据掩模与控制掩模组合而生成的积分数据进行直接曝光处理。

4. 发明授权

US06759268B2 Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06759268B2
公开(公告)日：2004-07-06
申请号：US10158155
申请日：2002-05-31
申请人： Masatoshi Akagawa
发明人： Masatoshi Akagawa
IPC分类号： H01L2144
CPC分类号： H01L25/0657 , H01L24/97 , H01L25/50 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/97 , H01L2225/06524 , H01L2225/06586 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/12042 , H01L2924/15311 , H01L2924/00014 , H01L2224/81 , H01L2924/00012 , H01L2224/83 , H01L2924/00
摘要： An object of the present invention is to make it possible to effect a reliable and compact configuration for a semiconductor device when mounting a plurality of semiconductor elements in a single package, and achieve higher integration and higher functionality more effectively. In a multi-layer wiring board 20 in which wiring patterns (conductor layers) 22, 24, and 26, and insulating layers 23, 25, and 27, are formed alternately in multiple layers on a base substrate, and electrically connections are made between the wiring patterns through via holes VH1 and VH2, semiconductor elements 30 are imbedded and mounted inside the insulating layers 23, 25, and 27, and the semiconductor elements 30 are deployed so that they are electrically connected to wiring patterns that are covered by the insulating layers, and so that they are stacked up in a direction perpendicular to the planar dimension of the multi-layer wiring board 20.
摘要翻译：本发明的一个目的是使得可以在将多个半导体元件安装在单个封装中时实现用于半导体器件的可靠且紧凑的配置，并且更有效地实现更高的集成度和更高的功能。在布线图案（导体层）22,24,26以及绝缘层23,25,27在基底基板上交替形成多层的多层布线基板20中，通过通孔VH1和VH2的布线图案，半导体元件30嵌入并安装在绝缘层23,25和27内，并且半导体元件30被展开，使得它们电连接到被绝缘层覆盖的布线图案并且使得它们在垂直于多层布线板20的平面尺寸的方向上堆叠。

5. 发明授权

US06717249B2 Non-contact type IC card and process for manufacturing-same 失效
标题翻译：非接触式IC卡及制造工艺相同
公开(公告)号：US06717249B2
公开(公告)日：2004-04-06
申请号：US10226608
申请日：2002-08-23
申请人： Masatoshi Akagawa
发明人： Masatoshi Akagawa
IPC分类号： H01L2302
CPC分类号： G06K19/0775 , G06K19/07749 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H05K3/4685 , Y10T29/49018 , Y10T29/4902 , Y10T29/4913
摘要： A non-contact type IC card includes an insulating film having first and second surfaces. A plane coil is arranged on the first surface of the film. A semiconductor element is arranged on the first surface of the film. The film has through holes which expose terminals of the plane coil and electrode terminals of the semiconductor element to the second surface of the film. A wiring pattern consisting of conductive paste is filled in the through holes and extends therebetween along the second surface of the film so that the terminals of the plane coil are electrically connected to the electrode terminals of the semiconductor element by means of the wiring pattern.
摘要翻译：非接触型IC卡包括具有第一表面和第二表面的绝缘膜。平面线圈布置在膜的第一表面上。半导体元件布置在膜的第一表面上。膜具有使平面线圈的端子和半导体元件的电极端子露出到膜的第二表面的通孔。由导电膏组成的布线图案填充在通孔中，沿着膜的第二表面延伸，使得平面线圈的端子通过布线图形电连接到半导体元件的电极端子。

6. 发明授权

US06255725B1 IC card and plane coil for IC card 失效
标题翻译： IC卡和IC卡平面线圈
公开(公告)号：US06255725B1
公开(公告)日：2001-07-03
申请号：US09492923
申请日：2000-01-28
申请人： Masatoshi Akagawa , Daisuke Ito
发明人： Masatoshi Akagawa , Daisuke Ito
IPC分类号： H01L2302
CPC分类号： G06K19/0775 , G06K19/07749 , G06K19/07779 , G06K19/07783 , H01F5/003 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014
摘要： Thickness of an IC card is decreased, and the manufacturing efficiency of the IC card is enhanced so as to reduce the manufacturing cost. The IC card comprises: a semiconductor element 14 having electrodes; a plane coil 12 formed in such a manner that a conductor 12b is wound on the same face, having terminals 12a at respective ends; bonding wires 16 for electrically connecting terminals at both ends of the plane coil to the electrodes of the semiconductor element; and resin films 10 for sealing the semiconductor element, plane coil and bonding wires 16 when they are interposed between the resin films, wherein the thickness of the semiconductor element 14 is smaller than the thickness of the plane coil 12 and does not interfere with the conductor of the plane coil, and a thin wall thickness portion 12c is formed on a front face of the conductor of the plane coil through which the bonding wires can pass without protruding from the region of the thickness of the plane coil.
摘要翻译：降低IC卡的厚度，提高IC卡的制造效率，降低制造成本。 IC卡包括：具有电极的半导体元件14; 以使导体12b缠绕在同一面上的方式形成的平面线圈12，在端部具有端子12a; 用于将平面线圈两端的端子电连接到半导体元件的电极的接合线16; 以及树脂膜10，用于当半导体元件14的厚度小于平面线圈12的厚度并且不干扰导体时，将半导体元件，平面线圈和接合线16密封在树脂膜之间并且在平面线圈的导体的正面上形成薄壁厚部12c，接合线可以通过该前导面而不从平面线圈的厚度区域突出。

7. 发明授权

US5886415A Anisotropic conductive sheet and printed circuit board 失效
公开(公告)号：US5886415A
公开(公告)日：1999-03-23
申请号：US786615
申请日：1997-01-17
申请人： Masatoshi Akagawa
发明人： Masatoshi Akagawa
IPC分类号： H01L21/60 , H01L23/498 , H01L23/532 , H05K1/03 , H05K3/32 , H05K3/40 , H05K3/46 , H01L23/29 , H01L23/48 , H01L23/52 , H01L23/58
CPC分类号： H01L24/31 , H01L23/49816 , H01L23/49827 , H01L23/5328 , H01L24/28 , H01L24/83 , H05K3/4617 , H01L2224/13016 , H01L2224/13022 , H01L2224/13111 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/29355 , H01L2224/81903 , H01L2224/8319 , H01L2224/838 , H01L2224/83851 , H01L24/12 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/14 , H01L2924/1517 , H01L2924/1579 , H01L2924/19041 , H01L2924/19043 , H05K1/0373 , H05K2201/0215 , H05K3/323 , H05K3/4084 , H05K3/4647
摘要： An anisotropic conductive sheet material includes a resin and conductive fillers, such as metallic particles, added in the resin. A conductive layer is formed on one of the surfaces of the anisotropic conductive sheet material. A circuit board includes a substrate having first and second surfaces and a circuit pattern being formed on the first surface of the substrate, an anisotropic conductive sheet having first and second surfaces, a circuit pattern being formed on the first surface thereof. The second surface of the anisotropic conductive sheet is adhered to the first surface of the substrate in such a manner that the circuit patterns are electrically connected to each other by means of the anisotropic conductive sheet. An electrically insulative layer formed on the first surface of the anisotropic conductive sheet to cover the circuit pattern thereof, except that external connecting portions thereof are exposed.

8. 发明授权

US5404273A Semiconductor-device package and semiconductor device 失效
标题翻译：半导体器件封装和半导体器件
公开(公告)号：US5404273A
公开(公告)日：1995-04-04
申请号：US216323
申请日：1994-03-23
申请人： Masatoshi Akagawa
发明人： Masatoshi Akagawa
IPC分类号： H01L21/60 , H01L23/057 , H01L23/12 , H01L23/24 , H01L23/367 , H01L23/495 , H01L23/498 , H01L23/50 , H05K7/20 , H01L23/28
CPC分类号： H01L24/50 , H01L23/057 , H01L23/24 , H01L23/3675 , H01L23/49572 , H01L23/49833 , H01L24/91 , H01L2224/48091 , H01L2224/49109 , H01L2224/73207 , H01L2224/73253 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/15311 , H01L2924/1532 , H01L2924/16195 , H01L2924/181
摘要： A semiconductor-device package includes: a printed circuit board which has a chip-accommodating hole in its center portion and which has external connection terminals formed on its one side and a flexible substrate which has a supporting film having a central hole coaxial with the chip-accommodating hole, a given circuit pattern which is formed on the supporting film and inner leads which project inside the central hole and which have micro patterns, the flexible substrate being bonded on the other side of the circuit pattern of the printed circuit board with electrical conduction between them.
摘要翻译：半导体器件封装包括：印刷电路板，其中心部分具有芯片容纳孔，并且其一侧上形成有外部连接端子;以及柔性基板，该柔性基板具有与芯片同轴的中心孔形成在支撑膜上的给定电路图案和在中心孔内突出并具有微图案的内引线，柔性基板通过电气接合在印刷电路板的电路图案的另一侧上它们之间的传导。

9. 发明授权

US07793412B2 Component-embedded board fabrication method 有权
标题翻译：组件嵌入式板制造方法
公开(公告)号：US07793412B2
公开(公告)日：2010-09-14
申请号：US10612222
申请日：2003-07-03
申请人： Masatoshi Akagawa , Kazunari Sekigawa , Shinichi Wakabayashi
发明人： Masatoshi Akagawa , Kazunari Sekigawa , Shinichi Wakabayashi
IPC分类号： H05K3/30
CPC分类号： H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/97 , H01L2224/24011 , H01L2224/2402 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2224/76155 , H01L2224/8203 , H01L2224/82102 , H01L2224/92244 , H01L2224/97 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01039 , H01L2924/01056 , H01L2924/01073 , H01L2924/01078 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H05K1/185 , Y10T29/49004 , Y10T29/49117 , Y10T29/49126 , Y10T29/49131 , Y10T29/49146 , Y10T29/49155 , Y10T29/49165 , Y10T29/53061 , Y10T29/53087 , Y10T29/53174 , Y10T29/532 , H01L2224/82 , H01L2924/00
摘要： A component-embedded board fabrication method includes detecting, before the board is covered with a first insulating layer, the actual position of a first electronic component formed on a surface of the board, calculating a displacement between the design position of the first electronic component on the surface of the board and holding the displacement as first displacement data, and correcting, based on the first displacement data, design data to be used for processing the board after the board is covered with the first insulating layer.
摘要翻译：组件嵌入式板的制造方法包括在板被第一绝缘层覆盖之前，检测形成在板的表面上的第一电子部件的实际位置，计算第一电子部件的设计位置之间的位移，将所述板的表面保持位移作为第一位移数据，并且基于所述第一位移数据，校正在所述板被所述第一绝缘层覆盖之后用于处理所述板的设计数据。

10. 发明授权

US06964887B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06964887B2
公开(公告)日：2005-11-15
申请号：US10454482
申请日：2003-06-05
申请人： Masatoshi Akagawa
发明人： Masatoshi Akagawa
IPC分类号： H05K1/18 , H01L21/60 , H01L23/12 , H01L23/31 , H01L23/498 , H01L23/538 , H05K3/46 , H01L21/44 , H01L21/48 , H01L21/50 , H01L21/82
CPC分类号： H01L23/3121 , H01L23/49816 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/97 , H01L2224/24225 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2224/82 , H01L2224/19 , H01L2224/83 , H01L2924/00
摘要： Method for manufacturing a semiconductor device wherein thin semiconductor chips having a thickness of 50 μm or so are imbedded and mounted inside a package, and multi-level stacking is facilitated by forming external connection terminals on both surfaces of the package, or, alternatively, exposing the terminal formation portions of the wiring pattern, to which the external conncetion terminals are to be connected, out of a solder resist layer.
摘要翻译：制造半导体器件的方法，其中厚度为50μm的薄半导体芯片嵌入并安装在封装内，并且通过在封装的两个表面上形成外部连接端子，或者可选地，暴露将要连接的外部连接端子的布线图案的端子形成部分从阻焊层中排出。

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