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1. 发明授权

US08450205B2 Redundancy design with electro-migration immunity and method of manufacture 失效
标题翻译：具有电迁移免疫力的冗余设计和制造方法
公开(公告)号：US08450205B2
公开(公告)日：2013-05-28
申请号：US13474244
申请日：2012-05-17
申请人： Louis L. Hsu , Conal E. Murray , Ping-Chuan Wang , Chih-Chao Yang
发明人： Louis L. Hsu , Conal E. Murray , Ping-Chuan Wang , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76838 , H01L21/76847 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.
摘要翻译：提供了基本上不受电迁移（EM）损害的高直流（DC）的IC互连以及IC互连的制造方法。一种结构包括层间电线之间的交叉处的通孔簇结构。通孔结构包括多个通孔，每个通孔填充有金属并衬有衬垫材料。至少两个相邻的通孔彼此接触并且多个通孔降低了层间电线之间的电流负载。

2. 发明授权

US08351166B2 Leakage sensor and switch device for deep-trench capacitor array 有权
标题翻译：泄漏传感器和开关器件用于深沟槽电容阵列
公开(公告)号：US08351166B2
公开(公告)日：2013-01-08
申请号：US12508665
申请日：2009-07-24
申请人： Howard H. Chen , Kai D. Feng , Louis L. Hsu , Seongwon Kim
发明人： Howard H. Chen , Kai D. Feng , Louis L. Hsu , Seongwon Kim
IPC分类号： H01G7/16 , G01R31/12
CPC分类号： G01R31/024 , G01R31/028
摘要： A high-density deep trench capacitor array with a plurality of leakage sensors and switch devices. Each capacitor array further comprises a plurality of sub-arrays, wherein the leakage in each sub-array is independently controlled by a sensor and switch unit. The leakage sensor comprises a current mirror, a transimpedance amplifier, a voltage comparator, and a timer. If excessive leakage current is detected, the switch unit will automatically disconnect the leaky capacitor module to reduce stand-by power and improve yield. An optional solid-state resistor can be formed on top of the deep trench capacitor array to increase the temperature and speed up the leakage screening process.
摘要翻译：一种高密度深沟槽电容阵列，具有多个漏电传感器和开关器件。每个电容器阵列还包括多个子阵列，其中每个子阵列中的泄漏由传感器和开关单元独立地控制。泄漏传感器包括电流镜，跨阻放大器，电压比较器和定时器。如果检测到过大的漏电流，开关单元将自动断开泄漏电容器模块，以降低待机功率并提高产量。可以在深沟槽电容器阵列的顶部形成可选的固态电阻器，以增加温度并加快泄漏检测过程。

3. 发明授权

US08324102B2 Techniques for impeding reverse engineering 有权
标题翻译：阻止逆向工程的技术
公开(公告)号：US08324102B2
公开(公告)日：2012-12-04
申请号：US13169248
申请日：2011-06-27
申请人： Louis L. Hsu , Rajiv V. Joshi , David W. Kruger
发明人： Louis L. Hsu , Rajiv V. Joshi , David W. Kruger
IPC分类号： H01L21/00
CPC分类号： H01L21/76816 , H01L21/76825 , H01L21/76831 , H01L21/76834 , H01L23/573 , H01L27/02 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.
摘要翻译：提供了反逆向工程技术。一方面，提供了一种在绝缘层中形成至少一个特征的方法。该方法包括以下步骤。离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同在植入区域外侧。空隙填充有至少一种导体材料以在绝缘层中形成特征。

4. 发明申请

US20120225549A1 REDUNDANCY DESIGN WITH ELECTRO-MIGRATION IMMUNITY AND METHOD OF MANUFACTURE 失效
公开(公告)号：US20120225549A1
公开(公告)日：2012-09-06
申请号：US13474244
申请日：2012-05-17
申请人： Louis L. HSU , Conal E. MURRAY , Ping-Chuan WANG , Chih-Chao YANG
发明人： Louis L. HSU , Conal E. MURRAY , Ping-Chuan WANG , Chih-Chao YANG
IPC分类号： H01L21/768
CPC分类号： H01L21/76816 , H01L21/76838 , H01L21/76847 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.

5. 发明授权

US08219040B2 Transmitter bandwidth optimization circuit 有权
标题翻译：发射机带宽优化电路
公开(公告)号：US08219040B2
公开(公告)日：2012-07-10
申请号：US11769128
申请日：2007-06-27
申请人： Louis L. Hsu , Hayden C. Cranford, Jr. , Joseph Natonio , James D. Rockrohr , Huihao Xu , Steven J. Zier
发明人： Louis L. Hsu , Hayden C. Cranford, Jr. , Joseph Natonio , James D. Rockrohr , Huihao Xu , Steven J. Zier
IPC分类号： H04B1/02
CPC分类号： H04L25/0286 , H04L25/0272
摘要： A method is provided for operating a transmitter integrated in a microelectronic element. In a calibration phase, a plurality of operational parameters are stored for controlling a frequency response of the transmitter under each of a plurality of corresponding operating conditions. Upon detecting an operating condition such as a temperature or power supply voltage level, the corresponding stored operational parameter is applied to the transmitter to control the frequency response.
摘要翻译：提供了一种用于操作集成在微电子元件中的发射器的方法。在校准阶段中，存储多个操作参数，用于在多个对应的操作条件中的每一个下控制发射机的频率响应。在检测到诸如温度或电源电压电平的操作条件时，将相应的存储的操作参数应用于发射机以控制频率响应。

6. 发明授权

US08188786B2 Modularized three-dimensional capacitor array 有权
标题翻译：模块化三维电容阵列
公开(公告)号：US08188786B2
公开(公告)日：2012-05-29
申请号：US12565802
申请日：2009-09-24
申请人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
发明人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
IPC分类号： H01G4/38 , H03K17/16
CPC分类号： H01L28/40 , H01L22/14 , H01L22/22 , H01L22/34 , H01L23/5223 , H01L27/0688 , H01L27/0805 , H01L28/60 , H01L2924/0002 , Y10T307/865 , H01L2924/00
摘要： A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.
摘要翻译：模块化电容器阵列包括多个电容器模块。每个电容器模块包括电容器和被配置为电气断开电容器的开关装置。开关装置包括：感测单元，被配置为检测电容器的泄漏电平，使得如果泄漏电流超过预定电平，则开关装置电连接电容器。每个电容器模块可以包括单个电容器板，两个电容器板或多于两个的电容器板。泄漏传感器和开关装置用于电气断开任何电容器阵列的电容器模块，从而保护电容器阵列免于漏电。

7. 发明授权

US07888729B2 Flash memory gate structure for widened lithography window 失效
标题翻译：用于加宽光刻窗的闪存门结构
公开(公告)号：US07888729B2
公开(公告)日：2011-02-15
申请号：US12198345
申请日：2008-08-26
申请人： Kangguo Cheng , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu
发明人： Kangguo Cheng , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L29/66825
摘要： A first portion of a semiconductor substrate belonging to a flash memory device region is recessed to a recess depth to form a recessed region, while a second portion of the semiconductor substrate belonging to a logic device region is protected with a masking layer. A first gate dielectric layer and a first gate conductor layer formed within the recessed region such that the first gate conductive layer is substantially coplanar with the top surfaces of the shallow trench isolation structures. A second gate dielectric layer, a second gate conductor layer, and a gate cap hard mask layer, each having a planar top surface, is subsequently patterned. The pattern of the gate structure in the flash memory device region is transferred into the first gate conductor layer and the first gate dielectric layer to form a floating gate and a first gate dielectric, respectively.
摘要翻译：属于闪存器件区域的半导体衬底的第一部分凹陷到凹陷深度以形成凹陷区域，而属于逻辑器件区域的半导体衬底的第二部分被掩蔽层保护。形成在凹陷区域内的第一栅介质层和第一栅极导体层，使得第一栅极导电层与浅沟槽隔离结构的顶表面基本共面。随后对第二栅介质层，第二栅极导体层和栅帽硬掩模层进行构图，每个具有平坦的顶表面。闪存器件区域中的栅极结构的图案被转移到第一栅极导体层和第一栅极介电层中，以分别形成浮置栅极和第一栅极电介质。

8. 发明申请

US20110031633A1 AIR CHANNEL INTERCONNECTS FOR 3-D INTEGRATION 有权
标题翻译：用于三维集成的空气通道互连
公开(公告)号：US20110031633A1
公开(公告)日：2011-02-10
申请号：US12536176
申请日：2009-08-05
申请人： Louis L. Hsu , Brain L. Ji , Fei Liu , Conal E. Murray
发明人： Louis L. Hsu , Brain L. Ji , Fei Liu , Conal E. Murray
IPC分类号： H01L23/532 , H01L21/50 , H01L21/768
CPC分类号： H01L23/467 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof. In addition, the 3D chip stack structure further includes one or more openings in a peripheral region of the chip stack structure that lead into and out of the air channel interconnect network, so that air can flow into and out of the air channel interconnect network through the one or more openings to remove heat from the chip stack structure.
摘要翻译：提供三维（3D）芯片堆叠结构及其结构的制造方法。 3D芯片堆叠结构包括互连并结合在一起的多个垂直堆叠的芯片，其中每个垂直堆叠的芯片包括一个或多个IC器件层。 3D芯片堆叠结构还包括嵌入在芯片堆叠结构内的空气通道互连网络，并且其中空气通道互连网络形成在至少两个晶片之间，所述至少两个晶片彼此接合在垂直堆叠的晶片之间，并且在至少两个结合在其接合界面处的垂直堆叠的晶片的晶片。此外，3D芯片堆叠结构还包括在芯片堆叠结构的外围区域中的一个或多个开口，其引入和流出空气通道互连网络，使得空气可以流入和流出空气通道互连网络，通过一个或多个开口以从芯片堆叠结构移除热量。

9. 发明申请

US20100225380A1 Implementing Tamper Resistant Integrated Circuit Chips 有权
标题翻译：实施防篡改集成电路芯片
公开(公告)号：US20100225380A1
公开(公告)日：2010-09-09
申请号：US12396512
申请日：2009-03-03
申请人： Louis L. Hsu , David W. Kruger , James S. Mason , Richard W. Oldrey
发明人： Louis L. Hsu , David W. Kruger , James S. Mason , Richard W. Oldrey
IPC分类号： H03K17/78
CPC分类号： H01L23/576 , H01L2224/48091 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： A method and tamper resistant circuit for resisting tampering including reverse engineering in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A sensing device for detecting a chip tampering state is formed with the semiconductor chip including the circuitry to be protected. A tamper resistant control signal generator is coupled to the sensing unit for generating a tamper resistant control signal responsive to a detected chip tampering state. A functional operation inhibit circuit is coupled to the tamper resistant control signal generator for inhibiting functional operation of the circuitry to be protected responsive to the tamper resistant control signal.
摘要翻译：提供一种用于抵抗篡改的方法和防篡改电路，包括半导体芯片中的逆向工程，以及设置有被摄体电路的设计结构。用于检测芯片篡改状态的感测装置由包括待保护电路的半导体芯片形成。防篡改控制信号发生器耦合到感测单元，用于响应于检测到的芯片篡改状态产生防篡改控制信号。功能操作禁止电路耦合到防篡改控制信号发生器，用于响应于防篡改控制信号而禁止要被保护的电路的功能操作。

10. 发明申请

US20100201403A1 MULTI-LEVEL POWER SUPPLY SYSTEM FOR A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR 审中-公开
标题翻译：用于补充金属氧化物半导体的多级电源系统
公开(公告)号：US20100201403A1
公开(公告)日：2010-08-12
申请号：US12761872
申请日：2010-04-16
申请人： Rajiv V. Joshi , Louis L. Hsu
发明人： Rajiv V. Joshi , Louis L. Hsu
IPC分类号： H03L5/00 , H02J1/10
CPC分类号： G11C11/4074 , G06F1/26 , G11C5/14 , Y10T307/305
摘要： There is provided a method that includes comparing a voltage level (Vs1) of a lower voltage supply bus to a voltage level (Vs2) of a higher voltage supply bus, and routing current from the lower voltage supply bus to the higher voltage supply bus if Vs2
摘要翻译：提供了一种方法，其包括将较低电压供应总线的电压电平（Vs1）与较高电压电源总线的电压电平（Vs2）进行比较，以及将电流从较低电压供应总线路由到较高电压供应总线，如果 Vs2

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