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1. 发明申请

US20120188002A1 MODULARIZED THREE-DIMENSIONAL CAPACITOR ARRAY 有权
标题翻译：模块化三维电容阵列
公开(公告)号：US20120188002A1
公开(公告)日：2012-07-26
申请号：US13438230
申请日：2012-04-03
申请人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
发明人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
IPC分类号： H03K17/687 , H01L21/02
CPC分类号： H01L28/40 , H01L22/14 , H01L22/22 , H01L22/34 , H01L23/5223 , H01L27/0688 , H01L27/0805 , H01L28/60 , H01L2924/0002 , Y10T307/865 , H01L2924/00
摘要： A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.
摘要翻译：模块化电容器阵列包括多个电容器模块。每个电容器模块包括电容器和被配置为电气断开电容器的开关装置。开关装置包括：感测单元，被配置为检测电容器的泄漏电平，使得如果泄漏电流超过预定电平，则开关装置电连接电容器。每个电容器模块可以包括单个电容器板，两个电容器板或多于两个的电容器板。泄漏传感器和开关装置用于电气断开任何电容器阵列的电容器模块，从而保护电容器阵列免于漏电。

2. 发明申请

US20110069425A1 MODULARIZED THREE-DIMENSIONAL CAPACITOR ARRAY 有权
标题翻译：模块化三维电容阵列
公开(公告)号：US20110069425A1
公开(公告)日：2011-03-24
申请号：US12565802
申请日：2009-09-24
申请人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
发明人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
IPC分类号： H01G4/38 , H01L21/02 , H03K17/687
CPC分类号： H01L28/40 , H01L22/14 , H01L22/22 , H01L22/34 , H01L23/5223 , H01L27/0688 , H01L27/0805 , H01L28/60 , H01L2924/0002 , Y10T307/865 , H01L2924/00
摘要： A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.
摘要翻译：模块化电容器阵列包括多个电容器模块。每个电容器模块包括电容器和被配置为电气断开电容器的开关装置。开关装置包括：感测单元，被配置为检测电容器的泄漏电平，使得如果泄漏电流超过预定电平，则开关装置电连接电容器。每个电容器模块可以包括单个电容器板，两个电容器板或多于两个的电容器板。泄漏传感器和开关装置用于电气断开任何电容器阵列的电容器模块，从而保护电容器阵列免于漏电。

3. 发明授权

US08188786B2 Modularized three-dimensional capacitor array 有权
标题翻译：模块化三维电容阵列
公开(公告)号：US08188786B2
公开(公告)日：2012-05-29
申请号：US12565802
申请日：2009-09-24
申请人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
发明人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
IPC分类号： H01G4/38 , H03K17/16
CPC分类号： H01L28/40 , H01L22/14 , H01L22/22 , H01L22/34 , H01L23/5223 , H01L27/0688 , H01L27/0805 , H01L28/60 , H01L2924/0002 , Y10T307/865 , H01L2924/00
摘要： A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.
摘要翻译：模块化电容器阵列包括多个电容器模块。每个电容器模块包括电容器和被配置为电气断开电容器的开关装置。开关装置包括：感测单元，被配置为检测电容器的泄漏电平，使得如果泄漏电流超过预定电平，则开关装置电连接电容器。每个电容器模块可以包括单个电容器板，两个电容器板或多于两个的电容器板。泄漏传感器和开关装置用于电气断开任何电容器阵列的电容器模块，从而保护电容器阵列免于漏电。

4. 发明授权

US08487696B2 Modularized three-dimensional capacitor array 有权
标题翻译：模块化三维电容阵列
公开(公告)号：US08487696B2
公开(公告)日：2013-07-16
申请号：US13438230
申请日：2012-04-03
申请人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
发明人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
IPC分类号： G01R31/28 , H03K17/687
CPC分类号： H01L28/40 , H01L22/14 , H01L22/22 , H01L22/34 , H01L23/5223 , H01L27/0688 , H01L27/0805 , H01L28/60 , H01L2924/0002 , Y10T307/865 , H01L2924/00
摘要： A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.
摘要翻译：模块化电容器阵列包括多个电容器模块。每个电容器模块包括电容器和被配置为电气断开电容器的开关装置。开关装置包括：感测单元，被配置为检测电容器的泄漏电平，使得如果泄漏电流超过预定电平，则开关装置电连接电容器。每个电容器模块可以包括单个电容器板，两个电容器板或多于两个的电容器板。泄漏传感器和开关装置用于电气断开任何电容器阵列的电容器模块，从而保护电容器阵列免于漏电。

5. 发明申请

US20110254121A1 PROGRAMMABLE ANTI-FUSE STRUCTURES WITH CONDUCTIVE MATERIAL ISLANDS 失效
标题翻译：具有导电材料岛的可编程防结构
公开(公告)号：US20110254121A1
公开(公告)日：2011-10-20
申请号：US12761780
申请日：2010-04-16
申请人： Kangguo Cheng , Louis L. Hsu , William R. Tonti , Chih-Chao Yang
发明人： Kangguo Cheng , Louis L. Hsu , William R. Tonti , Chih-Chao Yang
IPC分类号： H01L23/525 , H01L21/768 , G06F17/50
CPC分类号： H01L23/5252 , G06F17/505 , H01L2924/0002 , H01L2924/00
摘要： Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.
摘要翻译：提供了电压可编程的抗熔丝结构和方法，其包括位于介于两个相邻导电特征之间的电介质表面上的至少一个导电材料岛。在一个实施例中，反熔丝结构包括具有嵌入其中的至少两个相邻导电特征的电介质材料。至少一个导电材料岛位于介电材料的位于至少两个相邻导电特征之间的上表面上。电介质覆盖层位于电介质材料的暴露表面上，至少一个导电材料岛和至少两个相邻的导电特征。当反熔丝结构处于编程状态时，介电击穿路径存在于介电材料中，介电材料位于至少一个导电材料岛之下，该导电材料岛传导电流以电耦合两个相邻导电特征。

6. 发明授权

US07092235B2 Method for adjusting capacitance of an on-chip capacitor 失效
标题翻译：调整片上电容器电容的方法
公开(公告)号：US07092235B2
公开(公告)日：2006-08-15
申请号：US11043760
申请日：2005-01-26
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01G4/06
CPC分类号： H01G4/255 , H01L22/22 , H01L28/40
摘要： A method and apparatus, is herein disclosed, for adjusting capacitance of an on-chip capacitor formed on a substrate. A plurality of conductive layers is separated by a layer ofdielectric material. The dielectric material of the capacitor is exposed to an ion beam. The ion beam includes ions of at least one material to modify a dielectric constant of the dielectric material.
摘要翻译：本文公开了一种用于调节形成在衬底上的片上电容器的电容的方法和装置。多个导电层被一层电介质材料隔开。电容器的电介质材料暴露于离子束。离子束包括至少一种材料的离子，以改变介电材料的介电常数。

7. 发明授权

US06869895B1 Method for adjusting capacitance of an on-chip capacitor 失效
标题翻译：调整片上电容器电容的方法
公开(公告)号：US06869895B1
公开(公告)日：2005-03-22
申请号：US10674719
申请日：2003-09-30
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01G4/255 , H01L21/02 , H01L21/66 , H01L21/31
CPC分类号： H01G4/255 , H01L22/22 , H01L28/40
摘要： A method and apparatus for adjusting capacitance of an on-chip capacitor uses exposure of a dielectric material of the capacitor to an ion beam comprising ions of at least one material to modify a dielectric constant of the dielectric material.
摘要翻译：用于调整片上电容器的电容的方法和装置使用将电容器的电介质材料暴露于包含至少一种材料的离子的离子束，以改变介电材料的介电常数。

8. 发明授权

US08450205B2 Redundancy design with electro-migration immunity and method of manufacture 失效
标题翻译：具有电迁移免疫力的冗余设计和制造方法
公开(公告)号：US08450205B2
公开(公告)日：2013-05-28
申请号：US13474244
申请日：2012-05-17
申请人： Louis L. Hsu , Conal E. Murray , Ping-Chuan Wang , Chih-Chao Yang
发明人： Louis L. Hsu , Conal E. Murray , Ping-Chuan Wang , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76838 , H01L21/76847 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.
摘要翻译：提供了基本上不受电迁移（EM）损害的高直流（DC）的IC互连以及IC互连的制造方法。一种结构包括层间电线之间的交叉处的通孔簇结构。通孔结构包括多个通孔，每个通孔填充有金属并衬有衬垫材料。至少两个相邻的通孔彼此接触并且多个通孔降低了层间电线之间的电流负载。

9. 发明申请

US20090280636A1 METHODS OF FABRICATING INTERCONNECT STRUCTURES CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS 有权
标题翻译：电气保险丝各种接插材料互连结构的制作方法及其他相关应用
公开(公告)号：US20090280636A1
公开(公告)日：2009-11-12
申请号：US12118161
申请日：2008-05-09
申请人： Louis L. Hsu , William R. Tonti , Chih-Chao Yang
发明人： Louis L. Hsu , William R. Tonti , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76807 , H01L21/76825 , H01L21/76849 , H01L23/5256 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Methods are provided for fabricating interconnect structures containing various capping materials for electrical fuses and other related applications. The method includes forming a first interconnect structure having a first interfacial structure and forming a second interconnect structure adjacent to the first structure. The second interconnect structure is formed with a second interfacial structure different from the first interfacial structure of the first interconnect structure.
摘要翻译：提供了用于制造包含用于电熔丝和其它相关应用的各种封盖材料的互连结构的方法。该方法包括形成具有第一界面结构并形成与第一结构相邻的第二互连结构的第一互连结构。第二互连结构形成有与第一互连结构的第一界面结构不同的第二界面结构。

10. 发明授权

US07605072B2 Interconnect structure with a barrier-redundancy feature 有权
标题翻译：互连结构与屏障冗余功能
公开(公告)号：US07605072B2
公开(公告)日：2009-10-20
申请号：US11925161
申请日：2007-10-26
申请人： Chih-Chao Yang , Louis L. Hsu
发明人： Chih-Chao Yang , Louis L. Hsu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure that includes a barrier-redundancy feature which is capable of avoiding a sudden open circuit after an electromigration (EM) failure as well as a method of forming the same are provided. In accordance with the present invention, the barrier-redundancy feature is located within preselected locations within the interconnect structure including in a wide line region, a thin line region or any combination thereof. The barrier-redundancy feature includes an electrical conductive material located between, and in contact with, a conductive line diffusion barrier of a conductive line and a via diffusion barrier of an overlying via. The presence of the inventive barrier-redundancy feature creates an electrical path between the via diffusion barrier along the sidewalls of the via and the conductive line diffusion barrier along the sidewalls of the conductive line. This electrical path generated by the inventive barrier-redundancy feature can avoid a sudden open circuit resulting from EM failure at the bottom of the via. The presence of the inventive barrier-redundancy feature within an interconnect structure provides sufficient time for chip replacement or system operation.
摘要翻译：提供一种互连结构，其包括能够在电迁移（EM）故障之后避免突然断路的障碍物冗余特征以及其形成方法。根据本发明，阻挡冗余特征位于互连结构内的预选位置，包括在宽线区域，细线区域或其任何组合中。阻挡层冗余特征包括导电材料，其位于导电线的导电线扩散阻挡层和上覆通孔的通孔扩散阻挡层之间并与之接触。本发明的阻挡 - 冗余特征的存在在沿着导电线的侧壁的通孔的侧壁和导电线扩散阻挡层之间形成通路扩散阻挡层之间的电路径。由本发明的障碍物冗余特征产生的该电路径可以避免由于通孔底部的EM故障导致的突然开路。在互连结构内部存在本发明的障碍物冗余特征为芯片更换或系统操作提供足够的时间。

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