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1. 发明申请

US20120151154A1 LATENCY MANAGEMENT SYSTEM AND METHOD FOR MULTIPROCESSOR SYSTEM 有权
标题翻译：多处理器系统的延期管理系统和方法
公开(公告)号：US20120151154A1
公开(公告)日：2012-06-14
申请号：US13163948
申请日：2011-06-20
申请人： Woong Seo , Soo-Jung Ryu , Moo-Kyoung Chung , HoYoung Kim , Young-Chul Cho
发明人： Woong Seo , Soo-Jung Ryu , Moo-Kyoung Chung , HoYoung Kim , Young-Chul Cho
IPC分类号： G06F12/08
CPC分类号： G06F15/167
摘要： A latency management apparatus and method are provided. A latency management apparatus for a multiprocessor system having a plurality of processors and shared memory, when the shared memory and each of the processors is configured to generate a delayed signal, includes a delayed signal detector configured to detect the generated delayed signal; and one or more latency managers configured to manage an operation latency of any one of the processors upon detection of the delayed signal.
摘要翻译：提供了延迟管理装置和方法。一种用于具有多个处理器和共享存储器的多处理器系统的等待时间管理装置，当所述共享存储器和每个所述处理器被配置为产生延迟信号时，包括被配置为检测所生成的延迟信号的延迟信号检测器; 以及一个或多个延迟管理器，被配置为在检测到延迟的信号时管理任一个处理器的操作等待时间。

2. 发明申请

US20120092987A1 ROUTING APPARATUS AND NETWORK APPARATUS 有权
标题翻译：路由设备和网络设备
公开(公告)号：US20120092987A1
公开(公告)日：2012-04-19
申请号：US13092919
申请日：2011-04-23
申请人： Moo-Kyoung CHUNG , Soo-Jung RYU , Woong SEO , Ho-Young KIM , Young-Chul CHO
发明人： Moo-Kyoung CHUNG , Soo-Jung RYU , Woong SEO , Ho-Young KIM , Young-Chul CHO
IPC分类号： H04L12/56 , H04L12/26
CPC分类号： H04L45/60
摘要： A routing apparatus and a network apparatus that are capable of improving general system performance by compressing/decompressing data and transmitting the result of the compression/decompression, are provided. The routing apparatus may compress and/or decompress input data, and may transmit the compressed and/or decompressed input data.
摘要翻译：提供能够通过压缩/解压缩数据和发送压缩/解压缩的结果来提高一般系统性能的路由设备和网络设备。路由设备可以压缩和/或解压缩输入数据，并且可以传送压缩和/或解压缩的输入数据。

3. 发明授权

US09349155B2 Computing apparatus and method using X-Y stack memory 有权
标题翻译：使用X-Y堆栈存储器的计算设备和方法
公开(公告)号：US09349155B2
公开(公告)日：2016-05-24
申请号：US13171772
申请日：2011-06-29
申请人： Soo-Jung Ryu , Sung-Bae Park , Woong Seo , Young-Chul Cho , Jeong-Wook Kim , Moo-Kyoung Chung , Ho-Young Kim
发明人： Soo-Jung Ryu , Sung-Bae Park , Woong Seo , Young-Chul Cho , Jeong-Wook Kim , Moo-Kyoung Chung , Ho-Young Kim
IPC分类号： G06T1/60 , G06F13/00 , G06F12/02
CPC分类号： G06T1/60
摘要： A computing apparatus is provided. The computing apparatus includes a memory unit configured to have an address space defined as a multidimensional space having at least two axes, and a memory access unit configured to include a first pointer register storing a first pointer pointing to a row corresponding to the first axis and a second pointer register storing a second pointer pointing to a column corresponding to the second axis.
摘要翻译：提供了一种计算装置。计算装置包括存储单元，其被配置为具有被定义为具有至少两个轴的多维空间的地址空间，以及存储器访问单元，其被配置为包括存储指向与第一轴对应的行的第一指针的第一指针寄存器，以及存储指向对应于第二轴的列的第二指针的第二指针寄存器。

4. 发明申请

US20130067203A1 PROCESSING DEVICE AND A SWIZZLE PATTERN GENERATOR 审中-公开
标题翻译：处理装置和SWIZLE模式发生器
公开(公告)号：US20130067203A1
公开(公告)日：2013-03-14
申请号：US13618309
申请日：2012-09-14
申请人： Moo-Kyoung Chung , Woong Seo , Ho-Young Kim , Soo-Jung Ryu , Dong-Hoon Yoo , Jin-Seok Lee , Yeon-Gon Cho , Chang-Moo Kim , Seung-Hun Jin
发明人： Moo-Kyoung Chung , Woong Seo , Ho-Young Kim , Soo-Jung Ryu , Dong-Hoon Yoo , Jin-Seok Lee , Yeon-Gon Cho , Chang-Moo Kim , Seung-Hun Jin
IPC分类号： G06F9/302
CPC分类号： G06F9/30032 , G06F9/30036
摘要： A swizzle pattern generator is provided to reduce an overhead due to execution of a swizzle instruction in vector processing. The swizzle pattern generator is configured to provide swizzle patterns with respect to data sets of at least one vector register or vector processing unit. The swizzle pattern generator may be reconfigurable to generate various swizzle patterns for different vector operations.
摘要翻译：提供了一种旋转模式发生器，以减少由于在矢量处理中执行旋转指令而导致的开销。旋转图案生成器被配置为提供关于至少一个向量寄存器或向量处理单元的数据集的旋转图案。旋转图案发生器可以是可重构的，以产生用于不同矢量操作的各种旋转图案。

5. 发明申请

US20120158394A1 SIMULATION APPARATUS AND METHOD FOR MULTICORE SYSTEM 有权
标题翻译：模拟装置及其制作方法
公开(公告)号：US20120158394A1
公开(公告)日：2012-06-21
申请号：US13171017
申请日：2011-06-28
申请人： Young Chul Cho , Soo-Jung Ryu , Moo-Kyoung Chung , Ho-Young Kim , Woong Seo
发明人： Young Chul Cho , Soo-Jung Ryu , Moo-Kyoung Chung , Ho-Young Kim , Woong Seo
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5022 , G06F17/5031 , G06F2217/84
摘要： A simulation apparatus and method for a multicore system are provided. The simulation apparatus may prevent the occurrence of a data collision during the communication between modules and may reduce the overhead generated during simulation. The simulation apparatus may select a plurality of modules to be synchronized in terms of function execution timing based on timing information and may configure a multicore system architecture model using the selected modules. The simulation apparatus may acquire function execution timing information of the modules, control the execution of functions by the modules based on the acquired function execution timing information, and output the results of the control of the execution of functions by the modules.
摘要翻译：提供了一种用于多核系统的模拟装置和方法。模拟装置可以防止在模块之间的通信期间发生数据冲突，并且可以减少模拟期间产生的开销。模拟装置可以基于定时信息来选择要在功能执行定时上同步的多个模块，并且可以使用所选择的模块来配置多核系统体系结构模型。模拟装置可以获取模块的功能执行定时信息，基于所获取的功能执行定时信息控制模块的功能的执行，并且输出模块执行功能的控制结果。

6. 发明申请

US20110116550A1 VIDEO DECODING APPARATUS AND METHOD BASED ON A DATA AND FUNCTION SPLITTING SCHEME 有权
标题翻译：基于数据和功能分割方案的视频解码设备和方法
公开(公告)号：US20110116550A1
公开(公告)日：2011-05-19
申请号：US12837022
申请日：2010-07-15
申请人： Jae Jin Lee , Moo Kyoung Chung , Kyung Su Kim , Jun Young Lee , Seong Mo Park , Nak Woong Eum
发明人： Jae Jin Lee , Moo Kyoung Chung , Kyung Su Kim , Jun Young Lee , Seong Mo Park , Nak Woong Eum
IPC分类号： H04N11/02
CPC分类号： H04N19/436 , H04N19/44 , H04N19/61
摘要： A video decoding apparatus and method based on a data and function splitting scheme are disclosed. The video decoding apparatus based on a data and function splitting scheme includes a variable length decoding unit performing variable length decoding and parsing on a bit stream to acquire residual data and a decoding parameter, and splitting the residual data and the decoding parameter by row; and N (N is a natural number of 2 or larger) number of clusters splitting dequantization and inverse discrete cosine transform (IDCT), motion vector prediction, intra prediction and motion compensation, video restoration, and deblocking function into M number of functions, acquiring the residual data, the decoding parameter, and macroblock (MB) processing information of an upper cluster by column, and splitting the information acquired by column into M number of functions to process the same.
摘要翻译：公开了一种基于数据和功能分解方案的视频解码装置和方法。基于数据和功能分割方案的视频解码装置包括：可变长度解码单元，对比特流执行可变长度解码和解析以获取残差数据和解码参数，并且逐行分割残留数据和解码参数; 并且N（N是2或更大的自然数）将数量分解解量化和逆离散余弦变换（IDCT），运动矢量预测，帧内预测和运动补偿，视频恢复和去块功能的簇数分为M个函数，获取按照列逐列的残差数据，解码参数和宏块（MB）处理信息，并将通过列获取的信息拆分为M个函数以进行处理。

7. 发明申请

US20100074542A1 APPARATUS FOR DECODING CONTEXT ADAPTIVE VARIABLE LENGTH CODE AND TABLE SEARCH METHOD FOR DECODING CONTEXT ADAPTIVE VARIABLE LENGTH CODE 审中-公开
标题翻译：用于解码上下文自适应长度代码和表搜索方法用于解码上下文自适应可变长度代码
公开(公告)号：US20100074542A1
公开(公告)日：2010-03-25
申请号：US12368814
申请日：2009-02-10
申请人： Jae Jin LEE , Moo Kyoung CHUNG , Seung Hyun CHO , Kyung Su KIM , Jun Young LEE , Seong Mo PARK , Nak Woong EUM
发明人： Jae Jin LEE , Moo Kyoung CHUNG , Seung Hyun CHO , Kyung Su KIM , Jun Young LEE , Seong Mo PARK , Nak Woong EUM
IPC分类号： G06F7/06 , G06F17/30
CPC分类号： H04N19/426 , H04N19/44 , H04N19/91
摘要： Provided are an apparatus for decoding a minimum memory access-based context adaptive variable length code (CAVLC) of the moving picture compression standard, H.264, and a table search method for decoding a context adaptive variable length code using the same. The apparatus for decoding a context adaptive variable length code may be useful to improve an overall decoding speed since the repeated memory accesses may be reduced to 2 cycles of memory accesses by reconstructing a context adaptive variable length code table of first decoding information (TrailingOnes) and second decoding information (TotalCoefficient) into 2-step tables and storing the reconstructed 2-step tables in advance and performing a table search to decode the first decoding information and the second decoding information, by using the information stored in the 2-step tables, depending on whether the remaining bits except for the number of leading zero are present in the inputted bit stream.
摘要翻译：提供了一种用于解码运动图像压缩标准H.264的最小存储器访问上下文自适应可变长度码（CAVLC）的装置，以及用于使用其进行上下文自适应可变长度码的解码的表搜索方法。用于对上下文自适应可变长度码进行解码的装置对于提高整体解码速度可能是有用的，因为通过重建第一解码信息（TrailingOnes）的上下文自适应可变长度码表，可以将重复的存储器访问减少到2个周期的存储器访问，第二解码信息（TotalCoefficient）到2步表中，并且通过使用存储在2步表中的信息，预先存储重建的两步表并执行表搜索以解码第一解码信息和第二解码信息，取决于在输入的比特流中是否存在除了前导零的数目之外的剩余比特。

8. 发明申请

US20090138684A1 H.264 CAVLC DECODING METHOD BASED ON APPLICATION-SPECIFIC INSTRUCTION-SET PROCESSOR 失效
标题翻译：基于应用特定指令集处理器的H.264 CAVLC解码方法
公开(公告)号：US20090138684A1
公开(公告)日：2009-05-28
申请号：US12181769
申请日：2008-07-29
申请人： Jae Jin Lee , Jun Young Lee , Moo Kyoung Chung , Seong Mo Park , Nak Woong Eum
发明人： Jae Jin Lee , Jun Young Lee , Moo Kyoung Chung , Seong Mo Park , Nak Woong Eum
IPC分类号： G06F9/30
CPC分类号： H04N19/42 , H04N19/44 , H04N19/91
摘要： Provided is an H.264 Context Adaptive Variable Length Coding (CAVLC) decoding method based on an Application-Specific Instruction-set Processor (ASIP). The H.264 CAVLC decoding method includes determining a plurality of comparison bit strings on the basis of a table of a decoding coefficient, storing lengths of the comparison bit strings in a first register, storing code values of the comparison bit strings in a second register, comparing an input bit stream with the comparison bit strings based on the lengths and code values of the comparison bit strings, and determining value of the decoding coefficient according to a result of comparison between the input bit stream and the comparison bit strings. The method extracts a decoding coefficient using a register in an ASIP without accessing a memory and prevents a reduction in speed caused by memory access, thereby increasing the decoding speed of an H.264 decoder.
摘要翻译：提供了一种基于应用特定指令集处理器（ASIP）的H.264上下文自适应可变长度编码（CAVLC）解码方法。 H.264 CAVLC解码方法包括：基于解码系数的表确定多个比较比特串，将比较比特列的长度存储在第一寄存器中，将比较比特列的代码值存储在第二寄存器根据比较比特串的长度和码值比较输入比特流与比较比特串，并根据输入比特流和比较比特串之间的比较结果确定解码系数的值。该方法使用ASIP中的寄存器提取解码系数，而不访问存储器，并且防止由存储器访问引起的速度降低，从而提高H.264解码器的解码速度。

9. 发明授权

US09524266B2 Latency management system and method for multiprocessor system 有权
标题翻译：多处理器系统的延迟管理系统和方法
公开(公告)号：US09524266B2
公开(公告)日：2016-12-20
申请号：US13163948
申请日：2011-06-20
申请人： Woong Seo , Soo-Jung Ryu , Moo-Kyoung Chung , Ho-Young Kim , Young-Chul Cho
发明人： Woong Seo , Soo-Jung Ryu , Moo-Kyoung Chung , Ho-Young Kim , Young-Chul Cho
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F15/167
CPC分类号： G06F15/167
摘要： A latency management apparatus and method are provided. A latency management apparatus for a multiprocessor system having a plurality of processors and shared memory, when the shared memory and each of the processors is configured to generate a delayed signal, includes a delayed signal detector configured to detect the generated delayed signal; and one or more latency managers configured to manage an operation latency of any one of the processors upon detection of the delayed signal.
摘要翻译：提供了延迟管理装置和方法。一种用于具有多个处理器和共享存储器的多处理器系统的等待时间管理装置，当所述共享存储器和每个所述处理器被配置为产生延迟信号时，包括被配置为检测所生成的延迟信号的延迟信号检测器; 以及一个或多个延迟管理器，被配置为在检测到延迟的信号时管理任一个处理器的操作等待时间。

10. 发明授权

US08977800B2 Multi-port cache memory apparatus and method 有权
标题翻译：多端口缓存存储装置及方法
公开(公告)号：US08977800B2
公开(公告)日：2015-03-10
申请号：US13362460
申请日：2012-01-31
申请人： Moo-Kyoung Chung , Soo-Jung Ryu , Ho-Young Kim , Woong Seo , Young-Chul Cho
发明人： Moo-Kyoung Chung , Soo-Jung Ryu , Ho-Young Kim , Woong Seo , Young-Chul Cho
IPC分类号： G06F12/08
CPC分类号： G06F12/0853 , G06F12/0846
摘要： Provided is a multi-port cache memory apparatus and a method of the multi-port cache memory apparatus. The multi-port memory apparatus may divide an address space into address regions and allocate the divided memory regions to cache banks, thereby preventing the concentration of access to a particular cache.
摘要翻译：提供了一种多端口高速缓存存储装置和多端口高速缓存存储装置的方法。多端口存储装置可以将地址空间划分为地址区域，并将划分的存储区域分配给高速缓存存储体，从而防止对特定高速缓存的访问集中。

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