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1. 发明公开

KR1020130072799A 펄스신호 생성회로, 버스트 오더 제어회로 및 데이터 출력회로 审中-实审
标题翻译：脉冲信号发生电路，脉冲序列控制电路和数据输出电路
公开(公告)号：KR1020130072799A
公开(公告)日：2013-07-02
申请号：KR1020110140385
申请日：2011-12-22
申请人： 에스케이하이닉스 주식회사
发明人： 김광현
IPC分类号： G11C11/4096 , G11C11/4093 , G11C11/4076
CPC分类号： G06F1/12 , G06F1/06 , G11C7/1018 , G11C7/1042 , G11C7/1072 , G11C7/222 , G11C11/4076 , G11C11/4096 , H03K3/00
摘要： PURPOSE: A pulse signal generating circuit, a burst order control circuit, and a data output circuit are provided to reduce the number of shifting units which are operated simultaneously when a pulse signal is generated, thereby reducing the amount of electricity consumption. CONSTITUTION: A control unit (210) activates at least one control clock among multiple control clocks in response to at least one sequence signal and to at least one selection signal among multiple selection signals. Multiple shifting units (220-250) successively activate at least one output signal of the shifting units by shifting an input pulse when one control clock among the multiple control clocks corresponding to the shifting unit is activated. A signal transmission unit (260) transmits at least one output signal of one shifting unit, which corresponds to the activated selection signal among the multiple shifting units to at least one pulse signal. [Reference numerals] (211) Selection signal generating unit; (212) Clock delivery unit; (221) First unit shifting unit; (222) Second unit shifting unit; (223) Third unit shifting unit; (224) Fourth unit shifting unit; (231) Fifth unit shifting unit; (232) Sixth unit shifting unit; (233) Seventh unit shifting unit; (234) Eighth unit shifting unit; (241) Ninth unit shifting unit; (242) Tenth unit shifting unit; (243) Eleventh unit shifting unit; (244) Twelfth unit shifting unit; (251) Thirteenth unit shifting unit; (252) Fourteenth unit shifting unit; (253) Fifteenth unit shifting unit; (254) Sixteenth unit shifting unit; (261) First selecting unit; (262) Second selecting unit; (263) Third selecting unit; (264) Fourth selecting unit
摘要翻译：目的：提供脉冲信号发生电路，脉冲序列控制电路和数据输出电路，以减少在产生脉冲信号时同时工作的移位单元的数量，从而减少电力消耗量。构成：响应于至少一个序列信号和多个选择信号中的至少一个选择信号，控制单元（210）在多个控制时钟之间激活至少一个控制时钟。多个变速单元（220-250）通过在对应于变速单元的多个控制时钟中的一个控制时钟被激活时移位输入脉冲来连续地激活变速单元的至少一个输出信号。信号发送单元（260）将与多个移位单元中的激活的选择信号对应的一个移位单元的至少一个输出信号发送到至少一个脉冲信号。（附图标记）（211）选择信号生成单元; （212）时钟传送单元; （221）第一单元移位单元; （222）第二单元移位单元; （223）第三单位变速单元; （224）第四单位变速单元; （231）第五单元移位单元; （232）第六单元变速单元; （233）第七单位变速单元; （234）第八单位变速单位; （241）第九单元移位单元; （242）第十单元移位单元; （243）第十一单位变速单元; （244）第十二单元移位单元; （251）第十三单元移位单元; （252）第十四单元移位单元; （253）第十五单元移位单元; （254）第十六单元移位单元; （261）首选单元; （262）第二选择单元; （263）第三选单元; （264）第四选择单元

2. 发明公开

KR1020130022402A 복수의 모듈의 작동 방법 有权
标题翻译：激活多个模块的方法
公开(公告)号：KR1020130022402A
公开(公告)日：2013-03-06
申请号：KR1020127025708
申请日：2011-03-16
申请人： 로베르트 보쉬 게엠베하
发明人： 슈밋트슈테펜 , 바그너토마스 , 하니쉬위르겐
IPC分类号： H03K3/00 , G06F1/04 , G06F13/42 , H04L12/40
CPC分类号： H03K3/00 , G06F17/5022 , H04L12/40026 , H04L12/4035 , H04L2012/40241 , Y10T307/74 , G06F1/04 , G06F13/42
摘要： 본 발명은 복수의 모듈을 작동하기 위한 방법 및 회로 장치(10)에 관한 것이다. 상기 작동 방법은 유연한 트리거 메커니즘을 구현하는 상기 회로 장치(10)에 의해 실행된다.

3. 发明公开

KR1020120111526A 슈미트 트리거 회로 有权
标题翻译： SCHMITT触发电路
公开(公告)号：KR1020120111526A
公开(公告)日：2012-10-10
申请号：KR1020110030046
申请日：2011-04-01
申请人： 엘지디스플레이 주식회사
发明人： 이상용
IPC分类号： H03K3/027 , H03K3/3565
CPC分类号： H03K3/027 , H03K3/00 , H03K3/02 , H03K3/353 , H03K3/356 , H03K3/3565
摘要： PURPOSE: A Schmitt trigger circuit is provided to reduce a capacitance portion of an output terminal by using a diode connection of a MOS(Metal Oxide Semiconductor) transistor. CONSTITUTION: A first inverter(100) inverts an input voltage. A second inverter(200) generates an output voltage by inverting the output of the first inverter. A first p type transistor(MP1) includes a first source electrode connected to a first node, a first gate electrode, and a first drain electrode. A second p type transistor(MP2) comprises a second gate electrode, a second source electrode, and a second drain electrode connected to the first node. A first n type transistor(MN1) comprises a gate electrode, a source electrode connected to the second node, and a drain electrode connected to the second node. A second n type transistor(MN2) comprises a fourth gate electrode, a fourth source electrode, a fourth drain electrode connected to the second node.
摘要翻译：目的：提供施密特触发电路，通过使用MOS（金属氧化物半导体）晶体管的二极管连接来减小输出端子的电容部分。构成：第一反相器（100）反相输入电压。第二逆变器（200）通过使第一反相器的输出反相来产生输出电压。第一p型晶体管（MP1）包括连接到第一节点的第一源电极，第一栅极电极和第一漏极电极。第二p型晶体管（MP2）包括连接到第一节点的第二栅电极，第二源电极和第二漏电极。第一n型晶体管（MN1）包括栅电极，连接到第二节点的源电极和连接到第二节点的漏电极。第二n型晶体管（MN2）包括第四栅电极，第四源电极，连接到第二节点的第四漏电极。

4. 发明公开

KR20120044786A Receiver circuit of semiconductor apparatus and method for receiving a signal 无效
标题翻译：半导体装置的接收电路和接收信号的方法
公开(公告)号：KR20120044786A
公开(公告)日：2012-05-08
申请号：KR20100106276
申请日：2010-10-28
申请人： SK HYNIX INC
发明人： BYEON SANG YEON
IPC分类号： G11C7/22 , G11C7/06 , G11C7/10
CPC分类号： H03K3/00 , H03K3/0375 , H03K19/0175
摘要： PURPOSE: A receiver circuit of a semiconductor device and a signal receiving method are provided to improve the setup hold time of an output signal by outputting the output signal at the same point regardless of an input point of a clock signal and an input signal. CONSTITUTION: A receiver circuit includes a first sense amplifier(10), a first level limiting unit(100) and a second sense amplifier(20). The first sense amplifier generates a first signal with a swing voltage between a first level and a second level by amplifying an input signal. The level limiting unit generates a correction signal with a swing voltage between a first level and a third level by receiving a first signal.
摘要翻译：目的：提供半导体器件的接收器电路和信号接收方法，用于通过在时钟信号和输入信号的输入点输出相同点的输出信号来改善输出信号的建立保持时间。构成：接收器电路包括第一读出放大器（10），第一电平限制单元（100）和第二读出放大器（20）。第一读出放大器通过放大输入信号来产生具有在第一电平和第二电平之间的摆动电压的第一信号。电平限制单元通过接收第一信号产生具有在第一电平和第三电平之间的摆动电压的校正信号。

5. 发明授权

KR100829779B1 레벨 쉬프팅 회로 有权
标题翻译：水平移位电路
公开(公告)号：KR100829779B1
公开(公告)日：2008-05-16
申请号：KR1020070018133
申请日：2007-02-23
申请人： 삼성전자주식회사
发明人： 박동욱
IPC分类号： G11C7/10 , G11C5/14
CPC分类号： H03K3/00 , H03K3/35613
摘要： A level shifting circuit is provided to have equal duty ratios of output signals by obtaining equal delay time of a differential input signal by using a transmission gate. A level shifting part receives a differential pair of a first input signal and a second input signal swinging between a first voltage level and a second voltage level, and provides a differential pair of a first output signal and a second output signal swinging between the first voltage level and a third voltage level higher than the second voltage level. An output buffer part provides a third output signal and a fourth output signal by inverting the first output signal and the second output signal. Duty ratio of the first output signal and the second output signal outputted from the level shifting part is controlled on the basis of delay time of the first input signal and the second input signal. The level shifting part includes an output part(480) providing the first and the second output signal, a delay control part(470) controlling delay time of the first and the second input signal, and an input part(460) providing the first and the second input signal to the delay control part.
摘要翻译：提供电平移位电路以通过使用传输门获得差分输入信号的相等延迟时间来具有输出信号的相等占空比。电平移位部分接收在第一电压电平和第二电压电平之间摆动的第一输入信号和第二输入信号的差分对，并且提供在第一电压和第二电压之间摆动的第一输出信号和第二输出信号的差分对，电平和第三电压电平高于第二电压电平。输出缓冲器部分通过使第一输出信号和第二输出信号反相来提供第三输出信号和第四输出信号。基于第一输入信号和第二输入信号的延迟时间来控制从电平转换部分输出的第一输出信号和第二输出信号的占空比。电平移位部分包括提供第一和第二输出信号的输出部分（480），控制第一和第二输入信号的延迟时间的延迟控制部分（470）和提供第一和第二输出信号的输入部分（460）第二输入信号到延迟控制部分。

6. 发明公开

KR1020050086787A 전류 구동회로 및 이것을 사용한 표시장치 有权
标题翻译：电流驱动电路和显示使用相同
公开(公告)号：KR1020050086787A
公开(公告)日：2005-08-30
申请号：KR1020057009380
申请日：2003-11-27
申请人： 가부시키가이샤 한도오따이 에네루기 켄큐쇼
发明人： 키무라하지메
IPC分类号： G09G3/30 , G09G3/20 , G09G3/32
CPC分类号： H03K3/00 , G09G3/3233 , G09G3/325 , G09G3/3283 , G09G2300/0842 , G09G2300/0852 , G09G2300/0861 , G09G2300/0866 , G09G2310/0248 , G09G2320/0223 , G09G2320/0252 , G09G2320/0295 , G09G2320/043
摘要： A current drive circuit wherein the signal writing speed and the device driving speed can be improved even when a signal current is small and a display using such a current drive circuit are disclosed. A current drive circuit for supplying a signal current to a node of a circuit to be driven through a signal line is provided with a precharge means for supplying a precharge voltage to the node through the signal line. The precharge means comprises a supply means for supplying the precharge voltage to the node and the signal line before the supply of the signal current.
摘要翻译：即使在信号电流小的情况下也能够提高信号写入速度和器件驱动速度的电流驱动电路，并且公开了使用这种电流驱动电路的显示。用于向通过信号线驱动的电路的节点提供信号电流的电流驱动电路设置有用于通过信号线向节点提供预充电电压的预充电装置。预充电装置包括用于在提供信号电流之前向节点和信号线提供预充电电压的供电装置。

7. 发明授权

KR101907073B1 펄스신호 생성회로, 버스트 오더 제어회로 및 데이터 출력회로 有权
公开(公告)号：KR101907073B1
公开(公告)日：2018-10-11
申请号：KR1020110140385
申请日：2011-12-22
申请人： 에스케이하이닉스 주식회사
发明人： 김광현
IPC分类号： G11C11/4096 , G11C11/4093 , G11C11/4076
CPC分类号： G06F1/12 , G06F1/06 , G11C7/1018 , G11C7/1042 , G11C7/1072 , G11C7/222 , G11C11/4076 , G11C11/4096 , H03K3/00
摘要： 본기술은반도체장치의전류및 전력소모를줄이기위한것으로본 기술에따른펄스신호생성회로는하나이상의순서신호에응답하여다수의제어클럭중 하나이상의제어클럭을활성화하고, 다수의선택신호중 하나이상의선택신호를활성화하는제어부; 각각하나이상의출력신호를생성하되상기다수의제어클럭중 자신에게대응하는제어클럭이활성화되면입력펄스를쉬프팅하여자신의상기하나이상의출력신호를순차로활성화하는다수의쉬프팅부; 및상기다수의쉬프팅부중 상기활성화된선택신호에대응하는쉬프팅부의상기하나이상의출력신호를하나이상의펄스신호로전달하는신호전달부를포함한다.

8. 发明授权

KR101874414B1 하이측 게이트 드라이버, 스위칭 칩, 및 전력 장치 有权
公开(公告)号：KR101874414B1
公开(公告)日：2018-07-04
申请号：KR1020120035598
申请日：2012-04-05
申请人： 삼성전자주식회사
发明人： 최현식 , 김호정 , 신재광 , 정우인
IPC分类号： H03K17/687 , H02M1/08
CPC分类号： H03K3/00 , G05F3/02 , H01L2924/0002 , H03K17/06 , H01L2924/00
摘要： 보호소자를포함하는하이측게이트드라이버, 스위칭칩, 및전력장치가제공된다. 이를위해본 발명은, 하이측노말리-온스위치를턴 오프시키기위해제공된제1 로우레벨구동전원, 및제1 로우레벨구동전원과하이측노말리-온스위치의게이트사이에직렬로연결된보호소자및 제1 스위칭소자를포함하는하이측게이트드라이버와이를포함하는전력장치를제공한다. 또한, 본발명은동일한구조로구현된하이측노말리-온스위치, 추가노말리-온스위치, 및로우측노말리-온스위치를포함하는스위칭칩을제공한다.

9. 发明公开

KR1020130135507A 스테이지 회로 및 이를 이용한 주사 구동부 审中-实审
标题翻译：阶段电路和扫描驱动器使用它
公开(公告)号：KR1020130135507A
公开(公告)日：2013-12-11
申请号：KR1020120059120
申请日：2012-06-01
申请人： 삼성디스플레이 주식회사
发明人： 정경훈
IPC分类号： G09G3/30
CPC分类号： H03K3/00 , G09G3/003 , G09G3/3266 , G09G2310/0224
摘要： The present invention relates to a stage circuit which supplies a scan signal with a simultaneous or interlace method. The stage circuit according to the present invention includes: a sequence driving unit which outputs the scan signal to an output terminal by corresponding to a plurality of clock signals which are simultaneously or successively supplied and is disconnected to the output terminal when a third control signal is supplied; and a simultaneous driving unit which outputs the scan signal to the output terminal by corresponding to a first control signal and a second control signal which are not overlapped and is disconnected to the output terminal when a fourth control signal which does not overlap the third control signal is supplied.
摘要翻译：本发明涉及一种以同时或交错方式提供扫描信号的级电路。根据本发明的电路电路包括：序列驱动单元，其通过对应于同时或连续提供的多个时钟信号将输出端子输出到输出端子，并且当第三控制信号为供给; 以及同时驱动单元，当不与第三控制信号重叠的第四控制信号时，对应于不重叠的第一控制信号和第二控制信号将扫描信号输出到输出端，被提供。

10. 发明公开

KR1020130129788A 출력드라이버회로 审中-实审
标题翻译：输出驱动电路
公开(公告)号：KR1020130129788A
公开(公告)日：2013-11-29
申请号：KR1020120053909
申请日：2012-05-21
申请人： 에스케이하이닉스 주식회사
发明人： 백창기
IPC分类号： G11C7/10 , G11C5/14
CPC分类号： H03K3/00 , H03K19/00384
摘要： An output driver circuit includes: a driving control signal generating unit which generates first and second driving control signals and first and second inversion driving control signals by comparing a power voltage with a reference voltage; a pre-driving unit which drives a pull-up driving signal and a pull-down driving signal with a driving intensity which is set according to the first and second driving control signals and the first and second inversion driving control signals; and a driving unit which drives output data in response to the pull-up driving signal and the pull-down driving signal. [Reference numerals] (1) Driving control signal generating unit;(2) Pre-driving unit;(3) Driving unit
摘要翻译：输出驱动电路包括：驱动控制信号产生单元，通过将电源电压与参考电压进行比较来产生第一和第二驱动控制信号以及第一和第二反相驱动控制信号; 驱动单元，其驱动具有根据第一和第二驱动控制信号以及第一和第二反转驱动控制信号设置的驱动强度的上拉驱动信号和下拉驱动信号; 以及驱动单元，其响应于上拉驱动信号和下拉驱动信号来驱动输出数据。（附图标记）（1）驱动控制信号生成单元;（2）预驱动单元;（3）驱动单元

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