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1. 发明授权

KR101556573B1 부트스트랩 회로 有权
标题翻译： BOOTSTRAP电路
公开(公告)号：KR101556573B1
公开(公告)日：2015-10-01
申请号：KR1020090010076
申请日：2009-02-09
申请人： 소니 주식회사
发明人： 진타세이이치로
IPC分类号： G11C19/00 , G11C8/04
CPC分类号： H03K19/017
摘要： 동일도전형의제1 내지제3 트랜지스터로구성되고, 제3 트랜지스터가오프상태가되면제1 트랜지스터의게이트전극과제3 트랜지스터의한쪽의소스/드레인영역을접속하는노드부가부유상태가되고, 제2 트랜지스터의게이트전극은 2상의클록신호중 다른한쪽을전달하는클록공급선에접속되고, 노드부와제1 전위공급선사이에전위변동억제용량부가구비되는부트스트랩회로가공개된다.

2. 发明公开

KR1020050030779A 디바이스의 입출력 장치 无效
标题翻译：设备的输入和输出设备
公开(公告)号：KR1020050030779A
公开(公告)日：2005-03-31
申请号：KR1020030066937
申请日：2003-09-26
申请人： 삼성전자주식회사
发明人： 최정환
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K19/017 , H04L25/0264
摘要： An apparatus for inputting and outputting at the device is provided to reduce the number of channel required to the signal transmission and reception by using the full differential method when the device is operated at the normal mode and by using the pseudo differential method when the device is operated at the test mode. An apparatus for inputting and outputting at the device includes an input unit(301) and an output unit. The input unit(301) generates the non-inverted input data and the inverted input data by receiving the non-inverted data and the inverted data from each channel pair during the normal mode, wherein the first channel receives the non-inverted data and the second channel receives the inverted data. The input unit(301) generates the non-inverted input data and the inverted input data by receiving the non-inverted data and the reference voltage from each channel pair during the test mode. The output unit transmits the non-inverted output data to the first channel and transmits the inverted output data to the second channel during the normal mode. During the test mode, the output unit transmits the non-inverted data to the first channel and does not transmit the non-inverted data to the second channel.
摘要翻译：提供一种用于在设备处输入和输出的装置，用于当设备在正常模式下操作时通过使用全差分方法来减少信号发送和接收所需的信道数量，并且当设备为在测试模式下运行。一种用于在设备处输入和输出的装置包括输入单元（301）和输出单元。输入单元（301）在正常模式期间通过从每个通道对接收非反相数据和反相数据来产生非反相输入数据和反相输入数据，其中第一通道接收非反转数据，第二通道接收反相数据。输入单元（301）通过在测试模式期间从每个通道对接收非反相数据和参考电压来产生非反相输入数据和反相输入数据。输出单元将非反相输出数据发送到第一通道，并且在正常模式期间将反相输出数据发送到第二通道。在测试模式期间，输出单元将非反相数据发送到第一通道，并且不将非反相数据发送到第二通道。

3. 发明公开

KR1020170003420A 로직 회로, 반도체 장치, 전자 부품, 및 전자 기기 审中-实审
标题翻译：逻辑电路半导体器件电子元件和电子器件
公开(公告)号：KR1020170003420A
公开(公告)日：2017-01-09
申请号：KR1020160080003
申请日：2016-06-27
申请人： 가부시키가이샤 한도오따이 에네루기 켄큐쇼
发明人： 다무라히카루
IPC分类号： H03K19/0948 , H03K19/096 , H03K17/06
CPC分类号： H03K19/0013 , H01L27/1225 , H01L29/7869 , H03K19/017
摘要： 본발명의과제는로직회로의구동능력을향상시키는것이다. 로직회로는, 제 1 출력노드, 다이내믹로직회로, 다이오드접속된제 1 트랜지스터, 및용량소자를갖는다. 다이내믹로직회로는제 2 출력노드, 및복수의제 2 트랜지스터를갖는다. 제 1 트랜지스터및 복수의제 2 트랜지스터의도전형은 n형및 p형중 어느한쪽이다. 용량소자의한쪽의단자는제 1 출력노드와, 다른쪽의단자는제 2 출력노드와전기적으로접속된다. 제 1 트랜지스터의제 1 단자는제 1 출력노드와전기적으로접속되고, 제 1 트랜지스터의제 2 단자에는제 1 전압이입력된다. 제 1 트랜지스터의백게이트의전압에따라, 제 1 출력노드의전압이변화된다.
摘要翻译：提高了逻辑电路的驱动能力。逻辑电路包括第一输出节点，动态逻辑电路，二极管连接的第一晶体管和电容器。动态逻辑电路包括第二输出节点和多个第二晶体管形成和评估电路。第一晶体管和多个第二晶体管都具有n型导电性和p型导电性之一。电容器的一个端子电连接到第一输出节点。电容器的另一个端子电连接到第二输出节点。第一晶体管的第一端子电连接到第一输出节点。第一电压被输入到第一晶体管的第二端子。第一输出节点的电压通过施加到第一晶体管的背栅极的电压而改变。

4. 发明授权

KR101096466B1 고속 데이터 레이트에서 오프-칩 데이터 통신을 수행하는 시스템 및 방법 有权
标题翻译：用于在高数据速率下执行片外数据通信的系统和方法
公开(公告)号：KR101096466B1
公开(公告)日：2011-12-20
申请号：KR1020097023943
申请日：2008-04-18
申请人： 퀄컴 인코포레이티드
发明人： 모한비베크 , 디시트아브하이
IPC分类号： H04L25/02 , G06F15/163
CPC分类号： H04L25/0292 , H03K19/017 , H04L25/0272
摘要： 전자 디바이스가 설명된다. 그 전자 디바이스는 제 1 집적회로 (IC) 및 제 2 집적회로 (IC) 를 포함한다. 또한, 그 전자 디바이스는 병렬 데이터 신호를 직렬 데이터 신호로 멀티플렉싱하도록 구성된 멀티플렉서, 및 직렬 데이터 신호를 제 1 IC 로부터 제 2 IC 로 송신하도록 구성된 송신기를 포함한다. 그 전자 디바이스는 직렬 데이터 신호를 수신하도록 구성된 수신기를 더 포함한다. 수신기는 아날로그 노드의 전압 스윙을 결정된 범위 내로 클램핑하도록 구성된 클램프 회로를 포함한다. 또한, 클램프는 수신기의 대역폭을 확장하는 것을 돕는다.
오프-칩 데이터 통신, 고속 데이터 레이트, 전압 스윙

5. 发明公开

KR1020090086357A 부트스트랩 회로 有权
标题翻译： BOOTSTRAP电路
公开(公告)号：KR1020090086357A
公开(公告)日：2009-08-12
申请号：KR1020090010076
申请日：2009-02-09
申请人： 소니 주식회사
发明人： 진타세이이치로
IPC分类号： G11C19/00 , G11C8/04
CPC分类号： H03K19/017
摘要： A bootstrap circuit is provided to prevent a malfunction by decreasing sudden change by the parasitic capacitance. In a bootstrap circuit, one of source and drain region of the first transistor(Tr1) and one of the source and drain of the second transistor(Tr2) are connected each other through output unit. The other one of source and drain region of the first transistor is connected to a clock line. One of the source and drain of the gate electrode of the first transistor and one of the source and drain of third transistor(Tr3) are connected with each other through a node portion. The other one is connected to the first voltage supply line(PS1) of source and drain region of the second transistor.
摘要翻译：提供自举电路以通过减小寄生电容的突然变化来防止故障。在自举电路中，第一晶体管（Tr1）的源极和漏极区域中的一个以及第二晶体管（Tr2）的源极和漏极中的一个通过输出单元彼此连接。第一晶体管的源极和漏极区域中的另一个连接到时钟线。第一晶体管的栅电极和第三晶体管（Tr3）的源极和漏极之一的源极和漏极之一通过节点部分彼此连接。另一个连接到第二晶体管的源极和漏极区的第一电压源线（PS1）。

6. 发明授权

KR1019930000479B1 반도체 집적회로 失效
标题翻译：半导体芯片
公开(公告)号：KR1019930000479B1
公开(公告)日：1993-01-21
申请号：KR1019840004096
申请日：1984-07-12
申请人： 가부시끼가이샤 히다치 세이사꾸쇼
发明人： 니시하라모도히사 , 이와무라마사히로 , 마스다이꾸로우
IPC分类号： H03K19/00
CPC分类号： H03K19/09448 , H03K19/017
摘要： 내용 없음.

7. 发明公开

KR1020120051918A 반도체 장치의 스위칭 회로 有权
标题翻译：半导体设备的切换电路
公开(公告)号：KR1020120051918A
公开(公告)日：2012-05-23
申请号：KR1020100113290
申请日：2010-11-15
申请人： 에스케이하이닉스 주식회사
发明人： 최원범
IPC分类号： G11C7/10 , G11C5/14
CPC分类号： H03K17/102 , H03K17/693 , H03K19/017 , H03K2217/0018 , H03K17/30 , G11C5/14 , H03K17/145 , H03K19/0175
摘要： PURPOSE: A switching circuit of a semiconductor device is provided to improve a driving speed of the semiconductor device by including a preventing unit in a first switching unit. CONSTITUTION: A first switching unit(120) prevents a leakage current applied from the outside and switches a first signal with a first high voltage bias. A second switching unit(140) switches a second signal with a second high voltage bias according to a first high voltage bias level. The first and second switching units generate a global bias signal through selective switching by a first enable signal and a second enable signal applied from the outside.
摘要翻译：目的：提供半导体器件的开关电路，通过在第一开关单元中包括防止单元来提高半导体器件的驱动速度。构成：第一开关单元（120）防止从外部施加的漏电流并且以第一高电压偏压来切换第一信号。第二开关单元（140）根据第一高电压偏置电平用第二高电压偏压切换第二信号。第一和第二开关单元通过通过从外部施加的第一使能信号和第二使能信号的选择性切换来产生全局偏置信号。

8. 发明公开

KR1020120042505A 레벨 시프트 회로 有权
标题翻译：水平移位电路
公开(公告)号：KR1020120042505A
公开(公告)日：2012-05-03
申请号：KR1020100104220
申请日：2010-10-25
申请人： 주식회사 에이디텍
发明人： 김성렬 , 류동열 , 이병찬
IPC分类号： H03K19/0185
CPC分类号： H03K19/018521 , H03K19/0013 , H03K19/017
摘要： PURPOSE: A level shift circuit is provided to improve the driving strength of an output switching apparatus by using a low voltage device for a latch and a gate driver in a shifter circuit. CONSTITUTION: An input circuit(210) outputs an in-phase input signal having an in-phase and an inversion input signal having an inverted phase by receiving an input signal having a voltage level between a first driving voltage and a ground voltage. A shifter circuit(220) changes the in-phase input signal and an inversion input signal outputted from the input circuit to an output signal having a voltage level between the ground voltage and a second driving voltage which higher than the first driving voltage. A gate driver(230) outputs a driving signal by receiving the output signal. An output switching apparatus(240) outputs a switching voltage by receiving the driving signal outputted from the gate driver.
摘要翻译：目的：提供一种电平移位电路，通过使用用于锁存器的低电压装置和移位电路中的栅极驱动器来提高输出开关装置的驱动强度。构成：输入电路（210）通过接收具有第一驱动电压和接地电压之间的电压电平的输入信号，输出具有反相的同相输入信号和反相输入信号。移位器电路（220）将同相输入信号和从输入电路输出的反相输入信号改变为具有接地电压和高于第一驱动电压的第二驱动电压之间的电压电平的输出信号。栅极驱动器（230）通过接收输出信号来输出驱动信号。输出开关装置（240）通过接收从栅极驱动器输出的驱动信号来输出开关电压。

9. 发明公开

KR1020090115472A 동적 전류-모드 로직 회로 无效
标题翻译：动态电流模式逻辑电路
公开(公告)号：KR1020090115472A
公开(公告)日：2009-11-05
申请号：KR1020080041355
申请日：2008-05-02
申请人： 삼성전자주식회사
发明人： 송진석
IPC分类号： H03K19/094
CPC分类号： H03K19/09432 , H03K19/0013 , H03K19/017
摘要： PURPOSE: A dynamic current-mode logic circuit is provided to reduce current of a short circuit in static mode at high speed by using a logic gate with a new structure. CONSTITUTION: In a dynamic current-mode logic circuit, an MOS current-mode logic block(DLT) includes differential input terminals and differential output terminals. The MOS current-mode logic block performs an evaluation operation of the differential input signals in an evaluation step. Precharge circuit(Q2,Q3,Q4) precharge voltage levels of differential output terminals to the voltage level of the electric power supply in a precharge step. The precharge circuit connects a virtual ground node and a ground node within an activation range during of an pulse signal. A first switch circuit separates a current output terminal and a virtual ground node of the MOS current-mode logic block in the precharge step.
摘要翻译：目的：提供一种动态电流模式逻辑电路，通过使用具有新结构的逻辑门，以高速度降低静态模式下的短路电流。构成：在动态电流模式逻辑电路中，MOS电流模式逻辑块（DLT）包括差分输入端子和差分输出端子。 MOS电流模式逻辑块在评估步骤中执行差分输入信号的评估操作。预充电电路（Q2，Q3，Q4）在预充电步骤中将差分输出端子的预充电电压电平调节到电源的电压电平。在脉冲信号期间，预充电电路将虚拟接地节点和接地节点连接在激活范围内。第一开关电路在预充电步骤中分离MOS电流模式逻辑块的电流输出端子和虚拟接地节点。

10. 发明公开

KR1020090007210A 레벨 시프트 회로 失效
标题翻译：水平移位电路
公开(公告)号：KR1020090007210A
公开(公告)日：2009-01-16
申请号：KR1020080057442
申请日：2008-06-18
申请人： 야마하 가부시키가이샤
发明人： 츠지노부아키 , 카와이히로타카
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K3/356113 , H03K19/017
摘要： A level shift circuit is provided to protect the low voltage transistor by regularly maintaining the source voltage of the high voltage transistor. A level shift circuit(100) converts a high voltage power source(VH) into the output signal(OUT1 and OUT2) of the high voltage. A latch circuit(20) controls the operation of supplying the high voltage power source. An input-output circuit(70) comprises the high voltage transistor, the low voltage transistor and the second diode. A stable-currents circuit(30) controls the voltage of A-point. A first diode(40) and a second diode(50) are installed in the stable-currents circuit. One end of the first diode is earthed. The other end of the first diode is connected to the point B. One end of the second diode is connected to the source of the high voltage transistor. The other end of the first diode is earthed. The stable-currents circuit is comprised of the high voltage transistor(HP1) and the constant voltage circuit. The source of the high voltage transistor is connected to the high voltage power source(VH). A current mirror circuit(60) comprises the high voltage transistor.
摘要翻译：提供电平移位电路以通过定期维持高电压晶体管的源极电压来保护低压晶体管。电平移位电路（100）将高压电源（VH）转换成高电压的输出信号（OUT1和OUT2）。锁存电路（20）控制供给高电压电源的动作。输入输出电路（70）包括高压晶体管，低压晶体管和第二二极管。稳定电流电路（30）控制A点的电压。第一二极管（40）和第二二极管（50）安装在稳流电路中。第一个二极管的一端接地。第一二极管的另一端连接到点B.第二二极管的一端连接到高电压晶体管的源极。第一个二极管的另一端接地。稳定电流电路由高压晶体管（HP1）和恒压电路构成。高压晶体管的源极连接到高压电源（VH）。电流镜电路（60）包括高压晶体管。

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