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    • 2. 发明公开
    • 레벨 시프트 회로
    • 水平移位电路
    • KR1020120042505A
    • 2012-05-03
    • KR1020100104220
    • 2010-10-25
    • 주식회사 에이디텍
    • 김성렬류동열이병찬
    • H03K19/0185
    • H03K19/018521H03K19/0013H03K19/017
    • PURPOSE: A level shift circuit is provided to improve the driving strength of an output switching apparatus by using a low voltage device for a latch and a gate driver in a shifter circuit. CONSTITUTION: An input circuit(210) outputs an in-phase input signal having an in-phase and an inversion input signal having an inverted phase by receiving an input signal having a voltage level between a first driving voltage and a ground voltage. A shifter circuit(220) changes the in-phase input signal and an inversion input signal outputted from the input circuit to an output signal having a voltage level between the ground voltage and a second driving voltage which higher than the first driving voltage. A gate driver(230) outputs a driving signal by receiving the output signal. An output switching apparatus(240) outputs a switching voltage by receiving the driving signal outputted from the gate driver.
    • 目的:提供一种电平移位电路,通过使用用于锁存器的低电压装置和移位电路中的栅极驱动器来提高输出开关装置的驱动强度。 构成:输入电路(210)通过接收具有第一驱动电压和接地电压之间的电压电平的输入信号,输出具有反相的同相输入信号和反相输入信号。 移位器电路(220)将同相输入信号和从输入电路输出的反相输入信号改变为具有接地电压和高于第一驱动电压的第二驱动电压之间的电压电平的输出信号。 栅极驱动器(230)通过接收输出信号来输出驱动信号。 输出开关装置(240)通过接收从栅极驱动器输出的驱动信号来输出开关电压。
    • 3. 发明授权
    • ESD 보호 회로
    • ESD保护电路
    • KR100876549B1
    • 2008-12-31
    • KR1020070078809
    • 2007-08-07
    • 주식회사 에이디텍
    • 김성렬
    • H01L23/60H01L27/04
    • H03K17/08104H01L27/0262H01L27/0266H03K19/00315
    • The ESD protecting circuit is provided to reduce the area which the ESD protecting circuit occupies in the semiconductor chip between power supplies. The ESD(Electro-Static Discharge) protection circuit(500) comprises the NPN bipolar transistor(Q1), the first resistance(R1), and the first diode(D3). The NPN bipolar transistor has the emitter terminal connected to the first node(N1) in which the first supply voltage(VCC1) is applied. The NPN bipolar transistor has the collector terminal connected to the second Node(N2) in which the second supply voltage(VCC2) is applied. The first resistance has one terminal connected to the base terminal of the NPN bipolar transistor. The first resistance has the other one terminal connected to the emitter terminal. One terminal of the first diode is connected to the second node. The first diode has the other one terminal connected to the ground voltage.
    • 提供ESD保护电路以减少ESD保护电路在电源之间在半导体芯片中占据的面积。 ESD(静电放电)保护电路(500)包括NPN双极晶体管(Q1),第一电阻(R1)和第一二极管(D3)。 NPN双极晶体管的发射极端子连接到施加第一电源电压(VCC1)的第一节点(N1)。 NPN双极晶体管的集电极端子连接到施加第二电源电压(VCC2)的第二节点(N2)。 第一个电阻有一个端子连接到NPN双极晶体管的基极端子。 第一个电阻的另一个端子连接到发射极端子。 第一个二极管的一个端子连接到第二个节点。 第一个二极管的另一个端子连接到地电压。
    • 6. 发明公开
    • 펄스 충전 기법을 이용한 소프트 스타트 회로
    • 使用脉冲充电方法的软启动电路
    • KR1020130039278A
    • 2013-04-19
    • KR1020110103831
    • 2011-10-11
    • 주식회사 에이디텍충북대학교 산학협력단
    • 양병도김성렬류동렬민제중성시우오재문천유소
    • H03K17/28G05F1/44H02M3/28
    • H03K17/284H02M1/36H03K5/133
    • PURPOSE: A soft start circuit using pulse charging techniques is provided to reduce the overall size of a chip by using a small capacitor capable of obtaining the effect of a big capacitor and to improve stability and reliability by increasing the soft start switch time. CONSTITUTION: A pulse generator(310) receives a first CLK signal and generates a pulse signal by responding to an enable signal. A delay unit(320) receives the pulse signal and is charged with voltage by responding to the enable signal. A comparison unit(330) outputs a charging completion signal by detecting the comparison voltage charged in the delay unit. When a signal inputted to the delay unit is a comparison voltage, the charging completion signal of the delay unit is displayed as high if the comparison voltage is higher than a reference voltage(Vref). The pulse generator stops generating the pulse signal, and the delay unit stops being charged when the charging completion signal is high. [Reference numerals] (310) Pulse generator; (320) Delay unit; (330) Comparison unit; (AA) First CLK signal; (BB) Enable signal; (CC) Pulse signal; (DD) Charging completion signal; (EE) Comparison voltage;
    • 目的:提供使用脉冲充电技术的软启动电路,通过使用能够获得大电容器的效果的小电容器来减小芯片的总体尺寸,并通过增加软启动开关时间来提高稳定性和可靠性。 构成:脉冲发生器(310)接收第一CLK信号并通过响应使能信号产生脉冲信号。 延迟单元(320)接收脉冲信号并通过响应于使能信号对电压进行充电。 比较单元(330)通过检测在延迟单元中充电的比较电压来输出充电完成信号。 当输入到延迟单元的信号是比较电压时,如果比较电压高于参考电压(Vref),则延迟单元的充电完成信号被显示为高。 脉冲发生器停止产生脉冲信号,并且当充电完成信号为高时,延迟单元停止充电。 (附图标记)(310)脉冲发生器; (320)延迟单位; (330)比较单位; (AA)第一个CLK信号; (BB)使能信号; (CC)脉冲信号; (DD)充电完成信号; (EE)比较电压;
    • 7. 发明公开
    • 전하 공유방식을 이용한 보상 장치
    • 使用充电共享的补偿装置
    • KR1020130096774A
    • 2013-09-02
    • KR1020120016495
    • 2012-02-17
    • 주식회사 에이디텍충북대학교 산학협력단
    • 양병도김성렬이병찬정훈식오재문성동진천유소
    • G05F1/70H02M3/00
    • PURPOSE: A compensation device using a charge sharing method removes a compensation circuit connection pin by integrating a capacitor of a compensation device into a chip with a stable method. CONSTITUTION: A first amplifier (100) receives a reference voltage and a comparison voltage and outputs the same to an output terminal. One side of a first switch unit (200) is connected to the output terminal of the first amplifier. One side of a second capacitor unit (300) is connected to the other side of the switch unit. One side of a first capacitor (500) is connected to the output terminal of the first amplifier. One side of a second switch unit (600) is connected to the other side of the first capacitor. One side of a third capacitor (800) is connected to the other side of the second switch unit. The other sides of the second capacitor unit and the third capacitor are connected to a ground voltage and integrated on one chip.
    • 目的:使用电荷共享方法的补偿装置通过将补偿装置的电容器以稳定的方法集成到芯片中来去除补偿电路连接引脚。 构成:第一放大器(100)接收参考电压和比较电压,并将其输出到输出端子。 第一开关单元(200)的一侧连接到第一放大器的输出端子。 第二电容器单元(300)的一侧连接到开关单元的另一侧。 第一电容器(500)的一侧连接到第一放大器的输出端子。 第二开关单元(600)的一侧连接到第一电容器的另一侧。 第三电容器(800)的一侧连接到第二开关单元的另一侧。 第二电容器单元和第三电容器的另一侧连接到地电压并集成在一个芯片上。
    • 8. 发明授权
    • 레벨 시프트 회로
    • 电平移位电路
    • KR101162697B1
    • 2012-07-05
    • KR1020100104220
    • 2010-10-25
    • 주식회사 에이디텍
    • 김성렬류동열이병찬
    • H03K19/0185
    • 본 발명은 고전압 소자 대신 저전압 소자를 사용하여 동작 전원의 크기가 낮아도 빠른 스위칭 동작을 할 수 있으며, 회로의 구성이 용이하고, 구동 능력이 향상된 레벨 시프트 회로에 관한 것이다.
      본 발명에 따른 레벨 시프트 회로는, 접지전압(GND)과 제1구동전압(V
      D1 ) 사이의 전압 레벨을 갖는 입력신호(V
      IN1 )를 입력받아 동일한 위상을 갖는 동일위상입력신호(V
      IN ) 및 반전된 위상을 갖는 반전입력신호(V
      INB )를 출력하는 입력회로(210), 상기 입력회로에서 출력된 동일위상입력신호(V
      IN ) 및 반전된 입력신호(V
      INB )를 입력받아 접지전압(GND)과 상기 제1구동전압(V
      D1 )보다 높은 전압인 제2구동전압(V
      D2 ) 사이의 전압 레벨을 갖는 출력신호(V
      OUT )로 변환하는 쉬프트회로(220), 상기 출력신호(V
      OUT )를 입력받아 구동신호(V
      G )를 출력하는 게이트 드라이버(230) 및 상기 게이트 드라이버로부터 출력된 구동신호(V
      G )를 입력받아 스위칭전압(V
      SW )을 출력하는 출력 스위칭 장치(240)를 구비하는 것을 특징으로 한다.